This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics
Single-Carrier Phase-Disposition PWM
Implementation for Multilevel Flying Capacitor
Converters
Amer M. Y. M. Ghias, Member, IEEE, Josep Pou, Senior Member, IEEE, Gabriel J. Capella,
Vassilios G. Agelidis, Senior Member, IEEE, Ricardo P. Aguilera, Member, IEEE,
and Thierry Meynard, Member, IEEE
Abstract—This letter proposes a new implementation of phase-
disposition pulse-width modulation (PD-PWM) for multilevel
flying capacitor (FC) converters using a single triangular carrier.
The proposed implementation is much simpler than conventional
PD-PWM techniques based on multiple trapezoidal shaped carri-
ers, generates the same results as far as natural capacitor voltage
balance is concerned and offers better quality line-to-line voltages
when compared to phase-shifted PWM. The proposed algorithm
is based on re-shaping the reference signal to fit within the range
of a single carrier and assigning each crossing of the reference
signal with the carrier to a particular pair of switches at any time.
The proposed algorithm is suitable for digital implementation
taking maximum benefit from the PWM units available in the
processor. Simulation and experimental results are presented
from the five-level FC Converter to verify the proposed PD-PWM
implementation.
Index Terms—Multilevel converter; Flying capacitor converter;
Natural Voltage control; Pulse-width modulation
I. I NTRODUCTION
M ULTILEVEL converters have attracted significant in-
terest for medium/high power applications [1]–[3].
Among various multilevel converter topologies [4], the flying
capacitor (FC) converter [5] offers some advantages over
the neutral-point-clamped (NPC) converter [6], such as that
capacitor voltage balance can be achieved without producing
low frequency voltage ripples in the FCs, even in converters
with a large number of levels.
Phase-shifted pulse-width modulation (PS-PWM) is a com-
mon technique applied to FC converters. PS-PWM provides
natural capacitor voltage balance but the quality of line-to-line
voltages is not the best. On the other hand, phase-disposition
PWM (PD-PWM) produces better line-to-line voltages than
This work was supported by the University of New South Wales, Australia
Energy Research Institute, and the School of Electrical engineering and
Telecommunications.
A. M. Y. M. Ghias, J. Pou, V. G. Agelidis, and R. P. Aguilera are with
Australian Energy Research Institute & School of Electrical Engineering and
Telecommunications, The University of New South Wales, Sydney, NSW
2052, Australia (email: amer.ghias@student.unsw.edu.au; j.pou@unsw.edu.au;
vassilios.agelidis@unsw.edu.au; ricardo.aguilera@unsw.edu.au).
G.J.Capella is with the Department of Electronic Engineer-
ing, Technical University of Catalonia, Terrassa 08222, Spain
(gabriel.jose.capella@upc.edu).
T. Meynard is with the Laboratoire d’Electrotechnique et d’Electronique
Industrielle (LEEI), Institut National Polytechnique de Toulouse, Toulouse
31000, France, and also with Cirtem SA, Toulouse 31047, France
(thierry.meynard@laplace.univ-tlse.fr).
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1
PS-PWM, but it cannot be applied straightforward to the FC
converter. Some solutions are based on modifying the shapes
of the carriers to produce PD-PWM [7], [8]. However, each
cell requires different carriers, which complicates its practical
implementation, especially for FC converters with a large
number of levels. The technique was simplified in [9], and
the number of carriers was reduced from (n − 1)2 to (n − 1),
which is the standard number of carriers used in PD-PWM.
The main drawback is that it requires a lot of digital signal
power processing.
The property of natural capacitor voltage balance in FC
converters can be boosted by the addition of RLC filters
connected to the output of the converter [10]–[12]. Closed-
loop voltage balancing methods have also been reported in
the technical literature [13]–[19].
This letter proposes a new implementation of PD-PWM
for the FC converter. Unlike in [7]–[10], the proposed PD-
PWM implementation uses a single triangular carrier for the
modulation. Tables or masks containing digital information are
used to process the PWM pulses. It is very simple to apply
and can be easily programmed in a digital processor requiring
only a single PWM unit. The technique can be extended to
FC converters with any number of levels.
The letter is organized as follows. Section II describes
the operating principle of a FC converter and the PD-PWM
technique. Section III introduces the proposed PD-PWM im-
plementation. Section IV presents simulation and experimental
results obtained from a three-phase five-level FC converter.
Finally, the conclusions are summarized in Section V.
II. FC C ONVERTER AND PD-PWM
A. Fundamentals
Fig. 1 shows a phase-leg of an n-level FC converter,
which integrates n-2 FCs. The subscript x is used for the
phase identification x = {a, b, c}. The switch pairs in each
phase-leg sx1 − s̄x1 , sx2 − s̄x2 ,..., and sxn−1 − s̄xn−1 operate
in a complementary manner. During normal operation, the
mean voltage values of the FCs, Cx1 , Cx2 ,..., and Cxn−2 ,
should be maintained at Vdc /(n − 1), 2Vdc /(n − 1),..., and
(n − 2)Vdc /(n − 1), respectively, where Vdc is the dc-bus
voltage. Consequently, the voltage across each switch is only
1/(n − 1) of the dc-bus voltage. Each converter phase-leg
can generate n − 1 output voltage levels, i.e. 0, Vdc /(n − 1),
 Singl
Band
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information: DOI
10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics
2
va0 1 2
vb0 Resulting PD Arrangement 1 1
vc0 Cell 1 Carrier Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier
vxref 0 0

0 0
sxn1 sx 2 sx1 Band 4
iCxn2 iCx 2 iCx1 1 1
n2 2Vdc Vdc
ix 0 0
Vdc Cdc Vdc Cxn 2 Cx 2 Cx1 vx Band 3
1 1
n 1 n 1 n 1
0 0
Band 2
1 1

0 Band 1 Sing
sxn1 sx 2 sx1
Fig. 1. Phase-leg of a five-level FC Converter.
1 2
Cell 1 1 0
2Vdc /(n − 1),..., (n − 2)/(n − 1)Vdc , and Vdc , with respect to 0 0
the dc negative rail “0”. Cell 2 0 0
1 1
B. PD-PWM Cell 3 0 0
In standard PD-PWM, n-1 carriers of the same amplitude, 1 1
frequency, and phase are arranged in a level shifted manner Cell 4 0 1
that occupy the linear modulation range. The reference signal (a) 0 0
is compared with the carriers to define the voltage levels Singl
that have to be generated at the output. This technique is
Carrier 1 CellCarrier 2
1 Carrier Carrier 3 Carrier4
spectrally superior to other carrier layouts because it produces vxref
Band 4
large harmonic concentration at some specific frequencies that 1 2
Band 4
cancel in the line-to-line voltages, hence reducing their total Band 3
1 0
harmonic distortion (THD) [10], [20]. However, when PD- vxref0 0
Band 3
PWM is applied to the FC converter, and each carrier should Band 2
0 0
not be associated to a specific cell, otherwise capacitor voltage
Band 21 1 1Sin
balance cannot be achieved. This is because the reference Band
signal crosses a single carrier at any sampling period and 0 1
hence only the cell associated to that carrier will switch. As (b) Band 1 0 0
a consequence, the FC voltages will keep on increasing or Fig. 2. PD-PWM in a five-level FC converter: (a) association of carrier
0 1 02
Resulting PD Arrangement 0 1 01
decreasing depending on the the direction of the output current segments to FC cells and final cell pulses, and (b) standard PD-PWM
Cell 1 Carrier
implementation Cell 2 Carrier
using trapezoidal Cell(Cell
carriers 3 Carrier
1). Cell 4 Carrier v 0 0
ix , thus deviating from their reference values. 1 xref Single
In PS-PWM, natural capacitor voltage balance is achieved Cell 1 4 0 0
0 Band
when the consecutive carriers are phase shifted by 2π/(n−1). 1 1 1
Based on this idea, a carrier rotation technique was proposed is compared with the triangular carrier (only oneCell carrier).
2 3 0 0
0 Band 1 2
using PD-PWM [7], [8]. This rotation implies that each spe- Look-up tables and some digital processing are needed to 1 1
1
define the states of all the switches, including those that have 1 00 0
cific carrier defines switching transitions to different converter Cell 3 2
Band
to0 switch during a particular sampling period. 0 10 1
cells. A similar rotation effect is achieved by re-shaping the 1 The value that has to be added to the reference signal 0 1
carriers. Fig. 2 shows the carriers arrangement for a five-level Cell 4 1
FC converter. Different sets of carriers are required to achieve v0offsetx depends on the band bx within it is located Band (bx = 0 0Sin
natural capacitor voltage balance. As it can be deduced from {1, 2, . . . , n − 1}). In the general case of an n-level FC 0 0
Fig. 2, this implementation of PD-PWM is complex, specially converter: 0 0
1 2
for converters with a high number of levels. 0 0
2 n − 2bx + 1 Cell 1 1 0
voffsetx = ( )(n − bx ) − 1 = . (1) 0 0
n−1 n−1 0 0
III. P ROPOSED PD-PWM I MPLEMENTATION Cell 2 0 0
The PD-PWM method proposed in [7], [8] requires (n−1)2 When this offset is added to the reference signal, the operating 1 1
carriers with different shapes and phase dispositions. Its im- Cell 3
range is within the interval [0, 2/(n−1)]. In order to normalize 0 0
plementation is complex and unpractical, especially for FC this range into [0, 1], the signal needs to be multiplied by 1 1
converters with a high number of levels. The proposed PD- (n − 1)/2, as follows: Cell 4 0 1
PWM implementation is based on the same concept but it is 0 0
radically simplified because a single triangular carrier is used 0 n−1 Sing
instead. To achieve this, the reference signal vxref needs to vxref = (vxref + vof f set ) . (2)
2
Carrier 1 Carrier 2 Carrier 3 Carrier4
be level-shifted and re-scaled. The band where the reference vxref
signal is located (Fig. 2(b)) needs to be determined in order to Fig. 3(a) shows an example of reference signal with the 1 2
Band 4
know the adjustments required. The modified reference signal corresponding bands in the case of a five-level FC converter. 1 0
Band 3 0 0
0 0
Band 2 1 1
0 1
Band 1 0 0
0 0
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics
3

From (1) and (2) considering n = 5, reshaping the reference

Band
Band Reference,
Reference, bbx Reference
ReferenceSignal,
Signal, vvxref signal is done using the following equation:
x xref

bbx=4
=4 v 0xref = 3 + 2vxref − bx . (3)
11
x
bx=3
b =3
x
0 b =2 Modulation is performed by comparing the rescaled refer-
0 bx =2
x
ence signal with the triangular carrier (Fig. 3(b)) producing the
-1 so-called raw PWM. The raw PWM needs to be processed to
-1 bbx=1=1
x define the state of each FC converter cell. Digital processing
0 0.01 0.02
0 0.01 0.02 is performed using masks that are allocated in look-up tables.
Time (s)
Time (s) The amount of intervals considered in the masks depends on
(a)
the number of levels of the FC converter by the relationship
Triangular Carrier Rescaled Reference Signal, v'xref
Triangular Carrier Rescaled Reference Signal, v'xref 2(n − 1). Therefore, in this example where n = 5, the number
1 of intervals is eight. The masks are designed to decide whether
1 the control signal of a converter cell is ‘1’, ‘0’, or a transition
‘1’-‘0’ or ‘0’-‘1’ defined by the raw PWM. The masks are
obtained from the information provided in Fig. 2 [7], [8].
Fig. 4(a) shows an example for Band 3. In this example, the
output signal that defines the state of Cell 1 (sx1 ) is ‘0’ during
0 the Intervals 2 and 3, and ‘1’ during the Intervals 5-8. In the
00 0.01 0.02
0 0.01
Time (s) 0.02 Interval 1, there is a transition ‘1’-’0’, and in the Interval 4,
Time (s) the transition is in the opposite direction, i.e. ‘0’-’1’. Such
(b) transitions are defined by the crossing of the reference signal
Fig. 3. Single carrier PWM implementation: (a) reference signal and band with the triangular carrier, i.e. by the raw PWM.
signal, and (b) modified reference signal and triangular carrier. Fig. 4 shows a possible implementation for the digital
Single Carrier 1 2 3 4 5 6 7 8 Counter processing. The information included in the masks is designed
Waveform according to this digital implementation. Coming back to the
Dedicated Band 3
1 for 2
Single CarrierCarrier 3 4 5 6 7 8 Counter example in Fig. 3, when the counter indicates Intervals 1 or 4,
Waveform Cell 1 (sx1)
vxref
1 the raw PWM should be applied to Cell 1. To achieve this, the
Dedicated Band 3 Raw
information provided by the Mask A is ‘1’ (Mask A1 signal)
Carrier for 0 vxref PWM and it leads the raw PWM to the output of the AND gate
Cell 1 (sx1) 1 1
Raw sx1 associated to Cell 1 (Fig. 4(b)). During those intervals, the
0 0 PWM
Mask B should provide a ‘0’ (Mask B1 signal) to let the raw
1Switching
PWM 0 0 PWM 1 1 1 1
sx1 PWM reach the output sx1 through the OR gate. When the
Transition ON ON
0 counter indicates Intervals 2 or 3, the Mask A1 signal is ‘0’,
for Cell 1
Switching PWM (sx1) 0 0 PWM 1 1 ‘-’ Do
1 Not1 Care imposing the output of the AND gate to be ‘0’ and therefore
Transition Mask ON A1 1 0ON 0 1 - - - - preventing the raw PWM to go to the next stage. The final
for Cell 1 output for Cell 1 is defined by the state of mask B (signal
Mask B1 0 0 0 0 1 1 1 1
(sx1) ‘-’ Do Not Care
Mask B1), which is ‘0’ in this case. Similarly, the output sx1
Mask A1 1 0 0 1 - - - -
is imposed to be ‘1’ by the signal Mask B1 during the Intervals
Mask B1 0 0 0 0 1 1 1 1 5-8. Using this simple two-signal masks, the state of each cell
(a) is defined. Fig. 5 shows the block diagram for the proposed
implementation. Table I shows the masks for all the cells and
Mask B1 bands in the case of a five-level FC converter.
Raw PWM OR sx1
AND The generation of the masking codes is done off-line and,
Mask A1
given a specific n−level FC converter, the masks are always
Mask B1 Mask B2 sx2
Raw PWM OR sx1
OR the same. The mask pointer needs to be synchronized with
AND AND
Mask A1 Mask A2 the carrier signal and it increases whenever the slope of the
carrier changes. The number of the interval is odd/even when
Mask B2 Mask B3 sx3
OR sx2
OR the carrier signal has a positive/negative slope, respectively.
AND AND
Mask A2 Mask A3 Table II shows the comparison of the proposed PD-PWM
Mask B4 implementation with the methods presented in [7]–[10].
Mask B3 OR
s sx4
AND OR x3
Mask A4
AND
Mask A3
IV. S IMULATIONS AND E XPERIMENTAL R ESULTS
(b)
Mask B4 Simulations and Experimental tests are performed on a low
Fig. 4. Generation of PWM signals usingOR sx4analysis of intervals and
masks: (a)
Mask A4
(b) proposed digital AND
processing circuitry. power grid-connected five-level FC converter. The proposed
PD-PWM implementation has been programmed in a DSPACE

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 1 2 3 4 5 6 7 8 Counter
Resulting PD Arrangement 1 1 issue
0 0 of
0 this
0 0journal,
0 Maskbut
A1 has not been fully edited. Content may change prior to final publication. Citation information: DOI
Cell article
This 1 has1 been
0 0 accepted
1 0 0 0for0 publication
Mask A1 in a future
Cell 1 Carrier Cell 2 Carrier Cell 3 Carrier Cell 4 Carrier Cell 1 Cell 1
0 0 0 0 1 1 1 1 Mask B1 vxref 0 10.1109/TPEL.2015.2427201,
0 1 1 1 1 1 1 Mask B1 IEEE Transactions on Power Electronics
Cell 2 0 0 1 0 0 1 0 0 Mask A2 0 0 1 1 0 0 0 0 Mask A2
Band
Cell4 2 Cell 2 4
1 1 0 0 0 0 1 1 Mask B2 1 1 0 0 1 1 1 1 Mask B2
Cell 3 0 0 0 0 1 0 0 1 Mask A3 0 0 0 0 1 1 0 0 Mask A3
Band
Cell3 3 Cell 3
1 1 1 1 0 0 0 0 Mask B3 1 1 1 1 0 0 1 1 Mask B3
Cell 4 0 1 0 0 0 0 1 0 Mask A4 0 0 0 0 Mask
0 0 1 1 Mask A4
Band 4 Band Band
Cell2 4 1 1 1 1Signals
1 1 0 0 Mask B4
Cell 4
0 0 1 1 1 1 0 0 Mask B4
Detector Code sx1
Single Carrier Waveform Band 1 Sequencer
Single Carrier WaveformDigital
sx2 TABLE III
Band 3
r4 Band 2 Raw Signal PARAMETERS OF G RID -C ONNECTED FC C ONVERTER
vxref Band 3
PWM Processing sx3
Band 4 vxref1 2 3 4 Modulation
5 6 7 8 Counter v'xref Comparator
1 2 3 4 5 6 7 8 Counter
sx4 Circuit Parameter Value
Band 2 1 0 0 0Signal 0 1 Rescaler
0 0 Mask A1 Cell 1 1 0 0 1 0 0 0 0 Mask A1
Cell 1 Cell 1 RMS Grid Voltage, E 60 V
Band 3 0 0 0 0 0 0 1 1 Mask B1 0 0 0 0 1 1 1 1 Mask B1
Band 4 0 0 1 0 0 0 0 1 Mask A2 Cell Mask
2 0 0 1 0 0 1 0 0 Mask A2 Dc-Bus Voltage Source, Vdc 110V
Fig.1 5.1 Single
Band Carrier
Diagram of the Waveform
proposed Cell 2
PD-PWM
Signals implementation. Cell 2
Band 12
Band 0 0 0 0 0 Mask B2
0Detector Code 1 1 0 sx1 0 0 0 1 1 Mask B2 Dc-Bus Capacitor, Cdc 2 mF
Sequencer Digital
Band 3 0 1 0 0 1 0 0 0 Mask A3 Cell 3
CellRaw
3 0
Signal 0 0 sx2
0 1 0 0 1 Mask A3
1 1 0 0 0 0 Mask B3 PWM Band
Flying Capacitors, C1 , C2 , C3 220 µF
1I 41 1 sx3
0 0 Modulation Cell 3
Band 1 TABLE Processing 1 0 0 0 0 Mask B3
vxref
Band 2 0 0 Signal 0 0 v'1xref 0 Comparator
0 1Rescaler Mask A4Cell 4 0 1 FC 0 sx4
0 C0ONVERTER
0 1 0 Mask A4 Grid Inductance, L 6 mH
M ASKS U SED IN ACell 4 -L EVEL
F IVE Cell 4
0 10 02 0 31 14 0 50 Mask 6 B47 8 Counter 0 0 1 1 1 1 0 0 Mask B4 Carrier Frequency, fs 4.1 kHz
Band 1 Single Carrier Waveform
Single Carrier Waveform Single Carrier Waveform Fundamental Frequency, f 50 Hz
Cell 1 1 1 0 0 0 0 0 0 Mask A
Carrier 1 Carrier 2 Carrier 3 Band
Band 41
Carrier4 Cell 1 Band 2 Balance booster inductance, Lb 1mH
vxrefCell 2 0 0 1 1 1 1 1vxref1 Mask B
11 22 33 44 55 66 77 88 Counter
CounterBand 4 Balance booster capacitance, Cb 1.5µF
1 2 3 4 5 6 7 8 Counter
11 010 00000 100 001 00 00 Mask
0 A1
1 Mask A1
0 0 Mask A
Band
rrier 43 Cell
Cell 11
1 0 0Cell
0 02 1 0 0 Mask A1
Cell 1
Balance booster resistor, Rb 68Ω
vCell
xref 00 100 10110 010 100 10 10 Mask
1 1 B1
Mask B11Band 13 Mask 0 B
0 0 0 0 0 1 1 Mask B1
00 01 11 10 00 00 00 00 Mask
Mask A2
A2 Cell 2
Band Cell
4 0 0 1 0 0 0 0 1 Mask A2
10 010
Cell 4 1 Carrier 00000 010 100 10 110 Mask
1
Mask B2
0 Band042
Cell Mask A 0Band0 0 0 Cell 2
Mask
Band 3 B2Band 2 1 1 0Cell 3 0 Mask B2 Signals
Code sx1
Band 3
00 100 00101 111 101 00 00 Mask
0 0 A3
Mask A31 Cell1
Cell 333
Mask 0 B
1 0 Detector
0 1 0 0 0 Mask A3
Sequencer
Cell 3 Digital sx2
10 10 10 10 00 00 10 10 Mask B3 Band
Mask B3Band 1 0 0 1 1 0 0 0 0 Mask B3 Signal
00 000 00000 000 010 11 010 Mask
0 A4 1 1 Mask A 1 0 0 1 Raw
sx3
Mask A4
PWM Processing
Band 2 Cell vxref0 0 0Modulation
Cell 4 v' 0 Mask A4
Cell 244
Band 2 Comparator
Signal Rescaler xref
Cell 4 sx4
10 110 10110 110 101 00 10 Mask
0 1 B4
Mask B40Band 0 Mask 0 B
0 0 0 1 1 0 0 Mask B4 CH2:vdc CH3:vCa1 CH4:vCa2 CH5:vCa3
Band 1 Single Carrier Waveform Single
SingleCarrier
CarrierWaveform
Waveform
Band 1
Band 1 Single Carrier Waveform
Band 3
Cell 1
Band
Band 14

1 2 3 4 5 6 7 8 CounterCell 2 Band
11 23
2 33 44 55 66 77 88 Counter
Counter
Cell 1 Resulting
1 0PD0Arrangement
1 0 0 0 0 Mask A1 11 01 00 00 00 00 00 10 Mask
Mask A1
A1
Cell 1 Carrier Cell 20Carrier Cell
CarrierB1Cell 31 Cell 11
Cell
0 0Cell0 3 1Carrier
1 1 Cell
1 4Mask vxref8 00 00 01 01 01 01 01 01 Mask
Mask B1
B1
Cell 2 1 2 3 4
0 0 1 0 0 1 0 0 Mask A2
5 6 7 Counter
00 10 11 01 00 00 00 00 Mask A2
Mask A2
Cell 42
Band Cell 22
Cell
Cell 1 1 11 00 0 0 0 01 1 0 0 B2
1 Mask 0Cell 04 Mask
01 A
01 00 00 01 01 01 01 Mask B2
Mask B2 CH1:vab CH6:va
Cell 3 0 0 0 0 1 0 0 1 Mask A3 00 00 00Cell
10 111 01 00 00 Mask A3
Mask A3
0 0 0 0 1 1 1Band
1 1 1 1 0 0 0 0 Mask B3
Cell133 Mask B
01 01 01 01 00 00 01 01 Mask B3
Mask B3
Cell 33
Cell
CellCell2 4 0 0 1 0 00 01 00 1 0 1 0Band
0 Mask A4 0 Mask
00 A
00 00 00 00 10 11 01 Mask A4
Mask A4
Cell 44
01Cell
01 012 01
Cell 24 Cell
0 0 1 1 1 1 0 0 Mask B4 01 01 00 00 Mask B4
Mask B4
1 1 0 0 0 0 1 1 Mask B
Single Carrier Waveform
Cell 3 0 0 0 0 1 0 0 1 Mask A
Band 1 Single Carrier Waveform
4
vxref Band 2 Cell 3 Band 3
1 1 1 1 0 0 0 0 Mask B
Cell 4 Band 4 1006
1 2 controller
3 4 5 6 7 with integrated DS
8 Counter 1 2 52033 4 5 FPGA board. The
6 7 8 Counter
1 0
0 0 10 00 100 0 0 A11Cell 01 Mask1 A0 0 1 0 0 0 0 Mask A1
0 Mask CH7: ia CH8: ib CH9: ic
parameters of the converter Cell 1are given Cell
in 4
table III. Cell 1
Band 3 0 0
0 0 00 01 011 11 Mask
1 B1 0 Mask
0 proposed 0 B 0 0 0 1 1 1 1 Mask B1 CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div
The performance
0 0 of
1 0 0 0 0 the PD-PWM implementation
1 Mask A2Cell 2 0 0 1 0 0 1 0 0 Mask A2 CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div
Cell 2 Cell 2
Band 2 1 Single
is 1tested 0Carrier
0 0 a0Waveform
0 0 under Mask B2
closed-loop operation
1 1 0 0 on 0 0a 1 grid-connected
1 Mask B2 (a) Simulation
0 1 0 0 1 0 0 0 Mask A3Cell 3 0 0 0 0 1 0 0 1 Mask A3
FC0 converter, as shown inCellFig. 3 6. An RLC voltage balancing Cell 3
Band 1
vxref
0 1 1 0 0 0 0 Mask B3 Band1 21 1 1 0 0 0 0 Mask B3
booster
0 0 0 is 1 connected
0 0 1 0 Maskto the
A4Cell 4 converter
Cell 4 0 1 0output
0 0 0 [7]–[9].
1 0 Mask The
A4 dc- CH2:vdc CH3:vCa1 CH4:vCa2 CH5:vCa3
Cell 4
Band 4 bus0 1voltage
0 0 0 1 1 0 0 Mask B4
2 3is4provided
5 6 7by 8dc Counter 0 0 source
voltage 1 1 1 with 1 0 0 VMask =
dc B4 110V.
Single Carrier Waveform Single Carrier Waveform
Cell 1 Traditional
1 0 Carrier 0 decoupled 1 0id -i0q Mask
0 0Carrier4 current A control loops are used
Carrier 1 Carrier 2
for the 3 Band 1 v[21]. Cell 1 Band 2
Band
Cell 3
2 0 0 0 0 0 0 1 1 Mask B are charged using the
grid connection xref The FCs
1 2 3 4 5 6 7 8 Counter Band 4 1 2 3
precharging method proposed in [22]. The line-to-line voltage 4 5 6 7 8 Counter
0 0 00 01 000 01 Mask 0 A10 1 Mask 1 A0 0 0 0 1 0 0 Mask A1
Cell 3 vab10 , 00dc-bus voltage vdc and
Cell 1 FC voltages Cell 2(v 1 11 ,Mask
0 0 0 0 0 Ca
vCaB1 2
, and
Cell 1
Band 2 1 0 10 00 000 00 Mask 0 B10Band0 3 Mask 0 B
vCa 0 3 1 ) 1are
0 shown
0 0 0 0in Fig.
Mask A2 6(a). The0 converter
0 1 0 0 0maintains0 1 Mask A2the FC
Cell 2 CH1:vab CH6:va
0 0 0 0 10at00 the
00 0 reference
10 Mask
0 B20 Band022 Mask 1 A
Cell 4 Cell 1∗ 0 0 0 0 0 0 Mask ∗ B2
voltages values (V C1 =
Cell 27.5V,
3
0 1 0 0 1 0 0 0 Mask
VC2 A3
= 55V,
Band 1 VC3
0∗ 0 0 0 01 11 01 0 0
= 82.5V). At t0 =0 Cell
0 Mask A3 03 Mask
50ms, the B Cell 3
0 0 0 0 0 0 0 0 Mask B3 Band 1 0 0reference
1 1 0 0 current changes
0 0 Mask B3
0
0 0 i0 =3A
∗0 0 1 0∗ 0 1 0 Mask 0 A
0 0 1 0 0 1 0 Mask A4
from d 0 0 1to1 i0d =5A.
Mask A4 As it can be observed, the proposed
Cell 4 0 0 0Cell 0 14 1 0 0 Mask B4
Cell 4
0 0
PD-PWM 0 0 00 00 00 0 1 Mask
1 B40 0 performs
0 Mask
implementation B well under closed-loop
1 Single Carrier Waveform
0
operation SingleandCarrierthe voltages
Waveform Cell 1 in the FCs remain unaffected
1 Band 1
Cell 1 during this transient. Fig. 6(b) shows similar results obtained
Cell 2
0 3 4 5 6 7 8 Counter
Band1 12 CH7: ia CH8: ib CH9: ic
1
Cell 3
1 0 0 0 0 0 0 1 Mask A1
Cell 1 CH1:80V/div CH2:80V/div CH3:80V/div CH4:80V/div TB: 10ms/div
0Cell 2 0 0 0 0 0 0 0 0 Mask B1 CH5:80V/div CH6:30V/div CH7:4.0A/div CH8:4.0A/div CH9:4.0A/div
1 1 2 3 4 5 6 7 8TABLE Counter
0II 1 1 0 0 0 0 0 Mask A2
Cell 4 Cell 2 (b) Experimental
0 C1OMPARISON
0 0 0 OF0PD-PWM
0 0 I1MPLEMENTATIONS
Mask0 A0 0 0 0 IN0 FC
0 0MMask B2
ULTILEVEL
Cell 3 0 0 0Cell
C ONVERTERS 1 11 0 0 0 Mask A3 Fig. 6. Closed-loop grid-connected FC converter operating with the proposed
0 0 0 0 0 0 0 0 Mask0 B0 0 0 0 0 0 0 Mask B3 Cell 3 modulation technique. The dc-bus voltage is provided by dc voltage source
0 PD-PWM 0 0 ofMask0Shape
1 1 0 0 0Number A0 0 of
0 0 1 Implementation
1 0 Mask A4
Cell 4 with Vdc = 110V. The current reference changes from i∗d =3A to i∗d =5A at
Cell 4 0 0 0Cell
0 02 0 0 0 Mask B4
Implementations
0 0 0 0 0 0 0 MaskCarriers
0 Carriers B Difficulty t=50ms. Top waveforms: line-to-line output voltage, dc-bus and FC voltages.
Proposed one 1 Triangular Low Bottom waveforms: grid voltage and output currents. (a) Simulation and (b)
0 0 0 1 1 0 0 0 2 Mask A experimental results.
(n − 1)
[7], [8], [10] Cell 3
Trapezoidal High
0 0 0 0 0 0 0 0 Mask B
[9] n−1 Triangular Medium
0 0 0 0 0 1 1 0 Mask A
Cell 4
0 0 0 0 0 0 0 0 Mask B

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2427201, IEEE Transactions on Power Electronics
experimentally from the laboratory prototype.
V. C ONCLUSION
In this letter, a new implementation of PD-PWM for a
FC converter using just a single carrier has been presented.
The modulation signals have been properly level-shifted and
rescaled to operate in the range of a single triangular carrier.
The PWM pulses have been digitally processed to achieve the
same effect as in the case of other complex implementations
based on using several trapezoidal carriers. The proposed PD-
PWM implementation has been presented in a general way so
that it could be applied to FC converters with any number of
levels. It is easy to apply and very suitable to be processed
in a digital processor. In this letter, the proposed PD-PWM
implementation has been tested on a five-level FC converter
together with an RLC voltage balancing booster and it has
shown excellent results.
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