ARIGNAR ANNA INSTITUTE OF SCIENCE AND TECHNOLOGY

Dr.G.Jayarama Nagar, Pennalur, Sriperumbudur– 602 117

AP7201& ANALYSIS AND DESIGN OF ANALOG INTEGRATED

SUB. CODE & SUBJECT
CIRCUITS

DEPT. ECE YEAR / SEMESTER I / II

FACULTY NAME
DEPARTMENT OF VLSI DESIGN

LESSON PLAN

SYLLABUS
UNIT I BASIC CMOS CIRCUIT TECHNIQUES, CONTINUOUS TIME AND LOWVOLTAGE
SIGNAL PROCESSING 9
Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting
Techniques-Super MOSTransistor- Primitive Analog Cells-Linear Voltage-Current
Converters-MOS Multipliers and Resistors-CMOS, Bipolar and Low-Voltage Bi CMOS
Op- Amp Design-Instrumentation Amplifier Design-Low Voltage Filters.

UNIT II BASIC BICMOS CIRCUIT TECHNIQUES, CURRENT -MODE SIGNAL

PROCESSING AND NEURAL INFORMATION PROCESSING 9
Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-
Current Data Converters-Practical Considerations in SI Circuits Biologically-
Inspired Neural Networks - Floating - Gate, Low-Power Neural Networks-CMOS
Technology and Models- Design Methodology-Networks-Contrast Sensitive Silicon Retina.

UNIT III SAMPLED-DATA ANALOG FILTERS, OVER SAMPLED A/D

CONVERTERS AND ANALOG INTEGRATED SENSORS 9
First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-
Switched- Capacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate A/D
Converters- Modulators for Over sampled A/D Conversion-First and Second Order and
Multibit Sigma- Delta Modulators-Interpolative Modulators –Cascaded Architecture-
Decimation Filters- mechanical, Thermal, Humidity and Magnetic Sensors-Sensor
Interfaces.
UNIT IV DESIGN FOR TESTABILITY AND ANALOG VLSI
INTERCONNECTS 9
Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods
and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test
Buses- Design for Electron -Beam Testablity-Physics of Interconnects in VLSIScaling
of Interconnects-A Model for Estimating Wiring Density-A Configurable
Architecture for Prototyping Analog Circuits.

UNIT V STATISTICAL MODELING AND SIMULATION, ANALOG COMPUTERAIDED

DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL
LAYOUT 9
Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit
Simulation- Automation Analog Circuit Design-automatic Analog Layout-CMOS
Transistor Layout- Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -
Digital Layout.

TOTAL: 45 PERIODS

TEACHIN
S.NO DATE HOUR TOPICS T/R G
METHOD
UNIT I
Mixed-Signal VLSI Chips-Basic CMOS
1 BB
Circuits
2 Basic Gain Stage BB
Gain Boosting
3 BB
Techniques
4 Super MOS Transistor BB
5 Primitive Analog Cells- BB
Linear Voltage Current
6 BB
Converters
7 MOS Multipliers and Resistors BB
8 CMOS, Bipolar and Low-Voltage Bi CMOS
BB
9 Op- Amp Design-Instrumentation Amplifier BB
10 Design-Low Voltage Filters BB
11 REVIEW BB

UNIT II
Continuous-Time Signal Processing
12 BB

13 Sampled-Data Signal Processing BB

Switched-
14 BB
Current Data Converters
15 Practical Considerations in SI Circuits BB
16 Inspired Neural Networks BB
17 Floating BB
18 Gate, Low-Power Neural Networks BB
CMOS
19 BB
Technology and Models-
Design Methodology-Networks-
20 BB
Contrast Sensitive Silicon Retina.
21 BB
REVIEW

Unit-III
First-order and Second SC Circuits-Bilinear
22 BB
Transformation - Cascade Design

23 Switched- Capacitor Ladder Filter-Synthesis

of Switched-Current Filter
BB
Nyquist rate A/D
24 BB
Converters- Modulators for Over sampled
A/D Conversion
First and Second Order and
25 BB
Multibit Sigma
26 Delta Modulators-Interpolative Modulators
BB
Cascaded Architecture-
27 BB
Decimation Filters- mechanical, Thermal

28 Humidity and Magnetic Sensors BB

 Sensor
29 BB
Interfaces.
30 REVIEW BB

UNIT IV DESIGN FOR TESTABILITY AND

ANALOG VLSI INTERCONNECTS
31 Fault modeling and Simulation BB
Testability-Analysis Technique-Ad Hoc
32 Methods BB

General Guidelines-Scan Techniques-

Boundary Scan-Built-in Self Test-Analog
33 BB
Test

34 Buses- Design for Electron -Beam

Testability
BB
Physics of Interconnects in VLSIScaling
35 BB
36 Interconnects BB
37 A Model for Estimating Wiring Density- BB
A Configurable
38 BB
Architecture for Prototyping Analog Circuits
39 REVIEW BB

UNIT V STATISTICAL MODELING AND

SIMULATION,ANALOGCOMPUTERAIDED
DESIGN AND ANALOG AND MIXED
ANALOG-DIGITAL LAYOUT

40 INTRODUCTION BB
41 Review of Statistical Concepts
BB
42 Statistical Device Modeling-
BB
43 Statistical Circuit BB
44 Simulation
BB
 Automation Analog Circuit Design
45 BB
automatic Analog Layout-CMOS
46 BB
Transistor Layout
47 Resistor Layout-Capacitor Layout-Analog
Cell Layout-Mixed BB
48 Analog & Digital Layout
BB
49 REVIEWS
BB

Prepared by Approved by

Signature

Name

Designation Assistant Professor

 ARIGNAR ANNA INSTITUTE OF SCIENCE AND TECHNOLOGY
Dr.G.Jayarama Nagar, Pennalur, Sriperumbudur– 602 117

DEPARTMENT OF VLSI DESIGN

LESSON PLAN

SUB. CODE & SUBJECT CU7001 REAL TIME EMBEDDED SYSTEMS

DEPT. ECE YEAR / SEMESTER I / II

FACULTY NAME

SYLLABUS
UNIT I INTRODUCTION TO EMBEDDED COMPUTING 9
Complex systems and microprocessors – Design example: Model train controller –
Embedded system design process – Formalism for system design – Instruction sets
Preliminaries – ARM Processor – CPU: Programming input and output – Supervisor mode,
exception and traps – Coprocessor – Memory system mechanism – CPU performance –
CPU power consumption.

UNIT II COMPUTING PLATFORM AND DESIGN ANALYSIS 9

CPU buses – Memory devices – I/O devices – Component interfacing – Design with
microprocessors – Development and Debugging – Program design – Model of programs –
Assembly and Linking – Basic compilation techniques – Analysis and optimization of
execution time, power, energy, program size – Program validation and testing.

UNIT III PROCESS AND OPERATING SYSTEMS 9

Multiple tasks and multi processes – Processes – Context Switching – Operating Systems –
Scheduling policies - Multiprocessor – Inter Process Communication mechanisms –
Evaluating operating system performance – Power optimization strategies for processes.

UNIT IV HARDWARE ACCELERATES & NETWORKS 9

Accelerators – Accelerated system design – Distributed Embedded Architecture – Networks
for Embedded Systems – Network based design – Internet enabled systems.

UNIT V CASE STUDY 9

Hardware and software co-design - Data Compressor - Software Modem – Personal Digital
Assistants – Set–Top–Box. – System-on-Silicon – FOSS Tools for embedded system
development
TOTAL: 45 PERIODS

TEACHIN
S.NO DATE HOUR TOPICS T/R G
METHOD
UNIT I
Complex systems and microprocessors
1 Design example: BB

2 Model train controller

BB
Embedded system design process
Formalism for system design – Instruction
3 sets BB

4 Preliminaries – ARM Processor BB

CPU: Programming input and output
5 Supervisor mode BB

6 exception and traps – Coprocessor BB

7 Memory system mechanism BB
CPU performance
8 BB

9 CPU power consumption BB

10 EXAMPLES BB
11 REVIEW BB

UNIT II
12 CPU buses – Memory devices BB
13 I/O devices – Component interfacing BB
14 Design with
BB
microprocessors
15 Development and Debugging BB
16 Program design – Model of programs
BB
17 Assembly and Linking BB
18 Basic compilation techniques BB
19 Analysis and optimization of execution time BB
20 power, energy, program size BB
21 Program validation and testing. BB
REVIEW

Unit-III
22 Multiple task BB
23 multi processes BB
24 Context Switching BB
25 Operating Systems
BB

26 Scheduling policies - Multiprocessor

BB
27 Inter Process Communication mechanisms BB

28 Evaluating operating system performance BB

29 Power optimization strategies for processes BB

30 REVIEW BB

UNIT IV

introduction
31 BB

32 Accelerators
BB
33 Accelerators design BB
34 Accelerated system design BB
35 Accelerated system design
BB
Distributed Embedded Architecture –
36 Networks BB
for Embedded Systems
37 Network based design BB
38 Internet enabled systems BB
39 REVIEW BB
 UNIT V

40 Introduction BB
41 Hardware and software co-design
BB
42 Data Compressor
BB
43 Software Modem BB
44 Personal Digital
BB
Assistants
45 Set–Top–Box
BB
46 System-on-Silicon BB
47 System-on-Silicon design
BB
– FOSS Tools for embedded system
48 development BB

49 REVIEWS BB

Prepared by Approved by

Signature

Name

Designation Assistant Professor