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Analog Design Techniques
Analog Design Techniques
for Low-Temperature
Mixed-Signal CMOS Systems
Benjamin J. Blalock & Stephen C. Terry
bblalock@ece.utk.edu
INSYTE Lab
(Integrated Circuits & Systems Laboratory)
www.ece.utk.edu/insyte
Analog
In Residue
Out
S/H + G=2
ADC DAC
Digital
Out
Analog
In Digital
+ H(z) + Out
• Important Considerations:
– Vendor models not specified at cryogenic temperatures
– Standard circuit topologies may not work over large
temperature range
– Standard design equations not valid for large
temperature range
kT
UT =
q
−1
T
µ p = µ0 p
300
−1.4
T
µ n = µ0n
300
VBIAS
• The Beta-multiplier is a popular constant gm bias
1:1
circuit, however the standard analysis assumes
either strong or weak inversion
VCASP • Analysis of this circuit using the EKV model
provides a design equation that describes
operation at any inversion level (IC)
− 1
( )
IC
1 2 e −
gm = ⋅ ln 1 − e IC
(W/L) K(W/L) n ⋅ R IC e IC / K − 1
R
R
- IOUT
+
R
R
M1
R
R
M2
IF
= n2
1
IR
1 B.A. Minch, “A Low-Voltage MOS Cascode Bias Circuit for All Current Levels,” Proc.
IEEE Int. Sym. On Circuits and Systems, Scotsdale, AZ, 2002, pp. 619 – 622
Constant Adaptive
gm LVCCM
Biasing Biasing
1000
Noise spectrum w/
Auto-zero
100
1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05
Frequency (Hz)
VMID
VMID
VMID
VID
+
70
65
THD (dB)
60 10 Bit Linearity
55
50
8 Bit Linearity Measurement Notes:
Av = +1
Vin = 3V p-p @ 8kHz
45 11 Harmonics Measured
40
113 133 153 173 193 213 233 253 273 298
Temperature (K)