LOGIC STYLE

Prof. Kaushik Roy

@ Purdue Univ.
 DCVS Logic With Pass Gate (DCVSPG)
VDD VDD
1 2

Q Q’
0 VDD-VT VDD

3
B’ 5
4
B 6

A A’ A’ A

- Full Swing - Limited logical depth

- Area, power reduction - Body effect
- Differential noise immunity
Swing-Restored Pass Gate Logic (SRPL)
VDD VDD

Q
Q’

3
B’ 5
4
B 6

A A’ A’ A

- Low stand-by power

- High design margin, process tolerance
- Less delay via sense-amp action
 Double Pass-Transistor Logic (DPL)
Q’ Q

A’

B’

VDD B’ VDD A B GND A’ GND

- High Speed
- Avoids buffer
- Avoids VT drop
- Redundant device structure