Effect of Vdd Scaling

Different Architectures at Nominal Voltage

Convention CSHM DCT Proposed

CSHM DCT DCT Proposed
al WTM DCT (2 alphabet) DCT 1.0V
DCT with Original 6 alphabets jongsun modified Proposed 2 alphabets

(2 alphabets) with WTM DCT

Power (mW) 25.1 29.8 26

1.0 V Delay (ns) 3.2 3.64 3.57

5 Paths
Area (um2) 80490 108738 90337
PSNR (dB) 21.97 33.23 33.22

FAILS FAILS
0.9 V
Proposed Architecture at Reduced Voltage
Proposed 2 alphabets

Proposed DCT Proposed DCT

Vdd=0.9V Vdd=0.8V
FAILS FAILS
0.8 V
Power (mW) 17.53(41.2%) 11.09(62.8%)

PSNR (dB) 29 23.41

 Graceful degradation of proposed DCT architecture under Vdd scaling

( Vdd can be scaled to 0.75V)
 Conventional architectures fails Prof. Kaushik Roy
@ Purdue Univ.
 CRISTA for DSP Systems
2. Finite Impulse Response (FIR)

critical
coefficients

less-critical
coefficients

3. Color Interpolation
 Bilinear component is critical and gradient component is less-critical
 Design architecture such that failures can only occur in gradient term
Conv Proposed
Gi−1, j
Gi, j−1 Vdd
>>2 G’1
Gi+1, j G’2
1.0 V
Gi, j+1 M
>>2 Vdd G’3
R i, j >>1 FAILS
M1
― 0.9 V
Ri, j -2 ―
Ri, j+2 FAILS
Ri+2, j 0.8 V
Ri -2, j Prof. Kaushik Roy
@ Purdue Univ.
IS BOOLEAN EQUIVALENCE
ALWAYS REQUIRED?

Prof. Kaushik Roy

@ Purdue Univ.
 Approximate Full Adder Cells
Conventional/Accurate Approximation 1

A B Cin Sum Cout A B Cin Sum Cout

0 0 0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 1 1 0

0 1 0 1 0 0 1 0 0 1
0 1 1 0 1 0 1 1 0 1
1 0 0 1 0 1 0 0 0 0
1 0 1 0 1 1 0 1 0 1
1 1 0 0 1 1 1 0 0 1
1 1 1 1 1 1 1 1 1 1
Prof. Kaushik Roy
@ Purdue Univ.