@KENWOOD a SERVICE. MANUAL R-600 . COMMUNICATIONS RECEIVER } i CONTENTS CIRCUIT DESCRIPTION... 2 BLOCK DIAGRAM... PACKING nnn 5 TERMINAL FANCTIONS. PARTS LIST. —— ~ 8 SCHEMATIC DIAGRAM, PC BOARO/CIRCUIT DIAGRAM LEVEL DIAGRAM... PLL UNIT (X50-1850-X%) RX UNIT (X55-1310-X, DISASSEMBLY... ADJUSTMENT .. 10 SPECIFICATIONS... 12 DCK-1 DC CORD KIT PARTS LIST... 13 FREQUENCY SHIFT UNIT (W2 oni... 14R-600 2 CIRCUIT DESCRIPTION Tha A-600 PLL circuit consists of three VCO's. The re- ference oscillator frequency is 10 MHz, developed by 10 MHz quartz crystal X1 and oscillator Q9, 2SC1B151Y). A 1 MHz frequency 's used for PLL phase comparison. The fre- ‘quency counter uses 2 1.26 MHz frequency. ‘The 30 and 40 MHz receiver mixer injaction frequen cles are multialied from the 10 MHz master oscillator. Os- cillator 9's output is buffered by Q10, 2C1815(%) and vided 1/10 by Q1 1, SN74LS9ON to supply a 1 MHz refer- ence signal to 012, MIC4044P, the phase detector. The PLL includes the VFO (variable frequency oscillator circuit, which covers 3545 ~ 4545 Miz, a 7 MHz range. Also con- tained in the PLL is the frequency counter and display drivers forthe digital frequency readout Each of three VCO's are assigned a reception frequency range; 0.15 to 7 MHz receive coresponds to 40.605 to 48.455 MHz VCO-1 output, 8 to 16 MHz corresponds to 48.455 to 57.455 MHz, and 17 10 30 MHz is 67.455 to 70.45 MHz. VCO-1 is comprised of oscillator transistor 1 2C1923(0), wning diode 1 1SV54GC and output switch diode 02 1S1887. VCO-2 and 3 are similar. each ‘with @ voltage-contralled tuning diede and outout switch diode. The VCOs' autput for loop phase detection is but- fered by QS, while the output for receiver mixer injection is buffered by Q40 and Q4, 25C1923(0) The VFO circuit consists of 026, 2SK191¥) oscillator and a conventional LC tank circuit. 26, 2SC18151¥) emit. tet follower buffers the VFO output. The VFO range is 2545 ~ 345 MHz. Its output is mixed with a 40 MHz signal from buffer 043, 2SC460 (8) by G17, SN16913P to pro- ‘duce an output in the range of 36.455 to 37.455 MHz. Note that es described earlier, this 40 MHz signal is ob- tained by 2 4X mutiplication of the 10 MHz master oscila- tor output. Mixer 17's output is then fitered, buffered by 018, 25K19(GR), and mixed with the VCO output from O5. 2SC1923(0) buffer by 018, SN16913P. The output of this ‘mixer is a signal in the 4 ~ 33. MHz range. ‘Output trom O19 is fitered, buffered by 020, 28C1923)0}, and amplified by O21, 28C19230}. This is further buttered by 022, 2SC1B15(") and 23, 2SCI958IY, The signal is then waveform-shaped by Schmitt tigger 024, SN74SOON and delivered to 2 pro- ‘grammable counter controled by the band switch. This counter is comprised of O31 SN74LS163N, G32 SN74S112N, 033 SN74LSOON, and O34 SN74LS74N. Which produces a divided signal with a frequency ahvays at ‘MHz, The output of this divider is used for phase compari- on in the PLL circuit by O12 MC4044P phase comparator, against the 1 MH2 reference trom Q11 divider Any phase difference between the programmable ‘counter output and the 1 MH2 reference is detected in Q12, the phase comparstor. An error correction voltage, propor ‘ional to the phase arror between these two signals is out- put from Q12, and amplified by Darlington O6 ~ 8. 25C1775(E), This amplified correction voltage tunes the VCO's by varying the eapacitance of voltage-variable diodes: D1, 3, or 6 (depending on which VCO is selected). These diodes tune the VCO tank to reduce the error. which keeps the loop locked. The advantage ofthis system is that all sig- ral processing is dane out of the main signal path. and only clean, stable oscilator output s used by the receiver mixer The band switch outputs initial data forthe programma: ble counter, the band svaitehing signal forthe receiver circuit BPF's, and the VCO selection signal In the frequency display circuit, a 40 MHz signal gener- ated by Q16, 25C1815(¥) end buttered by 042, 25C460(8) is mixed with the VCO buffered. output trom Osi, 2C 1923/0) by O27, SN16913P to gonerate a signal inthe frequency range of 0.605 ~ 30 MHz. This 's filtered, but tered by 028 2SC1815(Y), amplified by 29 28C1923(0, and again buffered by G30 2SC18151¥}. The signal is wavetorm shaped by Schmitt tigger 44 SN74SOON. 035, MC54408P receives @ buffered 10 MHz clock signal through O13 2SC181 51M), divides this frequency by 32, and its output enters 035, M5482 1P a frequency counter. The output from O36 is used by 37 MS4521P digit driver anc 32 MB4563P segment drivar 10 multiplex the green five digit display LED, SL2504K. ‘The recewer seaond mixer local oscillator injection fre- ‘quency is 30 MHz, obtained by tripling the 10 MHz mastar ‘oscillator output through buffer 013, 2SC1811Y) by Q14, 2SC1B15(Y), Local oscilator injection is delivered through buffer 016, 28C1815)¥ The PLL also contains the main power supply circuts: bridge rectifiars DB ~ 11 VOSC for AC operation, D12 OSC biecking diode for optional DC operation, and a § voit AVR, 039 PC14305 for the PLL TTL circus. 77 17 rogue vier Gy once even bottinprscaer FEUEa Fig. 1 MB4408P Prescaler with crystal Oscillator CircuitR-600 CIRCUIT DESCRIPTION Dio our Incest safer moat o1 02 08 of 05 06 or 08 ow fF] fe) fe) Fa] fs) Fal fm fo om i TEE eae waa Fig, 6. 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