SCOE Vadgaon Pune

UNIT III
Algorithmic State Machine
 Syllabus

ASM & VHDL

Algorithmic State Machines: Finite State Machines (FSM) and

ASM, ASM charts, notations, construction of ASM chart and
realization for sequential circuits, Examples: Sequence
Generator, Types of Counter.

VHDL: Introduction to HDL, Data Objects & Data Types,

Attributes., VHDL- Library, Design Entity, Architecture, Modeling
Styles, Concurrent and Sequential Statements,

Design Examples: VHDL for Combinational Circuits-Adder, MUX,

VHDL for Sequential Circuits, Synchronous and Asynchronous
Counter.
Books to Refer
Text Books:

 R.P. Jain, ― “Modern Digital Electronics”,

Tata McGraw-Hill, 2012.

 Stephen Brown, Zvonko Vranesic, ―

“Fundamentals of Digital Logic with VHDL
Design”, McGraw-Hill.

Reference Books:

A VHDL Primer, J. Bhaskar

Digital Electronics & ASM
Logic Design
Introduction
 ASM chart: It is similar to conventional
flowchart but interpreted in different
manner.
 It is a graphical view.
 ASM chart is basically flowchart for
hardware algorithm.
 It considers timing relationships.
Cntd…
 It is useful to design the hardware of a
sequential circuits as per the specifications.
 It is suitable for describing the sequential
operations of a digital system.
ASM Chart Notations

The state box

The decision box
The conditional box
State box
 The state box is used for indicating the state
of the controller in the control sequence
 The shape of a state box is rectangular.
 Inside the box we write information such as
register operations or output value for given
state.
 For each state there is one entry and exit
point.
Cntd…
 On the right side of the box binary code of
each state is written.

entry
State Name Binary code
Register operation or outputs

exit
Cntd…
 Example

Entry
q1 binary code(00)

Z=1

Exit
Decision box
 The decision box is diamond shaped
box.
 It has two or more exit paths.
 A decision box may be conditioned on
a signal or a test of some kind.
Cntd…
 Decision box has exit path that checks condition
true or false.

0 (False) Condition 1 (True)

expression
Conditional box
 It is oval shaped.
 The input path to the conditional box must
come from one of the exit paths of the
decision box.
Conditional outputs
or actions
 entry
q1 001

1 0
D

q2 010 q3 100
Draw ASM chart for given diagram
Reset
w=1
w=0 A z = 0 B z = 0
w=0

w=0 w=1

C z = 1

w=1
State table

Present Next state Output

state w = 0 w = 1 z

A A B 0
B A C 0
C A C 1
ASM Chart
Reset

0
w
1

0
w
1

0 1
w
Multiplexer controller method:

Problem Statement:
Draw ASM Chart for the following state machine:
A 2 bit up counter with output Q1Q0 and enable
signal ‘X’ is to be design. If ‘X’ = 0, counter
changes the state as ‘00-01-10-11-00’. If ‘X’ =
1, counter should remain in present state.
Design your circuit using JK FF and suitable
mux.
 State Table
Present State Next State Input Mux input

A B A+ B+ Mux 1 Mux 2

0 0 0 0 X’ 0 X

0 0 0 1 X

0 1 0 1 X’ X X’

0 1 1 0 X

1 0 1 0 X’ 1 X

1 0 1 1 X

1 1 1 1 X’ X’ X’

1 1 0 0 X
VHDL
 V  Very high speed integrated circuit
 H  Hardware
 D  Description
 L  Language

It is used to model digital system.

What is VHDL?
 A documentation language
 A simulation language
 A synthesis language
 Technology independent logic design
Introduction to VHDL
 HDL is a technique for describing the hardware
associated with a digital system.
 The VHDL design (also called a model) is similar
to the structure of an ordinary program, such as a C
program.
 The C program is compiled to make an executable
file, whereas the VHDL design is simulated to test
the validity of the hardware design
Comparing C program with VHDL simulation
VHDL Language
 VHDL has all the characteristics of a modern
programming language.
 Data types
 Predefined and user defined
 Variables, signals and constants
 Expressions
 Relational and Arithmetic
 Sequential statements
 If, Case, For loops
History of VHDL
 The development of VHDL was initiated in 1981
by the United States Department of Defense (DoD)
to address the hardware life cycle crisis. The
requirement was for a language with a wide range
of descriptive capability.
Structure of VHDL Module
Library
Design Entity

Entity Declaration

Architecture
 Design Units
 To describe an entity, VHDL provides
five different types of design units:
 Entity declaration
 Architecture body
 Configuration declaration
 Package declaration
 Package body
Entity Declaration
 Entity declaration describes the external view of
the entity (e.g. The input and output signal names).
 It specifies the name of the entity being modeled
and lists the sets of interface ports.
 It is most basic building block in a design.
 It specifies I/O pins of the circuit .
 Syntax :
Entity Entity_name is
port (Port_name :mode Port_type;
Port_name :mode Port_type);
End entity_name ;
Example
Entity for And Gate :-
entity ANDGate is
port ( A, B : in std_logic;
C : out std_logic );
end ANDGate;
Entity for 4:1 MUX :-
entity Mux is
port ( a,b,c,d : in std_logic; so,s1: in std_logic;
y : out std_logic );
end mux ;
From above examples
 Entity_name : It is an identifier defined by user.
 Port_name/Port_type : Name of Port and Port Date
types
 Modes:
 In(Input) :to read the value from user.
 Out :output
 Inout:Bi-directinal port
 Buffer :Outport with read capabilities .
Architecture
 The architecture body contains the internal
description of the entity. For example, as a set of
interconnected components that represents the
structure of the entity or as a set of concurrent or
sequential statements that represents the behavior
of the entity.

 After an entity has been modeled, it needs to be

validated by a VHDL system which consists of
analyzer and simulator.
Syntax of architecture

Architecture architecture_name of
entity_name is
{ block declaration }
Begin
{
}
End architecture_name ;
Architecture
 The internal details of an entity are
specified by an architecture body. This can
be specified either as a description of the
structure or as a description of the
behavior. There are three modeling styles:

 Data flow Style of Modeling

 Behavioral Style of Modeling
 Structural Style of Modeling
 Mixed Style of Modelling
Architecture
 Data flow Style of Modeling
 The flow of data through the entity is
expressed using concurrent signal
assignment statements. The structure of
entity is not specified .
 In this modeling style ,We can view the
data as flowing through a design from
input to output.
 Entity-Architecture for And Gate
entity ANDGate is
port ( A, B : in std_logic;
C : out std_logic );
end ANDGate;
Architecture dfand of ANDGate is
Begin
C <= A and B;
End dfand;
Entity-Architecture for Half
ADDER
entity hadder is
port ( A, B : in std_logic; A
XOR S
S,C : out std_logic ); B
end Hadder ;
Architecture dfha of hadder is C
And
Begin
S<= A xor B;
C <= A and B;
End dfha;
 Architecture Body (cont.)
 Behavioral Style of Modeling
 It specifies the behavior (function) of an entity
as a set of statements that are executed
sequentially in the specified order, and they are
specified inside a process statement.
 In general behavioral specification is a
description of outputs’ responses to inputs’
changes.
 It is highest level of abstraction supported in
VHDL.
And gate using behavioral
Modeling style
entity ANDGate is
port ( A, B : in std_logic;
C : out std_logic );
end ANDGate;
Architecture bmsand of ANDGate is
Begin
Process(A,B)
Begin
If (a=‘1’) and (b’1’) then
C<= ‘1’;
Else
C<= ‘0’;
End process ;
End bmsand;
 Architecture Body (cont.)
 Structural Style of Modeling
 An entity is described as a set of interconnected
components. It tells HOW the components
should be connected to achieve the expected
results.
H.A using structural modeling
style
entity hadder is
port ( A, B : in std_logic;
S,C : out std_logic );
end Hadder ;
Architecture smsha of hadder is
Component Xorgate is
Port (X,Y:in bit;Z:out bit);
End component ;
Component andgate is
Port (L,M:in bit;N:out bit);
End component ;
Begin
X1:Xorgate portmap(A,B,S);
X2: andgate portmap(A,B,C);
End smsha;
 Package Declaration
 It is used to store a set of common declarations,
such as components, types, procedures, and
functions. These can be imported into other design
units using a use clause.
 Package Declaration (cont.)
 How to use a Package
 In your VHDL source file, do this:
Example: using the package Std_logic_1164 from the library IEEE

Library Library Name ;

Use Library_name.package_name.all;
...
Library IEEE ;
Use IEEE.Std_logic_1164.all;
...
 Package Declaration (cont.)
 IEEE Packages:
 std_logic_1164
 std_logic_misc
 std_logic_components
 std_logic_textio
 std_logic_arith
 std_logic_unsigned
 std_logic_signed
 Package Declaration
 Package std_logic_1164 is in library IEEE
 Recommended:
 Use std_logic instead of bit
 Use std_logic_vector instead of bit_vector
 VHDL - Main Elements
VHDL Design File
Library IEEE; Library &
Use IEEE.Std_Logic_1164.All; package declaration

entity hadder is Entity declaration

port ( A, B : in std_logic;
S,C : out std_logic );
end Hadder ;

Architecture dfha of hadder is Architecture Specification

Begin
S<= A xor B;
C <= A and B;
End dfha;
Design FULL ADDER using Data flow modelling style VHDL

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Entity Fulladder is
Port(A,B,Cin :in bit;
S,Cout:out bit);
End fulladder;
Architecture Adder of Fulladder is
Begin
S<= A xor B xor Cin;
Cout<= (A and B) or (B and Cin) or (Cin And A);
End Adder;
Design 4 bit counter
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Entity c1 is
Port (Clk,reset: in STD_lOGIC ;
Q :out STD_LOGIC_VECTOR(3 DOWNTO 0));
End C1;
Architecture Counter of C1 is
Signal Count: out STD_LOGIC_VECTOR(3 DOWNTO 0);
Begin
Process(clk,reset)
Begin
If (reset=‘0’) then
Count <= “0000”;
Elseif (cLK=‘1’) then
Count <= Count +1;
end if ;
End if ;
End process;
Q<=count ;
End counter;
Data Objects

• There are three types of data

objects:
• Signals
• Can be considered as wires in a
schematic.
• Can have current value and future values.
• Variables and Constants
• Used to model the behavior of a circuit.
• Used in processes, procedures and
functions.
Variable
 Variables are useful in keeping track of certain values
within the context of a process or a function, but cannot be
used outsides processes or functions.
 Syntax:

variable <variable_name> is : type;

 Examples:
variable count_v: integer range 0 to 15;
variable data_v: std_logic_vector(7 downto 0);
variable condition_v: boolean;
Variable Declaration

• Variables are used for local storage of data.

• Variables are generally not available to
multiple components or processes.
• All variable assignments take place
immediately.
• Variables are more convenient than signals
for the storage of (temporary) data.
Constant Declaration

• A constant can have a single value of a given

type.
• A constant’s value cannot be changed during
the simulation.
• Constants declared at the start of an
architecture can be used anywhere in the
architecture.
• Constants declared in a process can only be
used inside the specific process.
CONSTANT constant_name : type_name [ : = value];

CONSTANT rise_fall_time : TIME : = 2 ns;

CONSTANT data_bus : INTEGER : = 16;
 Signal Declaration

• Signals are used for communication between

components.
• Signals are declared outside the process.
• Signals can be seen as real, physical signals.
• Some delay must be incurred in a signal
assignment.
Predefined Data Types

• bit (‘0’ or ‘1’)

• bit_vector (array of bits)
• integer
• real
• time (physical data type)
Integer
• Integer
• Minimum range for any implementation as defined
by standard: -2,147,483,647 to 2,147,483,647
• Integer assignment example
Real
• Real
• Minimum range for any implementation as defined
by standard: -1.0E38 to 1.0E38
• Real assignment example
Enumerated
• Enumerated
• User defined range
• Enumerated example
Physical
• Physical
• Can be user defined range
• Physical type example

• Time units are the only predefined physical type in

VHDL.
Array

• Array Used to collect one or more elements of a

similar type in a single construct.
• Elements can be any VHDL data type.
Thank You