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Video, Image & Signal Processing Seminars

Code:DSP Video, Image & Signal Processing Seminar

Table of Contents

Each tab includes an abstract and agenda for the presentation as well as information about the speaker

Video, Image & Signal Processing With FPGAs Altera

Model-Based Design Tutorial With Simulink The MathWorks & Altera

Panel Discussion: Developing FPGA Co-Processors Celoxica, Mentor Graphics,

Using ‘C’ Language & Modeling Tools Synplicity & The MathWorks

Video System Design With High-Performance Texas Instruments

Analog & FPGAs

Video Co-Processing With DSP & FPGA Inlet

Low-Cost Solutions for Video Compression Systems Barco

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Video, Image & Signal Processing Seminars

Video, Image & Signal Processing

® With FPGAs
Abstract:

The combined requirements of fast time to market and high performance processing are driving the
use of FPGAs in video, image and signal processing applications. Cost and power consumption are also
critical system design considerations. This presentation will cover the most recent enhancements
to FPGA and structured ASIC architectures, tools, and intellectual property (IP).

Agenda:

 Digital signal processing (DSP) capabilities in FPGAs and structured ASICs

- Improving system performance, cost and power using Altera’s recent silicon
enhancements for Stratix® II, Cyclone™ II, and HardCopy® II
- Video design examples
 Development tools
- Power-optimized design
- Using SOPC Builder for system integration with FPGAs, DSP and peripherals
- High-speed hardware debug

Speaker: Brian Jentz

Brian Jentz joined Altera in 2000 with the responsibilities of new product definition for digital signal
processing products. In 2003, he assumed the role of DSP Marketing Manager for the company.
Prior to joining Altera, Brian spent 7 years at Texas Instruments, most recently as a DSP Product
Specialist. He holds a BSEE from Purdue University and has completed course work towards an
MSEE at Georgia Tech.
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Video, Image & Signal Processing Seminars

®
Model-Based Design Tutorial for Video
Applications by The MathWorks & Altera
Abstract:

Today’s embedded vision systems are doing more than simply capturing, encoding, and transmitting vid-
eo data. They are quickly becoming the first line of intelligence for automotive safety systems, consumer
electronics/communication devices, advanced medical imaging, and smart surveillance cameras. Model-
Based Design enables engineers to rapidly develop algorithms, create bit-accurate system specifications,
automatically generate HDL code, and build test harnesses for the complex designs of these systems.

This tutorial will show how The MathWorks and Altera are providing development tools for engineers to
explore and evaluate design trade-offs, develop prototypes, and deploy their ideas on Altera® FPGAs.
The MathWorks and Altera partnership enables engineers to meet their design requirements and shrink
deadlines.

Agenda:
 Overview of Model-Based Design from The MathWorks
- Simulink, the Signal Processing Blockset, and the Video and Image Processing
Blockset libraries, environment, etc.
 Rapid modeling and simulation of a video system
- Designing a sample system
- Converting floating-point data types to fixed-point data types
- Creating an executable specification
- Tips for fast simulations
 Targeting FPGAs with Altera’s DSP Builder
- Generate FPGA design with real-time video capture and filtering
- Simulate FPGA design using Simulink test benches
- Incorporate design as processor peripheral using SOPC Builder
- Verify real-time application in hardware

Speaker: David Jackson

David Jackson is the product manager for video and signal processing at The MathWorks, Inc. His
professional interests center on new product development and launches, as well as technology adop-
tion issues. Prior to his current role with The MathWorks, David worked at Lucent Technologies, Analog
Devices, and Nextel Communications. He held positions in product marketing, product launch and new
product introduction, channel marketing, and business development. David holds a Masters in Marketing
and Computer Science from Boston College and a Bachelor of Science from Boston University. He is an
advisory board member to Boston College’s Carroll School of Management’s Marketing Department.

Speaker: Alex Soohoo

Alex Soohoo joined Altera in 2004 as a marketing manager for digital signal processing products.
Prior to joining Altera, Alex held management positions at IDT, PMC-Sierra, and LSI Logic (formerly
C-Cube Microsystems). He earned a BS in EECS from UC Berkeley and a MS in electrical and
computer engineering from UC Davis.
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Video, Image & Signal Processing Seminars

Panel: Developing FPGA Co-Processors Using ‘C’ Language

& Modeling Tools
How do you move your digital signal processing algorithm from the software realm into a hardware
implementation on your FPGA? This panel will examine the design challenges and available solutions
for moving your algorithm into an FPGA. The panel will examine key questions, including industry
adoption, quality of results, system integration issues, technology roadmaps, plus audience questions.

Moderator
Jim Smith, Director EDA Relations ®

Jim Smith is responsible for managing the relationships with all 3rd party EDA vendors. He joined Altera
in 2001. Before that time, he was the director of business development for ASIC and master program-
ming unit (MPU) for Toshiba America Electronics Corporation, where he managed their embedded
processor ASIC business. Prior to Toshiba, Jim had his own consulting company focused on emerging
technologies. Jim has held positions at Hitachi and Draper Labs. Jim graduated from the University of
Massachusetts at Amherst with a B.S. degree in electrical engineering.

Panel Members
Chris Sullivan, Director of Marketing

Chris Sullivan joined Celoxica in 1999 and has responsibility for the identification and management of
new technology. Chris has a background in software development, parallel processing architectures
and systems engineering management, both in commercial and academic sectors. Chris graduated
from the University of Sheffield, UK and his interests include novel parallel processing architectures,
business models for pervasive reconfigurable systems and behavioral design and synthesis.

Shawn McCloud, High-Level Synthesis Product Manager

Shawn McCloud, product manager for Catapult C Synthesis, has nearly 20 years of experience in semi-
conductor design. Shawn joined Mentor in 1994, where he has held positions in technical and product
marketing focused on register transfer level (RTL) and high-level synthesis. From 1986 to 1994, Shawn
worked for Motorola as a senior system engineer responsible for RISC- and CISC-based micro-proces-
sor design. Shawn received his B.S. degree in electrical and computer engineering from Case Western
Reserve University.
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Video, Image & Signal Processing Seminars

Dirk Seynhaeve, Director CAE DSP

Dirk Seynhaeve has 20 years of experience in the ASIC design and EDA industry. He joined
Synplicity to help define and roll out DSP solutions to add to the synthesis portfolio. Before, at Tera
Systems, as Director of Technical Marketing, Dirk focused on defining the product line strategies for
RTL hand-off strategies. Prior to Tera Systems, Dirk was Director of Technical Services at Tharas
Systems, following a position as Director of Applications at Escalade. Dirk’s initial background is in
DSP and processor design with Philips and Signetics. Dirk holds an MSEE from the KU Louvain
University, Belgium.

David Jackson, Product Manager for Video

& Signal Processing

David Jackson is product managerfor video and signal processing at The MathWorks. His professional
interests include new product development, launches and technology adoption issues. Prior to his cur-
rent role with The MathWorks, Dave worked at Lucent Technologies, Analog Devices, and Nextel Com-
munications. He held management positions in Product Marketing, Product Launch and New Product
Introduction, Channel Marketing, and Business Development. Dave holds a Bachelor of Science from
Boston University and a Masters from Boston College in Marketing & Computer Science. He is an
advisory board member to Boston College’s Carroll School of Management’s Marketing Department.
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Video, Image & Signal Processing Seminars

Video System Design with High-Performance

Analog & FPGAs
The requirements for video input span the spectrum of resolutions, sampling rates, and worldwide
standards. Combining analog-to-digital (A/D) and video decoder technology from Texas Instruments
along with Altera FPGAs enables a very flexible solution to meet these diverse requirements. This
presentation will discuss the latest generation of A/D and decoder technology and demonstrate how
developers can use off-the-shelf hardware and software tools from TI and Altera to quickly get a video
system up and running.

Agenda:
 A/D and video decoder technology
 Demonstration with TI and Altera hardware platforms

Speaker: Nate Johanningsmeier

Nate Johanningsmeier is a member of the Texas Instruments Analog Field Application Team in San
Jose supporting digital audio and video products.
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Video, Image & Signal Processing Seminars

Low-Cost Solutions for Video Compression Systems

Abstract:

This presentation will demonstrate that real-time video compression systems can be implemented in
low-cost Altera® Cyclone™ II FPGAs. The impact of system considerations on device cost will be
explored including choice of bit rate, image resolution, and frame rate trade-offs. Starting from available
compression IP cores (MPEG4/JPEG2000) from Barco, we will show how to build a single-chip FPGA to
implement a complete video processing architecture for the surveillance and security markets.

Speaker: Olivier Cantineau

Olivier Cantineau began working for Barco Silex in Belgium in 1998, and is currently head of image
processing activities. Barco Silex offers design services in the field of hardware (ASIC, SoC, FPGA,
PCB), embedded software (RISC, DSP), intellectual property and system design. Strong focus is placed
on image processing applications.

Olivier studied electronics engineering at the Université catholique de Louvain in Belgium from 1991 to
1996. He did his thesis on designing a VHDL IP for MPEG-2 MP@ML decoding. Before joining Barco
Silex, he worked for two years as researcher in the microelectronics and telecommunication laboratories
of the university, with particular interest in image and video compression.