In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after

every two years. While such high packing densities allow more functionality to be incorporated on the
same chip, it is, however, becoming an increasingly ponderous task for the foundries across the globe
to manufacture defect free silicon. This predicament has exalted the significance of Design for
testability (DFT) in the design cycle over the last two decades. Shipping a defective part to a customer
could not only result in loss of goodwill for the design companies, but even worse, might prove out to
be catastrophic for the end users, especially if the chip is meant for automotive or medical
applications.

Scan chain testing is a method to detect various manufacturing faults in the silicon. Although many
types of manufacturing faults may exist in the silicon, in this post, we would discuss the method to
detect faults like- shorts and opens.

Figure 1 shows the structure of a Scan Flip-Flop. A multiplexer is added at the input of the flip-flop
with one input of the multiplexer acting as the functional input D, while other being Scan-In (SI). The
selection between D and SI is governed by the Scan Enable (SE) signal.

Figure 1: Scan Flip-Flop

Using this basic Scan Flip-Flop as the building block, all the flops are connected in form of a chain,
which effectively acts as a shift register. The first flop of the scan chain is connected to the scan-in
port and the last flop is connected to the scan-out port. The Figure 2 depicts one such scan chain
where clock signal is depicted in red, scan chain in blue and the functional path in black. Scan testing
is done in order to detect any manufacturing fault in the combinatorial logic block. In order to do so,
the ATPG tool try to excite each and every node within the combinatorial logic block by applying input
vectors at the flops of the scan chain.
 Figure 2: A Typical Scan Chain
Scan chain operation involves three stages: Scan-in, Scan-capture and Scan-out. Scan-in involves
shifting in and loading all the flip-flops with an input vector. During scan-in, the data flows from the
output of one flop to the scan-input of the next flop not unlike a shift register. Once the sequence is
loaded, one clock pulse (also called the capture pulse) is allowed to excite the combinatorial logic
block and the output is captured at the second flop. The data is then shifted out and the signature is
compared with the expected signature. Modern ATPG tools can use the captured sequence as the
next input vector for the next shift-in cycle. Moreover, in case of any mismatch, they can point the
nodes where one can possibly find any manufacturing fault. Figure 3 shows the sequence of events
that take place during scan-shifting and scan-capture.

Figure 3: Waveforms for Scan-Shift and Capture

Shift Frequency: A trade-off between Test Cost and Power Dissipation

It must be noted that the number of shift-in and shift-out cycles is equal to the number of flip-flops that
are part of the scan chain. For a scan chain with, let’s say, 100 flops, one would require 100 shift-in
cycles, 1 capture cycle and 100 shift-out cycles. The total testing time is therefore mainly dependent
on the shift frequency because there is only capture cycle. Tester time is a significant parameter in
 determining the cost of a semiconductor chip and cost of testing a chip may be as high as 50% of the
total cost of the chip. From timing point of view, higher shift frequency should not be an issue because
the shift path essentially comprises of direct connection from the output of the preceding flop to the
scan-input of the succeeding flop and therefore setup timing check would always be relaxed. Despite
the fact that higher shift frequency would mean lower tester time and hence lower cost, the shift
frequency is typically low (of the order of 10s of MHz). The reason for shifting at slow frequency lies in
dynamic power dissipation.
It must be noted that during shift mode, there is toggling at the output of all flops which are part of the
scan chain, and also within the combinatorial logic block, although it is not being captured. This
results in toggling which could perhaps be more than that of the functional mode. Higher shift
frequency could lead to two scenarios:
 Voltage Drop: Higher rate of toggling within the chip would result in drawing more current from the
voltage supply. And hence there would be a voltage droop because of the IR drop. This IR drop could
well drop the voltage below the safe margin and the devices might fail to operate properly.
 Increased Die Temperature: High switching activity might create local hot-spots within the die and
thereby increase the temperature above the worst-case temperature for which timing was closed. This
could again result in failure of operation, or in the worst case, it might cause thermal damage to the
chip.
Therefore, there exists a trade-off. It is desired to run the scan shift at a lower frequency which must
be dictated by the maximum permissible power dissipation within the chip. At the same time, the shift-
frequency should not be too low, otherwise, it would risk increasing the tester time and hence the cost
of the chip!