Laboratory Report Cover Sheet

SRM Institute Of Science And Technology

Faculty of Engineering and Technology
Department of Electronics and Communication Engineering
15EC302J VLSI Design
VI Semester, 2017-18 (Even Semester)

Name :

Register No. :

Venue :

Title of Experiment :

Date of Conduction :

Date of Submission :

Marks
Particulars Max. Marks
Obtained

Pre Lab 05

Design, HDL Code 15

Post Lab 5

Output verification 10
&viva
Lab Report 05

Total 40

REPORT VERIFICATION

Staff Name :

Signature :