2017

ASSIGNMENT-2
Digital Design with FPGA

I C V Subbarao Naidu
17MVD0109(M.Tech vlsi)
10/31/2017
Aim: To design and implement the given specification in ALTERA DE2-115 Board.
Software Details:
For design Functional Simulation: ModelSim
For design Synthesis: Quartus II
For design Implementation: Quartus II
Hardware Details:
Family: Cyclone II
Device: EP2C
Package: FBGA
Pin count: 786
Specification:
Write a program for sequence detector, when 00 is in sequence output would be 1 and also when
11 is in sequence output would be 1 again.
RTL CODE:
module fsm11(x,clk,z);
input x,clk;
output reg z;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
reg [1:0]ps,ns;
always@(posedge clk )
begin
ps<=ns;
end
always@(ps or x)
begin
case(ps)
s0:begin
z=x?0:1;
 ns=x?s2:s1;
end
s1:begin
z=x?0:1;
ns=x?s2:s0;
end
s2:begin
z=x?1:0;
ns=x?s3:s0;
end
s3:begin
z=x?1:0;
ns=x?s2:s0;
end
default:begin
z=1'b0;
ns=s0;
end
endcase
end
endmodule

TEST BENCH:
module fsm_tst();
reg x,clk;
wire z;
fsm11 f(.x(x),.clk(clk),.z(z));
initial
 clk=1'b0;
initial
begin
#100
x=1'b0;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b0;
#100
x=1'b0;
#100
x=1'b0;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b0;
#100
x=1'b1;
#100
x=1'b1;
#100
x=1'b0;
end
always
#50clk=~clk;
initial
#2000$stop;
endmodule

Functional Simulation:

State diagram:
QUARTUS (Program):
module vendingmachine(ticket,change,coin,rst,clk);
output reg ticket,change;
input [1:0] coin;
input clk,rst;
reg[2:0] state;
reg[2:0] next_state;
parameter [2:0] sinit=3'b000;
parameter [2:0] s1=3'b001;
parameter [2:0] s2=3'b010;
always@ (posedge clk)
begin
ticket=0;
change=0;
 if(rst==0)
state=sinit;
else
state=next_state;
end
always@ (*)
begin
case(state)
sinit:
begin
if(coin==2'b01)
next_state=s1;
else if(coin==2'b10)
next_state=s2;
else
next_state=sinit;
end
s1:
begin
if(coin==2'b01)
next_state=s2;
else
if(coin==2'b10)
begin
next_state=sinit;
ticket=1;
change=0;
end
end

s2:
begin
if(coin==2'b01)
begin
next_state=sinit;
ticket=1;
change=0;
end
else
if(coin==2'b10)
begin
next_state=sinit;
ticket=1;
change=1;
end
end

default:
next_state=sinit;
endcase
end
endmodule

OUTPUT: