DATASHEET

CD4066BMS
CMOS Quad Bilateral Switch Rev X.00
Jan 13, 2017

Features
• For Transmission or Multiplexing of Analog or Digital
Signals
• High Voltage Types (20V Rating)
• 15V Digital or 7.5V Peak-to-Peak Switching
Description
CD4066BMS is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin for pin compatible with CD4016B, but exhibits a much
lower on state resistance. In addition, the on-state resistance
is relatively constant over the full input signal range.

• 125 Typical On-State Resistance for 15V Operation The CD4066BMS consists of four independent bilateral
switches. A single control signal is required per switch. Both
• Switch On-State Resistance Matched to Within 5 the p and the n device in a given switch are biased on or off
Over 15V Signal Input Range simultaneously by the control signal. As shown in Figure 1,
• On-State Resistance Flat Over Full Peak-to-Peak Sig- the well of the n channel device on each switch is either tied
nal Range to the input when the switch is on or to VSS when the switch
is off. This configuration eliminates the variation of the switch
• High On/Off Output Voltage Ratio transistor threshold voltage with input signal, and thus keeps
- 80dB Typ. at FIS = 10kHz, RL = 1k the on-state resistance low over the full operating signal
range.
• High Degree of Linearity: <0.5% Distortion Typ. at
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS  10V, RL = 10k The advantages over single channel switches include peak
input signal voltage swings equal to the full supply voltage,
• Extremely Low Off-State Switch Leakage Resulting in
and more constant on-state impedance over the input signal
Very Low Offset Current and High Effective Off-State
range. For sample and hold applications, however, the
Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25oC
CD4016B is recommended.
• Extremely High Control Input Impedance (Control Cir-
The CD4066BMS is supplied in these 14-lead outline pack-
cuit Isolated from Signal Circuit): 1012 Typ.
ages:
• Low Crosstalk Between Switches: -50dB Typ. at FIS =
Braze Seal DIP H4Q
8MHz, RL = 1k
Frit Seal DIP H1B
• Matched Control Input to Signal Output Ceramic Flatpack H3W
Capacitance: Reduces Output Signal Transients
• Frequency Response, Switch on = 40MHz (Typ.)
Pinout
• 100% Tested for Quiescent Current at 20V
CD4066BMS
• 5V, 10V and 15V Parametric Ratings TOP VIEW
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
IN/OUT A 1 14 VDD
“B” Series CMOS Devices”
OUT/IN A 2 13 CONT A

Applications OUT/IN B 3 12 CONT D

• Analog Signal Switching/Multiplexing IN/OUT B 4 11 IN/OUT D

- Signal Gating - Modulator CONT B 5 10 OUT/IN D
- Squelch Control - Demodulator
CONT C 6 9 OUT/IN C
- Chopper - Commutating Switch
VSS 7 8 IN/OUT C
• Digital Signal Switching/Multiplexing
• Transmission Gate Logic Implementation
• Analog to Digital & Digital to Analog Conversion
• Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain

Rev X.00 Page 1 of 9

Jan 13, 2017
CD4066BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm  0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . ja jc
Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 0.5 A
2 +125oC - 50 A
VDD = 18V, VIN = VDD or GND 3 -55oC - 0.5 A
oC
Input Leakage Current IIL VC = VDD or GND 1 +25 -100 - nA
oC
2 +125 -1000 - nA
3 -55oC -100 - nA
oC
Input Leakage Current IIH VC = VDD or GND 1 +25 - 100 nA
o
2 +125 C - 1000 nA
o
3 -55 C - 100 nA
Input/Output Leakage IOZL VC = 0V, VIS = 18V, VDD = 20 1 +25oC -100 - nA
Current (Switch OFF) VOS = 0V, VIS = 0V, o
2 +125 C -1000 - nA
VOS = 18V
o
VDD = 18V 3 -55 C -100 - nA
o
IOZH VDD = 20 1 +25 C - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
o
On Resistance RON5 VC = VDD, RL = 10kW VDD = 5V 1 +25 C 1050 - 
returned to VDD - o
RON10 VDD = 10V 1 +25 C 400 - 
VSS/2
RON15 VDD = 15V 1 +25oC 240 - 
VIS = VSS to VDD
On Resistance RON5 VDD = 5V 1, 2 +125oC - 1300 
oC 
-55 - 800
o
On Resistance RON10 VDD = 10V 1, 2 +125 C - 550 
-55oC - 310 
On Resistance RON15 VDD = 15V 1, 2 +125oC - 320 
o
-55 C - 220 
o
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25 C VOH > VOL < V
(Note 3) VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Switch Threshold SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 4.1 - V
RL = 100k to VDD
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND 1, 2, 3 +25oC, +125oC, -55oC 14.1 - V
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1 +25oC -2.8 -0.7 V
o
P Threshold Voltage VPTH VSS = 0V, IDD = 10A 1 +25 C 0.7 2.8 V

Rev X.00 Page 2 of 9

Jan 13, 2017
CD4066BMS

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Control Input Low VILC5 VDD = 5V 1, 2, 3 +25oC, +125oC, -55oC - 1 V
Voltage (Note 2) oC,
VILC15 VDD = 15V 1, 2, 3 +25 +125oC, -55oC - 2 V
|IIS| < 10a, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
Control Input High VIHC VDD = 5V, |IIS| = .51mA, 4.6V < 1 +25oC 3.5 - V
Voltage VOS < 0.4V
(Note 2, Figure 2)
VDD = 5V, |IIS| = .36mA, 4.6V < 2 +125oC 3.5 - V
VIS = VSS and VIS =
VOS < 0.4V
VDD
VDD = 5V, |IIS| = .64mA, 4.6V < 3 -55oC 3.5 - V
VOS < 0.4V
VIHC VDD = 15V, |IIS| = 3.4mA, 13.5V < 1 +25oC 11 - V
VOS <1.5V
VDD = 15V, |IIS| = 2.4mA, 13.5V < 2 +125oC 11 - V
VOS < 1.5V
VDD = 15V, |IIS| = 4.2mA, 13.5V < 3 -55oC 11 - V
VOS <1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. VDD = 2.8V/3.0V, RL = 100K to VDD
implemented. VDD = 20V/18V, RL = 10K to VDD
2. Go/No Go test with limits applied to inputs.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE MIN MAX UNITS
o
Propagation Delay TPLH VC = VDD = 5V, VSS = GND 9 +25 C - 40 ns
Signal Input to Signal TPHL (Notes 2, 3)
10, 11 +125oC, -55oC - 54 ns
Output
Propagation Delay TPHZ/ZH VIS = VDD = 5V (Notes 1, 2) 9 +25oC - 70 ns
Turn-On, Turn-Off TPLZ/ZL oC,
10, 11 +125 -55oC - 95 ns
NOTES:
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.25 A
o
+125 C - 7.5 A
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 A
+125oC - 15 A
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 0.5 A
+125oC - 30 A
Control Input Low VILC10 VDD = 10V 1, 2 +25 C, +125oC,
o
- 2 V
Voltage -55oC
|IIS| < 10a, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
Control Input High VIHC10 VDD = 10V, VIS = VDD or GND 2 +25oC, +125oC, 7 - V
Voltage (See Figure 2) -55oC

Rev X.00 Page 3 of 9

Jan 13, 2017
CD4066BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation Delay TPLH VDD = 10V 1, 2, 3 +25oC - 20 ns
Signal Input to TPHL VDD = 15V 1, 2, 3 +25oC - 15 ns
Signal Output
Propagation Delay TPHZ/ZH VDD = 10V 1, 2, 3 +25oC - 40 ns
Turn-On, Turn-Off TPLZ/ZL oC
VDD = 15V 1, 2, 3 +25 - 30 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 A
oC
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1, 4 +25 -2.8 -0.2 V
N Threshold Voltage VTN VDD = 10V, ISS = -10A 1, 4 +25oC - 1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V
oC
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25 - 1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - SSI IDD 0.1A
ON Resistance RONDEL10  20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9

Rev X.00 Page 4 of 9

Jan 13, 2017
CD4066BMS

TABLE 6. APPLICABLE SUBGROUPS (Continued)

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883 TEST READ AND RECORD

CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V  -0.5V 50kHz 25kHz
Static Burn-In 1 (Note 1) 2, 3, 9, 10 1, 4-8, 11-13 14
Static Burn-In 2 (Note 1) 2, 3, 9, 10 7 1, 4-6, 8, 11-14
Dynamic Burn-In (Note 1) - 7 14 2, 3, 9, 10 5, 6, 12, 13 1, 4, 8, 11
Irradiation (Note 2) 2, 3, 9, 10 7 1, 4-6, 8, 11-14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V  0.5V

Functional Diagram
TRUTH TABLE EACH SWITCH

14
INPUT OUTPUT
IN/OUT 1 VDD
SW VC VIS VOS
SIG A A
OUT/IN 2 13 CONTROL A 1 0 0
1 1 1
OUT/IN 3 SW 12 CONTROL D
D 0 0 Open
SIG B
IN/OUT 4 11 IN/OUT 0 1 Open
SIG D Positive Logic: Switch ON VC = “1”
SW
CONTROL B 5 B 10 OUT/IN Switch OFF VC = “0”

CONTROL C 6 9 OUT/IN
SW SIG C
C
VSS 7 8 IN/OUT

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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

Rev X.00 Page 5 of 9

Jan 13, 2017
CD4066BMS

Schematic
SWITCH
NORMAL OPERATION CONTROL
CONTROL LINE BIASING:
IN
VIS SWITCH ON, VC “I” = VDD VDD
SWITCH OFF, VC “O” = VSS

P N * ALL CONTROL INPUTS ARE

P OUT PROTECTED BY THE CMOS
N VOS PROTECTION NETWORK
CONTROL
VC
N
NOTE: VSS
* VSS SIGNAL LEVEL RANGE: All “P” Substrates
VSS  VIS  VDD Connected to VDD

FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCH-

ES AND ITS ASSOCIATED CONTROL CIRCUITRY
KEITHLY 160 DIGITAL
VDD
MULTIMETER

IIS TG 1k
10k
“ON”
VIS
CD4066BMS
VOS RANGE Y
1 OF 4 SWITCHES HP
X-Y
MOSELEY
VSS PLOT TER
7030A
|VIS - VOS| X
RON =
|IIS|

FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASURE-
FOR CONTROL INPUT HIGH VOLTAGE (VIHC) MENT CIRCUIT
SPECIFICATION

CIOS
MEASURED ON BOONTON
VC = -5V VDD = +5V CAPACITANCE BRIDGE
MODEL 75A (1MHz) VC = VSS VDD
TEST FIXTURE CAPACITANCE
NULLED OUT
CD4066BMS VIS = VDD
1 OF 4 SWITCHES CD4066BMS ALL UNUSED TERMINALS
1 OF 4 SWITCHES ARE CONNECTED TO VSS

CIS COS 
VSS = -5V
VSS

FIGURE 4. CAPACITANCE TEST CIRCUIT FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE

VC = VDD VDD +10V

ALL UNUSED INPUTS VC VDD ALL UNUSED TERMINALS
ARE CONNECTED TO VSS tr = tf = 20ns ARE CONNECTED TO VSS
ViS VOS
CD4066BMS VIS VOS
CD4066BMS
1 OF 4 SWITCHES
1 OF 4 SWITCHES
50 200k
pF
VDD VSS 1k 10k
tr = tf = 20ns VSS

FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS) FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT
TO SIGNAL OUTPUT (VOS)

Rev X.00 Page 6 of 9

Jan 13, 2017
CD4066BMS

REP
VC RATE
tr = tf = 20ns

1
VOS 90% 0
10%
20ns
20ns

ALL UNUSED INPUTS

VC = VDD VDD +10V VC VDD = +10V ARE CONNECTED TO VSS
VDD ALL UNUSED TERMINALS
tr = tf = 20ns ARE CONNECTED TO VSS tr = tf = 20ns
VOS = 1/2VOS
VDD VOS VIS = +10V AT 1kHz
CD4066BMS CD4066BMS
1 OF 4 SWITCHES 1 OF 4 SWITCHES
50 50 1k
1k
pF pF
VSS VSS

FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETI-
SIGNAL OUTPUT. DELAY IS MEASURED AT VOS TION RATE
LEVEL OF +10% FROM GROUND (TURN ON) OR
ON-STATE OUTPUT LEVEL (TURN OFF).

10 2 3 7 9 12
10 2 3 7 9 12
CLOCK
CLOCK 14 PE J1 J2 J3 J4 J5
14 PE J1 J2 J3 J4 J5 EXT 15 CD4018B
RESET 13 RESET
15 CD4018B
1 Q1 Q2
1 Q1 Q2

1 1 2 5 4
5 4 /4 CD4066B

1 13 12 9 8 6 5 2 1
3 7 6
2
1/ CD4049B
3
3 2 5 CD4001B
9 10
1/
4
3 CD4049B 6
CD4001B
5 4 11 10 4 3
8
10
9
6 5 13
12 12 6 5 11 SIGNALS
11 OUTPUTS
13 CHANNEL 1
12 11 12 2 LPF
SIGNALS
INPUTS CHANNEL 1 1 10K
1 2 /6 CD4049B
5 1
CHANNEL 2 CD4066B 3
4 CHANNEL 2
4 3 LPF
CHANNEL 3 9
8
4 1/ CD4066B 3 8 10K
CHANNEL 4 4 CD4066B
11 10
11
10K CHANNEL 3
PACKAGE COUNT 9 LPF
2 - CD4001B
1 - CD4049B 10K
3 - CD4066BMS CLOCK VDD
2 - CD4018B
30% (VDD - VSS) CHANNEL 4
MAX. ALLOWABLE 10 LPF
SIGNAL LEVEL VSS
CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4 10K

FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM

Rev X.00 Page 7 of 9

Jan 13, 2017
CD4066BMS

+5
ANALOG INPUTS (5V)

-5 VDD = +5V
VDD = 5V
CD4066BMS
5V
SWA
0
SWB
IN CD4054B
SWC

SWD

DIGITAL
CONTROL
INPUTS

VSS = 0V
VEE = -5V ANALOG OUTPUTS (5V) VSS = -5V

FIGURE 11. BIDIRECTIONAL SIGNAL TRANSMISSION VIA DIGITAL CONTROL LOGIC

Typical Performance Characteristics

CHANNEL ON-STATE RESISTANCE (RON) ()

CHANNEL ON-STATE RESISTANCE (RON) ()

SUPPLY VOLTAGE (VDD - VEE) = 5V SUPPLY VOLTAGE (VDD - VEE) = 10V

600 300
AMBIENT TEMPERATURE
(TA) = +125oC AMBIENT TEMPERATURE
500 250 (TA) = +125oC

400 200

+25oC
300 150

+25oC -55oC
200 100

-55oC
100 50

0 0
-4 -3 -2 -1 0 1 2 3 4 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 12. TYPICAL ON-STATE RESISTANCE vs INPUT FIGURE 13. TYPICAL ON-STATE vs INPUT SIGNAL VOLTAGE
SIGNAL VOLTAGE (ALL TYPES) (ALL TYPES).
CHANNEL ON-STATE RESISTANCE (RON) ()
CHANNEL ON-STATE RESISTANCE (RON) ()

SUPPLY VOLTAGE (VDD - VSS) = 15V AMBIENT TEMPERATURE

(TA) = +25oC
300 600

250 500 SUPPLY VOLTAGE (VDD - VSS) = 5V

200 400
AMBIENT TEMPERATURE
(TA) = +125oC
150 300

100 +25oC 200

10V
50 -55oC 100
15V

0 0
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 14. TYPICAL ON-STATE RESISTANCE vs INPUT FIGURE 15. ON-STATE RESISTANCE vs INPUT SIGNAL
SIGNAL VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)

Rev X.00 Page 8 of 9

Jan 13, 2017
CD4066BMS

Typical Performance Characteristics (Continued)

104
AMBIENT TEMPERATURE (TA) = +25oC 8 AMBIENT TEMPERATURE (TA) = +25oC

POWER DISSIPATION PER PACKAGE (PD) (W)

3 VDD = 2.5V, VSS = -2.5V 6
INPUT = TERM 1, OUTPUT = TERM 2 4
10K
RL = 100K 1K SUPPLY VOLTAGE (VDD) = 15V
OUTPUT VOLTAGE (VO) (V)

2 2
500
103 8 10V
1
100 6
4 VDD
0 VC = VDD VDD 14
100 2 5V
5
VIS CD4066BMS VOS f
-1 500 1 OF 4 102 6 CD4066/
8 BMS
SWITCHES 6 12
-2 1K RL 4 13
10K
ALL UNUSED TERMINALS VSS 2 7
100K ARE CONNECTED TO VSS
-3 VSS
10
-3 -2 -1 0 1 2 3 4 2 4 6 8 2 4 6 8
10 102 103
INPUT VOLTAGE (VI) (V)
SWITCHING FREQUENCY (f) (kHz)

FIGURE 16. TYPICAL ON CHARACTERISTICS FOR 1 OF 4 FIGURE 17. POWER DISSIPATION PER PACKAGE vs
CHANNELS SWITCHING FREQUENCY

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.
Special Considerations Grid graduations are in mils (10-3 inch).

In applications that employ separate power sources to drive No VDD current will flow through RL if the switch current
VDD and the signal inputs, the VDD current capability should flows into terminals 2, 3, 9, or 10.
exceed VDD/RL (RL = effective external load of the four
METALLIZATION: Thickness: 11kÅ 14kÅ, AL.
CD4066B bilateral switches). This provision avoids any per-
manent current flow or clamp action on the VDD supply PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
when power is applied or removed from the CD4066B. BOND PADS: 0.004 inches X 0.004 inches MIN
In certain applications, the external load-resistor current may DIE THICKNESS: 0.0198 inches - 0.0218 inches
include both VDD and signal line components. To avoid
drawing VDD current when switch current flows into termi-
nals 1, 4, 8 or 11 the voltage drop across the bidirectional
switch must not exceed 0.8 volts (calculated from RON val-
ues shown).

Rev X.00 Page 9 of 9

Jan 13, 2017