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ADSP-BF592: Blackfin Embedded Processor
ADSP-BF592: Blackfin Embedded Processor
Embedded Processor
ADSP-BF592
FEATURES PERIPHERALS
Up to 400 MHz high performance Blackfin processor Four 32-bit timers/counters, three with PWM support
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 2 dual-channel, full-duplex synchronous serial ports (SPORT),
40-bit shifter supporting eight stereo I2S channels
RISC-like register and instruction model for ease of 2 serial peripheral interface (SPI) compatible ports
programming and compiler-friendly support 1 UART with IrDA support
Advanced debug, trace, and performance monitoring Parallel peripheral interface (PPI), supporting ITU-R 656
Accepts a wide range of supply voltages for internal and I/O video data formats
operations, see Operating Conditions on Page 16 2-wire interface (TWI) controller
Off-chip voltage regulator interface 9 peripheral DMAs
64-lead (9 mm × 9 mm) LFCSP package 2 memory-to-memory DMA channels
MEMORY Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
68K bytes of core-accessible memory
hysteresis
(See Table 1 on Page 3 for L1 and L3 memory size details)
Debug/JTAG interface
64K byte L1 instruction ROM
On-chip PLL capable of frequency multiplication
Flexible booting options from internal L1 ROM and SPI mem-
ory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
WATCHDOG TIMER
SPORT1
PORT F
VOLTAGE REGULATOR INTERFACE JTAG TEST AND EMULATION
SPI0
PERIPHERAL
TIMER2–0
ACCESS BUS
B
UART GPIO
INTERRUPT
CONTROLLER
PPI
SPORT0
L1 INSTRUCTION L1 INSTRUCTION L1 DATA
DMA PORT G
ROM SRAM SRAM
CONTROLLER DMA SPI1
ACCESS
DCB BUS TWI
DEB
BOOT
ROM
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies. Technical Support www.analog.com
ADSP-BF592* PRODUCT PAGE QUICK LINKS
Last Content Update: 07/13/2017
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ADSP-BF592
TABLE OF CONTENTS
Features ................................................................. 1 Related Signal Chains ........................................... 13
Memory ................................................................ 1 Signal Descriptions ................................................. 14
Peripherals ............................................................. 1 Specifications ........................................................ 16
General Description ................................................. 3 Operating Conditions ........................................... 16
Portable Low Power Architecture ............................. 3 Electrical Characteristics ....................................... 18
System Integration ................................................ 3 Absolute Maximum Ratings ................................... 20
Blackfin Processor Core .......................................... 3 ESD Sensitivity ................................................... 20
Memory Architecture ............................................ 5 Package Information ............................................ 21
Event Handling .................................................... 5 Timing Specifications ........................................... 22
DMA Controllers .................................................. 6 Output Drive Currents ......................................... 36
Processor Peripherals ............................................. 6 Test Conditions .................................................. 37
Dynamic Power Management .................................. 8 Environmental Conditions .................................... 40
Voltage Regulation ................................................ 9 64-Lead LFCSP Lead Assignment ............................... 41
Clock Signals ....................................................... 9 Outline Dimensions ................................................ 43
Booting Modes ................................................... 11 Automotive Products .............................................. 44
Instruction Set Description ................................... 12 Ordering Guide ..................................................... 44
Development Tools ............................................. 12
Additional Information ........................................ 13
REVISION HISTORY
7/13—Rev. A to Rev. B
Corrected Processor Block Diagram ............................. 1
Updated Development Tools .................................... 12
Updated text in Signal Descriptions ............................ 14
Corrected VDDINT rating in Table 14,
Absolute Maximum Ratings ..................................... 20
SP
I3 L3 B3 M3 FP
I2 L2 B2 M2 P5
I1 L1 B1 M1 DAG1 P4
I0 L0 B0 M0 P3
DAG0
P2
DA1 32
P1
DA0 32
P0
TO MEMORY
32 32
RAB PREG
SD 32
LD1 32 32 ASTAT
LD0 32
32
SEQUENCER
R7.H R7.L
R6.H R6.L
R5.H R5.L ALIGN
R4.H R4.L 16 16
8 8 8 8
R3.H R3.L
R2.H R2.L DECODE
R1.H R1.L BARREL
R0.H R0.L SHIFTER 40 40 LOOP BUFFER
40 40
A0 A1 CONTROL
UNIT
32
32
• I2S mode
• Packed I2S mode
• Left-justified mode
SCLK d CCLK
BLACKFIN
CLKOUT (SCLK) Figure 5. Frequency Modification Methods
CLKBUF
EN TO PLL CIRCUITRY All on-chip peripherals are clocked by the system clock (SCLK).
EN The system clock frequency is programmable by means of the
SELECT SSEL3–0 bits of the PLL_DIV register. The values programmed
560 ⍀ into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 4 illustrates typical system clock ratios.
EXTCLK CLKIN XTAL
330 ⍀*
FOR OVERTONE Table 4. Example System Clock Ratios
OPERATION ONLY:
Example Frequency Ratios
18 pF * 18 pF * Signal Name Divider Ratio (MHz)
SSEL3–0 VCO/SCLK VCO SCLK
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING 0010 2:1 100 50
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE 0110 6:1 300 50
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀. 1010 10:1 400 40
Figure 4. External Crystal Connections
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
A third-overtone crystal can be used for frequencies above
changed dynamically without any PLL lock latencies by writing
25 MHz. The circuit is then modified to ensure crystal operation
the appropriate values to the PLL divisor register (PLL_DIV).
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper- The core clock (CCLK) frequency can also be dynamically
ation is discussed in detail in (EE-168) Using Third Overtone changed by means of the CSEL1–0 bits of the PLL_DIV register.
Crystals with the ADSP-218x DSP on the Analog Devices web- Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
site (www.analog.com)—use site search on “EE-168.” Table 5. This programmable core clock capability is useful for
fast core frequency modifications.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and Table 5. Core Clock Ratios
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying Example Frequency Ratios
the CLKIN signal by a programmable 5× to 64× multiplication Signal Name Divider Ratio (MHz)
factor (bounded by specified minimum and maximum VCO CSEL1–0 VCO/CCLK VCO CCLK
frequencies). The default multiplier is 6×, but it can be modified
00 1:1 300 300
by a software instruction sequence.
01 2:1 300 150
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and 10 4:1 400 100
SCLK rates depend on the applied voltages VDDINT and VDDEXT; 11 8:1 200 25
the VCO is always permitted to run up to the frequency speci-
fied by the part’s instruction rate. The EXTCLK pin can be The maximum CCLK frequency both depends on the part’s
configured to output either the SCLK frequency or the input instruction rate (see Ordering Guide) and depends on the
buffered CLKIN frequency, called CLKBUF. When configured applied VDDINT voltage. See Table 8 for details. The maximal sys-
to output SCLK (CLKOUT), the EXTCLK pin acts as a refer- tem clock rate (SCLK) depends on the chip package and the
ence signal in many timing specifications. While three-stated by applied VDDINT and VDDEXT voltages (see Table 10).
default, it can be enabled using the VRCTL register.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF592 pro-
cessor (and related processors) can be ordered from any Analog
Devices sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF59x Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF592 Blackfin Processor Anomaly List
Driver
Signal Name Type Function Type
Port F: GPIO and Multiplexed Peripherals
PF0–GPIO/DR1SEC/PPI_D8/WAKEN1 I/O GPIO/SPORT1 Receive Data Secondary/PPI Data 8/Wake Enable 1 A
PF1–GPIO/DR1PRI/PPI_D9 I/O GPIO/SPORT1 Receive Data Primary/PPI Data 9 A
PF2–GPIO/RSCLK1/PPI_D10 I/O GPIO/SPORT1 Receive Serial Clock/PPI Data 10 A
PF3–GPIO/RFS1/PPI_D11 I/O GPIO/SPORT1 Receive Frame Sync/PPI Data 11 A
PF4–GPIO/DT1SEC/PPI_D12 I/O GPIO/SPORT1 Transmit Data Secondary/PPI Data 12 A
PF5–GPIO/DT1PRI/PPI_D13 I/O GPIO/SPORT1 Transmit Data Primary/PPI Data 13 A
PF6–GPIO/TSCLK1/PPI_D14 I/O GPIO/SPORT1 Transmit Serial Clock/PPI Data 14 A
PF7–GPIO/TFS1/PPI_D15 I/O GPIO/SPORT1 Transmit Frame Sync/PPI Data 15 A
PF8–GPIO/TMR2/SPI0_SSEL2/WAKEN0 I/O GPIO/Timer 2/SPI0 Slave Select Enable 2/Wake Enable 0 A
PF9–GPIO/TMR0/PPI_FS1/SPI0_SSEL3 I/O GPIO/Timer 0/PPI Frame Sync 1/SPI0 Slave Select Enable 3 A
PF10–GPIO/TMR1/PPI_FS2 I/O GPIO/Timer 1/PPI Frame Sync 2 A
PF11–GPIO/UA_TX/SPI0_SSEL4 I/O GPIO/UART Transmit/SPI0 Slave Select Enable 4 A
PF12–GPIO/UA_RX/SPI0_SSEL7/TACI2–0 I/O GPIO/UART Receive/SPI0 Slave Select Enable 7/Timers 2–0 Alternate Input A
Capture
PF13–GPIO/SPI0_MOSI/SPI1_SSEL3 I/O GPIO/SPI0 Master Out Slave In/SPI1 Slave Select Enable 3 A
PF14–GPIO/SPI0_MISO/SPI1_SSEL4 I/O GPIO/SPI0 Master In Slave Out/SPI1 Slave Select Enable 4 A
(This pin should always be pulled high through a 4.7 kΩ resistor,
if booting via the SPI port.)
PF15–GPIO/SPI0_SCK/SPI1_SSEL5 I/O GPIO/SPI0 Clock/SPI1 Slave Select Enable 5 A
Port G: GPIO and Multiplexed Peripherals
PG0–GPIO/DR0SEC/SPI0_SSEL1/SPI0_SS I/O GPIO/SPORT0 Receive Data Secondary/SPI0 Slave Select Enable 1/SPI0 Slave A
Select Input
PG1–GPIO/DR0PRI/SPI1_SSEL1/WAKEN3 I/O GPIO/SPORT0 Receive Data Primary/SPI1 Slave Select Enable 1/Wake Enable 3 A
PG2–GPIO/RSCLK0/SPI0_SSEL5 I/O GPIO/SPORT0 Receive Serial Clock/SPI0 Slave Select Enable 5 A
PG3–GPIO/RFS0/PPI_FS3 I/O GPIO/SPORT0 Receive Frame Sync/PPI Frame Sync 3 A
PG4–GPIO(HWAIT)/DT0SEC/SPI0_SSEL6 I/O GPIO (HWAIT output for Slave Boot Modes)/SPORT0 Transmit Data A
Secondary/SPI0 Slave Select Enable 6
PG5–GPIO/DT0PRI/SPI1_SSEL6 I/O GPIO/SPORT0 Transmit Data Primary/SPI1 Slave Select Enable 6 A
PG6–GPIO/TSCLK0 I/O GPIO/SPORT0 Transmit Serial Clock A
PG7–GPIO/TFS0/SPI1_SSEL7 I/O GPIO/SPORT0 Transmit Frame Sync/SPI1 Slave Select Enable 7 A
PG8–GPIO/SPI1_SCK/PPI_D0 I/O GPIO/SPI1 Clock/PPI Data 0 A
PG9–GPIO/SPI1_MOSI/PPI_D1 I/O GPIO/SPI1 Master Out Slave In/PPI Data 1 A
Driver
Signal Name Type Function Type
PG10–GPIO/SPI1_MISO/PPI_D2 I/O GPIO/SPI1 Master In Slave Out/PPI Data 2 A
(This pin should always be pulled high through a 4.7 kΩ resistor if booting via
the SPI port.)
PG11–GPIO/SPI1_SSEL5/PPI_D3 I/O GPIO/SPI1 Slave Select Enable 5/PPI Data 3 A
PG12–GPIO/SPI1_SSEL2/PPI_D4/WAKEN2 I/O GPIO/SPI1 Slave Select Enable 2 Output/PPI Data 4/Wake Enable 2 A
PG13–GPIO/SPI1_SSEL1/SPI1_SS/PPI_D5 I/O GPIO/SPI1 Slave Select Enable 1 Output/PPI Data 5/SPI1 Slave Select Input A
PG14–GPIO/SPI1_SSEL4/PPI_D6/TACLK1 I/O GPIO/SPI1 Slave Select Enable 4/PPI Data 6/Timer 1 Auxiliary Clock Input A
PG15–GPIO/SPI1_SSEL6/PPI_D7/TACLK2 I/O GPIO/SPI1 Slave Select Enable 6/PPI Data 7/Timer 2 Auxiliary Clock Input A
TWI
SCL I/O TWI Serial Clock (This signal is an open-drain output and requires a pull-up B
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
SDA I/O TWI Serial Data (This signal is an open-drain output and requires a pull-up B
resistor. Consult version 2.1 of the I2C specification for the proper resistor
value.)
JTAG Port
TCK I JTAG CLK
TDO O JTAG Serial Data Out A
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST I JTAG Reset
(This lead should be pulled low if the JTAG port is not used.)
EMU O Emulation Output A
Clock
CLKIN I CLK/Crystal In
XTAL O Crystal Output
EXTCLK O External Clock Output pin/System Clock Output C
Mode Controls
RESET I Reset
NMI I Nonmaskable Interrupt
(This lead should be pulled high when not used.)
BMODE2–0 I Boot Mode Strap 2–0
PPI_CLK I PPI Clock Input
External Regulator Control
PG I Power Good indication
EXT_WAKE O Wake up Indication A
Power Supplies ALL SUPPLIES MUST BE POWERED
See Operating Conditions on Page 16.
VDDEXT P I/O Power Supply
VDDINT P Internal Power Supply
GND G Ground for All Supplies (Back Side of LFCSP Package.)
OPERATING CONDITIONS
Voltage (VDDINT)1
1
TJ (°C) 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
25 0.85 0.98 1.13 1.29 1.46 1.62 1.85 2.07
40 1.57 1.8 2.01 2.16 2.51 2.74 3.05 3.36
55 2.57 2.88 3.2 3.5 3.84 4.22 4.63 5.05
70 4.04 4.45 4.86 5.3 5.81 6.31 6.87 7.45
85 6.52 7.12 7.73 8.36 9.09 9.86 10.67 11.54
100 9.67 10.51 11.37 12.24 13.21 14.26 15.37 16.55
115 14.18 15.29 16.45 17.71 19.05 20.45 21.96 23.56
1
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 16.
Table 13. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1
a
ADSP-BF592
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B
Figure 6. Product Information on Package
tCKIN
CLKIN
tBUFDLAY
tCKINL tCKINH
tBUFDLAY
CLKBUF
tWRST
RESET
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
PPI_CLK
tPSUD
PPI_FS1/2
PPI_CLK
tPCLKW
tSFSPE tHFSPE
tPCLK
PPI_FS1/2
tSDRPE tHDRPE
PPI_DATA
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
PPI_CLK
tDFSPE tPCLKW
tHOFSPE tPCLK
PPI_FS1/2
tSDRPE tHDRPE
PPI_DATA
PPI_CLK
tDFSPE tPCLKW
tHOFSPE
PPI_FS1/2
tDDTPE tHDTPE
PPI_DATA
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 3 3 ns
tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 3 3 ns
tSDRE Receive Data Setup Before RSCLKx1 3 3 ns
tHDRE Receive Data Hold After RSCLKx1 3.5 3 ns
tSCLKEW TSCLKx/RSCLKx Width 4.5 4.5 ns
tSCLKE TSCLKx/RSCLKx Period 2 × tSCLK 2 × tSCLK ns
tSUDTE Start-Up Delay From SPORT Enable To First External TFSx2 4 × tTSCLKE 4 × tTSCLKE ns
tSUDRE Start-Up Delay From SPORT Enable To First External RFSx2 4 × tRSCLKE 4 × tRSCLKE ns
Switching Characteristics
tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx 10 10 ns
(Internally Generated TFSx/RFSx)3
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx 0 0 ns
(Internally Generated TFSx/RFSx)1
tDDTE Transmit Data Delay After TSCLKx1 11 10 ns
tHDTE Transmit Data Hold After TSCLKx1 0 0 ns
1
Referenced to sample edge.
2
Verified in design but untested.
3
Referenced to drive edge.
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 11.5 9.6 ns
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 –1.5 –1.5 ns
tSDRI Receive Data Setup Before RSCLKx1 11.5 11.3 ns
tHDRI Receive Data Hold After RSCLKx1 –1.5 –1.5 ns
Switching Characteristics
tSCLKIW TSCLKx/RSCLKx Width 7 8 ns
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx 4 3 ns
(Internally Generated TFSx/RFSx)2
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx –2 –2 ns
(Internally Generated TFSx/RFSx)1
tDDTI Transmit Data Delay After TSCLKx1 4 3 ns
tHDTI Transmit Data Hold After TSCLKx1 –1.8 –1.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
tDFSI tDFSE
tHOFSI tHOFSE
RFSx RFSx
(OUTPUT) (OUTPUT)
RFSx RFSx
(INPUT) (INPUT)
DRx DRx
tD FSI tDFSE
tHOFSI tHOFSE
TFSx TFSx
(OUTPUT) (OUTPUT)
TFSx TFSx
(INPUT) (INPUT)
tDDTI tDDTE
tHDTI tHDTE
DTx DTx
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 15. Serial Port Start Up with External Clock and Frame Sync
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
tDTENE Data Enable Delay from External TSCLKx1 0 0 ns
tDDTTE Data Disable Delay from External TSCLKx1 tSCLK + 1 tSCLK + 1 ns
tDTENI Data Enable Delay from Internal TSCLKx1 –2 –2 ns
tDDTTI Data Disable Delay from Internal TSCLKx1 tSCLK + 1 tSCLK + 1 ns
1
Referenced to drive edge.
TSCLKx
tDTENE/I tDDTTE/I
DTx
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx 12 10 ns
or External RFSx in multi-channel mode with MFD = 01, 2
tDTENLFSE Data Enable from External RFSx in multi-channel mode with 0 0 ns
MFD = 01, 2
1
When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFSE apply.
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
DTx 1ST BIT
TSCLKx
TFSx
tDDTLFSE
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tSDRI Receive Data Setup Before TSCLKx 11.3 8.7 ns
tHDRI Receive Hold After TSCLKx 0 0 ns
Switching Characteristics
tDDTI Transmit Data Delay After TSCLKx 3 3 ns
tHDTI Transmit Data Hold After TSCLKx –1.8 –1.8 ns
tDFTSCLKCNV First TSCLKx edge delay after TFSx/TMR1 Low 0.5 × tTSCLK – 3 0.5 × tTSCLK – 3 ns
tDCNVLTSCLK TFSx/TMR1 High Delay After Last TSCLKx Edge tTSCLK – 3 tTSCLK – 3 ns
TSCLKx
(OUT)
tSDRI tHDRI
DRx
TFS/TMR
(OUT)
tDFTSCLKCNV tDCNVLTSCLK
TSCLKx
(OUT)
tDFTSCLKCNV tDCNVLTSCLK
TSCLKx
(OUT) tDDTI
tHDTI
DTx
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 11.6 9.6 ns
tHSPIDM SCK Sampling Edge to Data Input Invalid –1.5 –1.5 ns
Switching Characteristics
tSDSCIM SPI_SELx low to First SCK Edge 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPICHM Serial Clock High Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPICLM Serial Clock Low Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPICLK Serial Clock Period 4 × tSCLK – 1.5 4 × tSCLK – 1.5 ns
tHDSM Last SCK Edge to SPI_SELx High 2 × tSCLK – 2 2 × tSCLK – 1.5 ns
tSPITDM Sequential Transfer Delay 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay) 0 6 0 6 ns
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1 –1 ns
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
tHDSPIDM tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM tHSPIDM
CPHA = 0
SPIxMISO
(INPUT)
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tSPICHS Serial Clock High Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPICLS Serial Clock Low Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPICLK Serial Clock Period 4 × tSCLK 4 × tSCLK ns
tHDS Last SCK Edge to SPI_SS Not Asserted 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSPITDS Sequential Transfer Delay 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSDSCI SPI_SS Assertion to First SCK Edge 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 ns
tHSPID SCK Sampling Edge to Data Input Invalid 2 1.6 ns
Switching Characteristics
tDSOE SPI_SS Assertion to Data Out Active 0 12 0 10.3 ns
tDSDHI SPI_SS Deassertion to Data High Impedance 0 11 0 9 ns
tDDSPID SCK Edge to Data Out Valid (Data Out Delay) 10 10 ns
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0 0 ns
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
tDSOE tDDSPID
tHDSPID tDDSPID tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID tHSPID
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
tHSPID
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tWL Timer Pulse Width Input Low 1 × tSCLK 1 × tSCLK ns
(Measured In SCLK Cycles)1
tWH Timer Pulse Width Input High 1 × tSCLK 1 × tSCLK ns
(Measured In SCLK Cycles)1
tTIS Timer Input Setup Time Before CLKOUT Low2 10 8 ns
tTIH Timer Input Hold Time After CLKOUT Low2 –2 –2 ns
Switching Characteristics
tHTO Timer Pulse Width Output 1 × tSCLK – 2 (232 – 1) × tSCLK tSCLK – 1.5 (232 – 1) × tSCLK ns
(Measured In SCLK Cycles)
tTOD Timer Output Update Delay After CLKOUT High 6 6 ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
TMRx INPUT
tWH,tWL
PPI_CLK
tTODP
TMRx OUTPUT
VDDEXT VDDEXT
1.8V Nominal 2.5 V/3.3V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
tTCK TCK Period 20 20 ns
tSTAP TDI, TMS Setup Before TCK High 4 4 ns
tHTAP TDI, TMS Hold After TCK High 4 4 ns
tSSYS System Inputs Setup Before TCK High1 4 5 ns
tHSYS System Inputs Hold After TCK High1 5 5 ns
tTRSTW TRST Pulse Width2 (measured in TCK cycles) 4 4 TCK
Switching Characteristics
tDTDO TDO Delay from TCK Low 10 10 ns
tDSYS System Outputs Delay After TCK Low3 13 13 ns
1
System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.
2
50 MHz maximum.
3
System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
tTCK
TCK
tSTAP tHTAP
TMS
TDI
tDTDO
TDO
tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
40
VOH
20 –30
0
–40
–20 0 0.5 1.0 1.5
–40
SOURCE VOLTAGE (V)
–60
VOL
–80 Figure 27. Driver Type A Current (1.8V VDDEXT)
–100
120
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VDDEXT = 3.6V @ – 40°C
100
SOURCE VOLTAGE (V) VDDEXT = 3.3V @ 25°C
80
VDDEXT = 3.0V @ 105°C
Figure 25. Driver Type A Current (3.3V VDDEXT) 60
SOURCE CURRENT (mA)
40
20
80
VDDEXT = 2.75V @ – 40°C 0
60 VDDEXT = 2.5V @ 25°C –20
VDDEXT = 2.25V @ 105°C
–40
40
SOURCE CURRENT (mA)
–60
VOL
20
–80
VOH
–100
0
–120
–20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SOURCE VOLTAGE (V)
–40
VOL Figure 28. Driver Type B Current (3.3V VDDEXT)
–60
–80 80
0 0.5 1.0 1.5 2.0 2.5 VDDEXT = 2.75V @ – 40°C
60 VDDEXT = 2.5V @ 25°C
SOURCE VOLTAGE (V)
VDDEXT = 2.25V @ 105°C
Figure 26. Drive Type A Current (2.5V VDDEXT) 40
SOURCE CURRENT (mA)
20
–20
–40
VOL
–60
–80
0 0.5 1.0 1.5 2.0 2.5
20 20
VOH
10
0
0
–10
–20
–20 VOL
VOL
–30 –40
–40
–60
–50 0 0.5 1.0 1.5
0 0.5 1.0 1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
TEST CONDITIONS
150
VDDEXT = 3.6V @ – 40°C All timing parameters appearing in this data sheet were mea-
120 VDDEXT = 3.3V @ 25°C sured under the conditions described in this section. Figure 34
90 VDDEXT = 3.0V @ 105°C shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point VMEAS is VDDEXT/2
SOURCE CURRENT (mA)
60
30
VOH for VDDEXT (nominal) = 1.8 V/2.5 V/3.3 V.
0
– 30 INPUT
OR VMEAS VMEAS
– 60 OUTPUT
– 90 VOL
25
Figure 35.
VOH
0
– 25 REFERENCE
SIGNAL
– 50
VOL tDIS_MEASURED tENA_MEASURED
– 75
tDIS tENA
– 100 VOH VOH(MEASURED)
0 0.5 1.0 1.5 2.0 2.5 (MEASURED) VOH (MEASURED) ⴚ ⌬V VTRIP(HIGH)
SOURCE VOLTAGE (V)
VOL (MEASURED) + ⌬V VTRIP(LOW)
VOL VOL (MEASURED)
Figure 32. Driver Type C Current (2.5V VDDEXT) (MEASURED)
tDECAY tTRIP
The time for the voltage on the bus to decay by ΔV is dependent The graphs of Figure 37 through Figure 42 show how output
on the capacitive load CL and the load current IL. This decay rise time varies with capacitance. The delay and hold specifica-
time can be approximated by the equation: tions given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
t DECAY = C L V I L ranges shown.
The time tDECAY is calculated with test loads CL and IL, and with
20
ΔV equal to 0.25 V for VDDEXT (nominal) = 2.5 V/3.3 V and
18
0.15 V for VDDEXT (nominal) = 1.8V. tFALL
16
The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays ΔV from the 14
tRISE
RISE AND FALL TIME (ns)
10
Example System Hold Time Calculation
8
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV 6
16 8
tFALL tFALL
14 7
12 6
tRISE
10 5
8 4
6 3
4 2
Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Figure 41. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT) Load Capacitance (2.5V VDDEXT)
16 7
14
tFALL 6
tFALL
12
RISE AND FALL TIME (ns)
tRISE 5
RISE AND FALL TIME (ns)
10 tRISE
4
8
3
6
4 2
Figure 39. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Figure 42. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT) Load Capacitance (3.3V VDDEXT)
12
tFALL
10
RISE AND FALL TIME (ns)
8
tRISE
2
tFALL = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
0
0 50 100 150 200 250
Figure 40. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
T J = T CASE + JT P D
where:
TJ = junction temperature (°C)
TCASE = case temperature (°C) measured by customer at top cen-
ter of package.
JT = from Table 32
PD = power dissipation (see Total Power Dissipation on Page 19
for the method to calculate PD)
T J = T A + JA P D
where:
TA = ambient temperature (°C)
Values of JC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Values of JB are provided for package comparison and printed
circuit board design considerations.
In Table 32, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Signal Lead No. Signal Lead No. Signal Lead No. Signal Lead No.
BMODE0 29 PF7 7 PG6 38 TDO 23
BMODE1 28 PF8 10 PG7 39 TMS 21
BMODE2 27 PF9 11 PG8 42 TRST 20
EXTCLK/SCLK 57 PF10 12 PG9 43 VDDEXT 3
CLKIN 61 PF11 13 PG10 44 VDDEXT 14
EMU 19 PF12 15 PG11 45 VDDEXT 25
EXT_WAKE 51 PF13 16 PG12 47 VDDEXT 35
GND 30 PF14 17 PG13 48 VDDEXT 46
NMI 54 PF15 18 PG14 49 VDDEXT 58
PF0 63 PG 52 PG15 50 VDDINT 8
PF1 64 PG0 31 PPI_CLK 56 VDDINT 9
PF2 1 PG1 32 RESET 53 VDDINT 26
PF3 2 PG2 33 SCL 60 VDDINT 40
PF4 4 PG3 34 SDA 59 VDDINT 41
PF5 5 PG4 36 TCK 24 VDDINT 55
PF6 6 PG5 37 TDI 22 XTAL 62
GND* 65
* Lead no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
Lead No. Signal Lead No. Signal Lead No. Signal Lead No. Signal
1 PF2 17 PF14 33 PG2 49 PG14
2 PF3 18 PF15 34 PG3 50 PG15
3 VDDEXT 19 EMU 35 VDDEXT 51 EXT_WAKE
4 PF4 20 TRST 36 PG4 52 PG
5 PF5 21 TMS 37 PG5 53 RESET
6 PF6 22 TDI 38 PG6 54 NMI
7 PF7 23 TDO 39 PG7 55 VDDINT
8 VDDINT 24 TCK 40 VDDINT 56 PPI_CLK
9 VDDINT 25 VDDEXT 41 VDDINT 57 EXTCLK/SCLK
10 PF8 26 VDDINT 42 PG8 58 VDDEXT
11 PF9 27 BMODE2 43 PG9 59 SDA
12 PF10 28 BMODE1 44 PG10 60 SCL
13 PF11 29 BMODE0 45 PG11 61 CLKIN
14 VDDEXT 30 GND 46 VDDEXT 62 XTAL
15 PF12 31 PG0 47 PG12 63 PF0
16 PF13 32 PG1 48 PG13 64 PF1
65 GND*
* Pin no. 65 is the GND supply (see Figure 43 and Figure 44) for the processor (6.2 mm × 6.2 mm); this pad must connect to GND.
PIN 64 PIN 49
PIN 1 PIN 48
PIN 1 INDICATOR
ADSP-BF592
64-LEAD LFCSP
TOP VIEW
PIN 16 PIN 33
PIN 17 PIN 32
PIN 49 PIN 64
PIN 48 PIN 1
ADSP-BF592
GND PAD
64-LEAD PIN 1 INDICATOR
LFCSP (PIN 65)
BOTTOM VIEW
PIN 33 PIN 16
PIN 32 PIN 17
PIN 1
INDICATOR
0.50 6.35
TOP VIEW 8.75 BSC EXPOSED PAD
BSC SQ 6.20 SQ
(BOTTOM VIEW)
6.05
0.50
0.40 33 16
32 17
0.30
0.25 MIN
7.50
REF
12° MAX 0.80 MAX
1.00
0.65 TYP FOR PROPER CONNECTION OF
0.85
0.05 MAX THE EXPOSED PAD, REFER TO
0.80 THE LEAD ASSIGNMENT AND
0.02 NOM
SIGNAL DESCRIPTIONS
SEATING 0.30 SECTIONS OF THIS DATA SHEET.
PLANE 0.20 REF
0.23
0.18
ORDERING GUIDE
Authorized Distributor