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Applications of Silicon-Germanium Heterostructure Devices
Applications of Silicon-Germanium Heterostructure Devices
Applications of Silicon-Germanium Heterostructure Devices
Heterostructure Devices
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Series in Optics and Optoelectronics
Series Editors:
R G W Brown, University of Nottingham, UK
E R Pike, Kings College, London, UK
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Series in Optics and Optoelectronics
Applications of Silicon–Germanium
Heterostructure Devices
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c IOP Publishing Ltd 2001
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In memory of
Dr Suva Maiti
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CONTENTS
PREFACE xiii
1 INTRODUCTION 1
1.1 Evolution of bipolar technology 5
1.2 Heterojunction bipolar transistors 9
1.3 Development of SiGe/SiGeC HBT technology 13
1.4 Heterostructure field-effect transistors 16
1.5 Vertical heterostructure FETs 18
1.6 Optoelectronic devices 20
1.7 Applications of SiGe HBTs 21
1.8 Summary 25
Bibliography 25
2 FILM GROWTH AND MATERIAL PARAMETERS 32
2.1 Strained layer epitaxy 33
2.2 Deposition techniques 42
2.2.1 Wafer cleaning 43
2.2.2 Molecular beam epitaxy 44
2.2.3 UHVCVD 46
2.2.4 LRPCVD and RTCVD 47
2.2.5 Very low pressure CVD 48
2.2.6 Remote plasma CVD 48
2.2.7 Atmospheric pressure CVD 48
2.2.8 Solid phase epitaxy 49
2.2.9 SiGeC film growth 49
2.2.10 Strained-Si film growth 50
2.3 Thermal stability of alloy layers 51
2.4 Bandgap and band discontinuity 52
2.4.1 Si/SiGe 54
2.4.2 Si/SiGeC 56
2.4.3 Strained-Si 58
2.5 Mobility 59
2.5.1 Si/SiGe 59
2.5.2 Si/SiGeC 59
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viii Contents
2.5.3 Strained-Si 63
2.6 Summary 64
Bibliography 65
3 PRINCIPLE OF SIGE HBTS 73
3.1 Energy band 75
3.2 Terminal currents in a SiGe HBT 77
3.3 Transit time 83
3.4 Early voltage 85
3.5 Heterojunction barrier effects 90
3.5.1 Effect of undoped spacer layers 92
3.6 High level injection 94
3.7 High-frequency figures-of-merit 96
3.7.1 Unity gain cut-off frequency, fT 96
3.7.2 Maximum oscillation frequency, fmax 98
3.8 Breakdown voltage, BVceo 99
3.9 Summary 100
Bibliography 100
4 DESIGN OF SIGE HBTS 104
4.1 Device modelling 106
4.2 Numerical methods 108
4.3 Material parameters for simulation 110
4.3.1 SiGe: hole mobility 112
4.3.2 SiGe: electron mobility 113
4.3.3 SiGe: bandgap 115
4.3.4 Recombination and carrier lifetime 117
4.4 History of simulation of SiGe HBTs 118
4.5 Experimental SiGe HBTs 119
4.6 Device design issues 121
4.6.1 Base design 122
4.6.2 Emitter design 126
4.6.3 Collector design 129
4.7 Small-signal ac analysis 134
4.7.1 Small-signal equivalent circuit 134
4.7.2 Evaluation of transit time 139
4.7.3 ECL gate delay 141
4.8 Summary 145
Bibliography 145
5 SIMULATION OF SIGE HBTS 152
5.1 Epitaxial-base SiGe HBT (1995) 155
5.2 Double polysilicon self-aligned SiGe HBT (1998) 159
5.3 Energy balance simulation 162
5.4 SiGe HBTs on SOI substrates 166
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Contents ix
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x Contents
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Contents xi
xiii
xiv Preface
C K Maiti
G A Armstrong
26 October 2000
Chapter 1
INTRODUCTION
Silicon is by far the most widely used semiconductor material and is likely
to remain so for the foreseeable future, although from the perspective of an
integrated circuit (IC) designer silicon is hardly a perfect semiconductor.
Compared with other semiconductors, it is relatively poor in terms of
how fast the charge carriers can move through the crystal lattice, which
limits the speed at which silicon devices can operate. ‘Why is silicon still
dominant?’ The answer to this question is economics. Silicon is abundant
in nature, non-toxic, strong and an excellent conductor of heat. It can be
grown to a very high purity and very large diameter (with 12 inch now
being contemplated) wafers, and it readily forms a stable insulating film
(SiO2 or Si3 N4 ) of high quality. Properties of this kind make silicon a
natural choice for IC manufacturing and, in fact, over the past 40 years or
so, the performance of silicon ICs and the density of devices per unit area
have soared, while the cost per function has plunged (see figure 1.1). ICs
are more difficult and more expensive to fabricate from III–V compound
semiconductors such as GaAs/AlGaAs or InP. High-quality oxides are
scarce in the III–V semiconductors, impeding device integration. High-
purity, large diameter crystals are difficult to grow and yield is poor because
of more defect density.
For decades, miniaturization has been the key to faster performance
of ICs. As the size of a transistor, whether field effect or bipolar,
influences its speed of operation, designers have focused on creating
ever smaller transistors. The strategy for enhancing the function of an
electronic device by reducing its critical dimensions is commonly referred
to as scaling. Although scaling has led to improvement in the speed
and flexibility of silicon-based electronics, the trend cannot continue
indefinitely. Researchers are actively pursuing alternative approaches to
boost the speed of electronic devices by introducing ‘bandgap engineering’.
In silicon technology, two materials may be used in bandgap-engineered
transistors: silicon carbide (SiC) and silicon–germanium (SiGe). Silicon
1
2 Introduction
Figure 1.1. Moore’s law: the gate length and cost of production lines as a
function of time. Source: National Technology Roadmap for Semiconductors,
Semiconductor Industry Association, San Jose, USA, 1997. (After Paul D J 1999
Adv. Mater. 11 191–204.)
Figure 1.3. Electron devices for backbone network. (After Nakamura M 1998
IEEE ISSCC Tech. Dig. pp 16–21).
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Evolution of bipolar technology 5
The design and study of a new semiconductor device structure hold promise
at both the device level, where the transistor’s electrical behaviour may lead
to novel effects, and the circuit level, where the device characteristics may
be exploited to enhance functional performance. Since the revolutionary
invention of the point-contact transistor at Bell Laboratories in 1947,
numerous new transistor structures have been proposed and demonstrated.
Of the many transistors demonstrated in the last fifty years, however, the
IC market is dominated by just two devices: the BJT with a market share
of about 20%, and the metal–oxide semiconductor field-effect transistor
(MOSFET) with 75%. BJTs and MOSFETs are the dominant high-
performance devices in silicon technology. In this section, we shall present
an overview of the high-performance transistors in silicon.
6 Introduction
Figure 1.5. (a)–(g) The evolutionary continuum between bipolar and field-effect
transistors. A conventional FET is shrunk in lateral dimension (a), then
converting to a stacking configuration (b). Rotating the structure by 90◦ produces
(c). Reducing the vertical dimensions from (c) to (e) yields a permeable base
transistor. Replacing the grid with a sheet of metal produces a metal-base
transistor (f ). Finally, replacing the metal base with a p-doped layer results in
the conventional bipolar transistor (g). (After Stoneham E B 1982 Microwaves
55–60.)
Evolution of bipolar technology 7
entering the base from the emitter see a large band discontinuity. This
accelerates them to a large momentum in the vertical direction. The
base being very narrow, electrons remain hot throughout the base region,
resulting in a reduction in the base transit time. In addition, the use of a
metal for the base reduces the base resistance. In principle, the metal-base
transistor should have a significant performance advantage over the BJT.
Unfortunately, no metal-base transistor has yet achieved even unity current
gain.
Nishizawa [6] proposed a high-speed switching device known as the
bipolar static induction transistor (BSIT) which may be thought of as
a bipolar transistor with the intrinsic base region missing. Control of
collector current in this device is only possible because the extrinsic p+
base regions are physically close together and current is controlled by
forward biasing the base–emitter junction. A high transconductance is
obtained compared to FETs of comparable dimensions and also leads
to faster switching times. Indeed, several types of circuits have been
successfully fabricated with the BSIT device [6, 7]. However, due to its
extreme sensitivity to process variations, the BSIT could hardly be useful
for high levels of circuit integration.
Another interesting structure, a tunnel transistor, which is identical
to that of a p-channel MOSFET with a very thin (20 Å) gate oxide layer
has also been proposed [8]. The thin oxide layer allows substantial electron
tunnelling currents in the vertical direction. The gate can thus act as
an emitter, the substrate as a collector and the source/drain regions as
extrinsic base regions. The intrinsic base is replaced with a mobile hole
layer or ‘inversion channel’ whose charge density modulates the electric
field strength across the oxide, and thus controls the electron tunnelling
currents in the vertical direction. This hole charge density is controlled by
the extrinsic base potential. Using this concept, Simmons and Taylor [8]
have theoretically and experimentally studied tunnel transistors built in
the Alx Ga1−x As/GaAs material system. GaAs was used as the emitter
and the collector semiconductors and AlAs was used as a wide bandgap
semiconductor replacing the insulator. However, limited current density
and transconductance resulted in a much slower device.
Despite much research on alternative technologies, silicon integrated
circuits dominate mainstream electronics. Impressive improvements in
high-speed Si bipolar technology have been made in the last few years.
Self-aligned bipolar transistors having polySi base electrodes have been
effective in reducing base resistance through their small resistance in the
base electrode and short length between the emitter and the base.
Si homojunction transistors with a maximum oscillation frequency,
fmax above 80 GHz have been obtained using low base resistance self-
aligned metal/IDP (SMI) technology. The base resistance is reduced to a
half compared to conventional polySi technology and a 12.2 ps gate delay
Heterojunction bipolar transistors 9
Figure 1.6. Si and SiGe device performance over the past several years. In terms
of device speed, SiGe has maintained about 50% advantage over Si devices.
1.9 ps, and an AlInAs/InGaAs HBT has given a unity current gain cut-off
frequency exceeding 200 GHz.
Despite the advances in HBT fabrication techniques, mostly using
group III–V and II–VI materials, silicon devices continue to dominate
due to the low cost and ease of manufacturability. Silicon readily forms
a high-quality oxide which can be used to mask implants, diffusion
and metallization. The isolation technique, chemical vapour deposition,
diffusion, ion implantation, contact technology and etching methods
are highly developed in Si technology. GaAs and the other III–V
semiconductors lack this important property.
It is well known that GaAs or InP technologies exhibit superior fT
and fmax , compared to a SiGe device, for a specified geometry. An
excellent comparison of the technologies has been presented by Konig and
Gruhle [31]. Plots from [31] of both fT and fmax as a function of base
width are shown in figures 1.7 and 1.8. A further performance comparison
of a III–V material HBT with a SiGe HBT has been presented by Larson
[32]. Clearly, if maximum bandwidth or speed is the only criterion, then
Table 1.1. Technology comparison in the frequency range of 1–10 GHz. (After
Temic Semiconductors, Germany.)
and their associated doping profiles. A SiGe HBT offers additional design
flexibility in that the bandgap of the base may be tailored by grading
the Ge concentration. Reducing the width of the base region reduces the
base transit time with associated improvement in cut-off frequency, but
inevitably increases overall base resistance with possible reduction in fmax .
For effective design, it is thus essential to use an appropriate simulation
tool. Many of the significant issues have been published in a number of
reports dealing with aspects of both numerical and analytical modelling of
SiGe HBTs [34–41]. In chapters 4 and 5 of this book, we discuss the design
considerations for SiGe HBTs in terms of the following:
• optimization of base, emitter and collector doping profiles;
• effect of Ge profile on the transit times;
• prediction of cut-off frequencies, fT and fmax ; and
• design issues at low temperature.
Since the first report of SiGe HBTs in 1987, there have been numerous
demonstrations (see figure 1.6) of its impressive potential. For example,
an early theoretical study [42] predicted a unity gain cut-off frequency in
excess of 300 GHz. Since then there have been a number of significant
milestones in the measured performance of SiGe HBTs, including fT in
excess of 130 GHz [43], fmax values of 160 GHz [44], ECL and current
model logic (CML) gate delay of less than 10 ps [45–47]. Recently, an
Si/Si0.65 Ge0.35 abrupt SiGe HBT with an fT of 213 GHz and fmax of
115 GHz at 77 K has been reported [48]. Summarized in table 1.2 are some
of the reported results obtained with high-performance SiGe HBTs, which
relate to state-of-the-art performance in commercially available devices.
The addition of substitutional carbon to silicon–germanium thin films
Table 1.2. Some of the commercially available (as of 1998) device results from
various SiGe research groups.
Group IBM IBM
parameter (1996) (BiCMOS) NEC HP Daimler–Benz
fT /fmax 48/60 48/60 60/50 40/– 59/90
(GHz) 113/65
Rbi /Rb 7–9 k 7–9 k – 40k 380–780
(Ohms/square)
Wb 700–1000 700–1000 – 500–600 150
(Å) w/spacers
Ge Profile 0–15% 0–15% 15% 16% 30%
various various graded graded uniform
shapes shapes
Development of SiGe/SiGeC HBT technology 15
Figure 1.9. Cut-off and maximum oscillation frequencies versus collector current
for SiGeC HBTs. (After Osten H J et al 1999 IEEE BCTM Proc. pp 109–16.)
16 Introduction
Vertical MOS structures are being explored for increasing the integration
density and for incorporation of quantum effects into MOS devices.
Vertical MOS heterostructures are expected to solve the scaling issues
of lithography, doping confinement and DIBL. Vertical devices will have
Vertical heterostructure FETs 19
small contact areas and will facilitate interconnects and minimize the via
contacts leading to a minimization of the area per function. Present
projections, based on the operation of a 20 nm channel length vertical
device at room temperature, result in an on-current of 20 000 µA µm−1 ,
an off-state current less than 1 pA µm−2 , a peak transconductance of more
than 3500 mS mm−1 , a VT of less than 0.3 V at VDD of 1 V and an intrinsic
carrier transit time of less than 1 ps.
In establishing its potential advantages and assessing its performance
with respect to conventional transistors, a technology which provides
denser and faster structures, and uses the standard processing technology
and production equipment, research has been initiated. In fact, the
SiGe technology has been implemented in the Si process lines by several
manufacturers and is expected to facilitate a low-cost transfer of the new
vertical SiGe heterostructure MOS into production. In addition, a CMOS
possibility also exists if the heterojunction is made by a SiGe/Si(p-MOS)
or SiGe/Ge(n-MOS) combination. All these materials are compatible with
Si technology and allow for an easy integration into production.
A vertical heterostructure MOS (VHMOS) has the following
advantages.
• The device is not a lateral but a vertical one; source/channel and
drain regions are grown epitaxially. As such the device channel
length is defined by the channel layer epitaxial growth and thus fully
decoupled from lithographic limitations. Therefore, much shorter
channel lengths (down to 20 nm) become feasible.
• At the source side of the device, a heterojunction is used which keeps
the barrier for conduction in the off-state constant and not affected
by the drain voltage. In order to have conduction in the on-state,
the source side closest to the channel region is intrinsic. This allows
for Fermi-level modulation by the action of the overlapping gate and
thus conduction. The DIBL effect no longer exists [68].
The experimental evidence of the enhancement of out-of-plane hole
mobility in SiGe using a vertical p-MOSFET structure, fabricated by
high-dose Ge implantation followed by solid phase recrystallization, has
been reported [69]. The structure combines the merits of a very short
channel device without a critical lithography process and a higher hole
mobility in the channel region. Superior performance with respect to
a homojunction structure has been demonstrated, especially for deep
submicron dimensions. Although the p-MOS devices have been reported
so far, similar work is being performed on n-MOS devices with strained-
Si/SiGe in the source/channel and drain regions. However, in this case, a
virtual substrate consisting of a relaxed-SiGe layer is needed [68, 70].
Up to this point, we have described the major application areas where
SiGe technology has become established. However, there are a number of
20 Introduction
other application areas in which SiGe devices may have a role to play.
Bipolar inversion channel field-effect transistors (BICFETs) have been
studied extensively theoretically [71] as well as experimentally in SiGe
materials [72–74]. Taft and Plummer [71] implemented the concept in
the SiGe material system in order to take advantage of the established
Si technology and showed that the SiGe BICFET could potentially fulfil
both the ends: high performance (due to its intrinsic speed advantage) and
manufacturability (due to the lower costs of silicon processing). Kasper
and Reitemann [75] have explored the idea of a common device structure
for different functions by combining a SiGe HBT and a charge injection
transistor (CHINT) on Si–SiGe–Si–SiGe [76]. It is a hot electron device;
VDS accelerates the carriers, which cross the SiGe–Si barrier to be collected
at the real space transfer output as stated.
Figure 1.10. The integrated silicon chip of the future: CMOS, HBT/bipolar,
SiGe quantum devices, SiGe detectors, SiGe waveguides and light emitter all on
a chip. (After Paul D J 1998 Thin Solid Films 321 172–80.)
Applications of SiGe HBTs 21
Table 1.4. Summary of several circuits reported in the literature using SiGe
HBT technology.
Table 1.5. List of devices available in the SiGe BiCMOS technology. The main
characteristics are provided for each device which are available to the designers
to make a full custom design. (After Brenner et al 1999 IBM MicroNews 5 1–4.)
Device Parameter
1 npn SiGe HBT fT = 47 GHz
fmax = 65 GHz
2 npn Higher breakdown SiGe HBT
fT = 27 GHz, fmax = 55 GHz
3 n-FET ID,sat = 485µA/µm
Leff min=0.39 µm
4 p-FET ID,sat = 213µA/µm
Leff min=0.39 µm
5 Gated lateral pnp β = 107, VA = 67 V
6 Spiral inductor L = 10 nH, Q = 6 at 1 GHz
7 Varactor 1.4 fF µm−2
8 Schottky barrier diode Vf = 0.31 V @ 100 µA for 5 × 5 µm
9 Substrate contact 330 Ωs (p+ subs.) for 2 × 10 µm
10 Polysilicon resistor (RP) 220 Ω/square
11 Polysilicon resistor (XN) 340 Ω/square
12 Reach-through implant resistor (RN) 23.5 Ω/square
13 n+ -subcollector resistor (RS) 8 Ω/square
14 Ion implanted resistor (RI) 1750 Ω/square
15 Metal–insulator–metal capacitor 0.7 fF µm−2
16 Decoupling capacitor 1.5 fF µm−2
17 p–i–n diode 6 Ω for a 2 × 10 µm
18 ESD protective device 2000 V HBM
Summary 25
1.8. SUMMARY
BIBLIOGRAPHY
[1] Walker R C, Hsieh K-C, Knotts T A and Yen C-S 1998 A 10 Gb/s Si-bipolar
TX/RX chipset for computer data transmission IEEE ISSCC Tech. Dig.
pp 302–3
[2] Stoneham E B 1982 The search for the fastest three-terminal device
Microwaves 55–60
[3] Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester:
Wiley)
[4] Patton G L, Bravman J C and Plummer J D 1986 Physics, technology
26 Introduction
Dig. pp 509–12
[60] Welser J, Hoyt J L, Takagi S and Gibbons J F 1994 Strain dependence of the
performance enhancement in strained-Si n-MOSFETs IEEE IEDM Tech.
Dig. pp 373–6
[61] Nayak D K, Goto K, Yutani A, Murota J and Shiraki Y 1996 High-mobility
strained-Si PMOSFETs IEEE Trans. Electron Devices 43 1709–15
[62] Maiti C K, Bera L K, Dey S S, Nayak D K and Chakrabarti N B 1997
Hole mobility enhancement in strained-Si p-MOSFETs under high vertical
fields Solid-State Electron. 41 1863–9
[63] Hartmann R, Gennser U, Sigg H, Grutzmacher D and Dehlinger G 1999
Si/SiGeC heterostructures: a path towards high mobility channels
Future Trends in Microelectronics—the Road Ahead (New York: Wiley
Interscience) pp 133–42
[64] Quinones E J, John S, Ray S K and Banerjee S K 2000 Design, fabrication
and analysis of SiGeC heterojunction PMOSFETs IEEE Trans. Electron
Devices 47 1715–25
[65] Alieu J, Skotnicki T, Bouillon P, Regolini J L, Soufi A, Guillot G and
Bremond G 1999 Potential of SiGe-channel MOSFETs for a submicron
CMOS technology Future Trends in Microelectronics—the Road Ahead
(New York: Wiley Interscience) pp 143–54
[66] Whall T E and Parker E H C 2000 SiGe heterostructures for CMOS
technology Thin Solid Films 376 250–9
[67] Paul D J 1999 Silicon–germanium strained layer materials in micro-
electronics Adv. Mater. 11 191–204
[68] Collaert N and De Meyer K 1999 Modelling the short-channel threshold
voltage of a novel vertical heterojunction pMOSFET IEEE Trans.
Electron Devices 46 933–9
[69] Liu K C, Ray S K, Oswal S K and Banerjee S K 1998 A deep submicron
Si1−x Gex /Si vertical PMOSFET fabricated by Ge ion implantation IEEE
Electron Device Lett. 19 13–15
[70] De Meyer K, Caymax M, Collaert N, Loo R and Verheyen P 1998 The
vertical heterojunction MOSFET Thin Solid Films 336 299–305
[71] Taft R C and Plummer J D 1992 Gex Si1−x /silicon inversion-base transistors:
theory of operation IEEE Trans. Electron Devices 39 2108–18
[72] Taft R C, Plummer J D and Iyer S S 1989 Demonstration of a p-channel
BICFET in the Gex Si1−x /Si system IEEE Electron Device Lett. 10 14–16
[73] Taft R C, Plummer J D and Iyer S S 1992 Gex Si1−x /silicon inversion-base
transistors: experimental demonstration IEEE Trans. Electron Devices
39 2119–26
[74] Mierzwinski M E, Plummer J D, Croke E T, Iyer S S and Harrell M J 1992
AC characterization and modelling of the Gex Si1−x /Si BICFET IEEE
IEDM Tech. Dig. pp 773–6
[75] Kasper E and Reitemann G 1999 Can silicon-based heterodevices compete
with CMOS for system solutions? Future Trends in Microelectronics—the
Road Ahead (New York: Wiley Interscience) pp 125–32
[76] Mastrapasqua M, King C A, Smith P R and Pinto M R 1996 Functional
devices based on real space transfer in Si/SiGe structures IEEE Trans.
Electron Devices 43 1671–7
30 Introduction
32
Strained layer epitaxy 33
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Strained layer epitaxy 35
Figure 2.2. Lattice constant for an Si1−x Gex alloy as a function of x. Vegard’s
law is a linear interpolation between aSi and aGe .
constants of Si1−x Gex alloys are larger than that of Si, pseudomorphic
Si1−x Gex layers grown on silicon have biaxial in-plane compression of the
alloy and an extension normal to the interface. If layers are grown on a
germanium substrate the reverse is the case. In both cases the layers suffer
a tetragonal distortion.
In fully relaxed Si1−x Gex on silicon, the lattice constant returns
to the bulk value. The lattice constants of bulk-Si1−x Gex alloys have
been measured and the results obey Vegard’s law to a very good
approximation. Assuming Vegard’s law applies, the bulk-Si1−x Gex lattice
constant (aSi1−x Gex ) is a function of the silicon and germanium lattice
constants (aSi and aGe ) and the mole fraction of germanium, x in
equation (2.1). The lattice constant of Si1−x Gex alloys varies linearly, as
shown in figure 2.2 obeying Vegard’s rule:
Due to the relatively large lattice mismatch between SiGe and silicon,
commensurate (defect-free) SiGe alloy films cannot be grown on silicon
substrates without introducing large amounts of strain.
As the thickness of the SiGe layer increases, so does the integrated
strain energy and at some point this configuration will reach a thickness,
which is known as the ‘critical layer thickness’, beyond which the total
energy becomes larger and results in ‘misfit dislocations’ or periodic arrays
of incompletely bonded atom rows. Misfit or threading dislocations appear
at the interface in both the relaxed and partially relaxed cases. Threading
dislocations affect the heterojunction by acting as a pathway for enhanced
36 Film growth and material parameters
Figure 2.3. Critical layer thickness versus Ge content showing stable, metastable
and relaxed ranges of Si1−x Gex layers on Si. (After Schuppen A et al 1995
J. Mater. Sci., Mater. Electron. 6 298–305.)
strained, even though the layers are above the Matthews–Blakeslee critical
thickness. However, metastable layers relax with subsequent annealing.
People and Bean sought to reconcile these differences by including
the kinetics of relaxation in their calculation [10]. Their critical thickness
prediction fits their data, but their theory has not been widely accepted
by other researchers. Many other researchers have also contributed with
critical thickness theories based on energy, mechanical equilibrium and
kinetics of dislocations [11–13]. The critical thickness theories based
on dislocation formation are disputed by some researchers because other
factors, such as wafer preparation and particulate contamination, may play
a much larger role in determining misfit dislocations [14]. Furthermore,
methods for determining whether a layer is strained or relaxed may not
have enough sensitivity to detect the onset of dislocation formation [15].
As a result, dislocation techniques with poor resolution overestimate the
critical thickness. Determination of the critical thickness curve depends on
the deposition methods and characterization methods used. Nonetheless,
most researchers concur that the Matthews–Blakeslee equilibrium curve
distinguishes the point where strained-Si1−x Gex layers cannot sustain
extended thermal processing.
When a thin film with a larger lattice constant (e.g., Si1−x Gex )
is grown on a smaller lattice constant substrate (e.g., silicon), the film
maintains an in-plane lattice constant of the substrate and is under
a biaxially compressive strain. Since layer sequences with well-defined
electrical and optical properties require coherence of the in-plane lattice
constant, biaxial strain is always present in such heterostructures. This
asymmetry of the strain with respect to the (001) growth direction leads
to a splitting of the sixfold degenerate conduction band and also of the
heavy-hole/light-hole valence band degeneracy. The band ordering in this
heterosystem is therefore strongly strain dependent, and a type I band
alignment is obtained where the entire band offset occurs in the valence
band (figure 2.4(a)) while the band offset in the conduction band is very
small. This type of structure is favourable for hole confinement and has
been exploited in several novel heterostructure devices, namely buried
channel p-MOSFETs, p-MODFETs and HBTs (see for example, a review
by Konig and Daembkes [16]).
Similarly, a smaller lattice constant silicon epilayer (strained-Si) will
be under biaxial tension when grown on a larger lattice constant relaxed-
Si1−x Gex substrate. In this case, type II band offset occurs (figure 2.4(b))
and the structure has several advantages over the more common type I
band alignment. A large band offset is obtained in both the conduction
and valence bands, relative to the relaxed-Si1−x Gex layer [7]. This allows
both electron and hole confinements in the strained-Si layer, making it
useful for both n- and p-type devices for strained-Si/SiGe-based CMOS
technology. The ability to achieve both n-MOS and p-MOS devices
Strained layer epitaxy 39
Figure 2.4. Band alignments for (a) Si0.8 Ge0.2 on (001)Si, (b) strained-Si
on (100)Si0.8 Ge0.2 and (c) Si0.6 Ge0.4 /Si heterostructure on (001)Si0.8 Ge0.2
substrates.
Many methods exist for depositing low-temperature silicon and Si1−x Gex
on silicon. These can be broadly categorized into physical deposition and
chemical vapour deposition (CVD) methods. To cope with the difficulties of
growing SiGe alloys, molecular beam epitaxy was used at first to produce
thin, device quality films. MBE is a physical vapour deposition method
and is mostly used for the deposition of III–V compound semiconductors
because of the excellent control of layers. Pioneering studies in the mid-
1980s at AT&T Bell Laboratories, IBM Thomas J Watson Research Center
and Daimler–Benz Research Laboratories, Germany, British Telecom, UK,
Hitachi and NEC, Japan, among others, used molecular beam epitaxy
to show that SiGe alloys could be bandgap-engineered controllably and
successfully used to realize a host of novel electronic and photonic devices.
MBE allows the fabrication of moderately defect-free heterojunctions.
However, MBE not being a production tool, they are only used for
demonstration devices.
On the CVD side, Gibbons et al [32] at Stanford were one of the
first groups to demonstrate high-quality Si1−x Gex on silicon. Towards
commercialization of SiGe technology, the development of UHVCVD by
Meyerson et al [33] at IBM has been a key step forward which appeared
at nearly the same time in the mid-1980s as limited reaction processing
CVD (LRPCVD). The UHVCVD reactor combines a standard diffusion
furnace with an ultrahigh vacuum and has made the most significant
impact in the fabrication of Si/Si1−x Gex HBTs. An excellent review of
this technique, and of the devices fabricated using this method of growth,
has been published [34]. Other CVD techniques have also been used to
grow device quality SiGe layers [35]. Results of Si1−x Gex film depositions
at atmospheric pressure CVD by ASM, the only commercial entry in the
late 1980s, have been published. These atmospheric CVD results may
Deposition techniques 43
For CVD techniques, gas chemistry and gas purity are very important
issues. Silane (SiH4 ) is more reactive than dichlorosilane (SiH2 Cl2 ),
so a lower deposition temperature is possible. Even lower deposition
temperatures can be achieved by using disilane (Si2 H6 ).
Molecular beam epitaxy is the growth technique most widely used to grow
pseudomorphic Si1−x Gex layers on Si. This is a growth technique where
the thermally evaporated molecules of the desired species impinge on an
atomically clean heated substrate to form a crystalline solid. The growth
technique is intrinsically clean due to UHV growth environment (base
pressure ∼10−11 Torr). Cryopumps provide an oil-free evacuation system.
MBE is specially suited for the growth of heterostructures requiring precise
control of alloy composition, layer thickness and doping. The main
characteristics of the MBE growth technique are as follows:
• very low growth pressure (∼10−9 Torr) allowing atomic layer by layer
growth on a atomically clean surface;
• low growth temperature (350–600 ◦ C) which minimizes solid state
diffusion and autodoping;
• slow growth rate (0.1–5 Å s−1 ) which permits atomically thin-layer
growth and better uniformity;
• multilayer growth capability that allows growth of quantum well and
superlattice structures;
• in situ surface analysis capability such as high-energy electron
diffraction (RHEED), Auger electron spectroscopy (AES) and x-ray
photoelectron spectroscopy (XPS).
Figure 2.6. Temperature dependence for planar Si1−x Gex growth as a function
of Ge concentration. It is noted that for the Ge fraction more than 0.5, the
growth temperature must be lower than 550◦ C.
46 Film growth and material parameters
2.2.3. UHVCVD
Chemical vapour deposition systems utilize precursor gases that
incorporate the desired atoms to the substrate surface. This technique,
which has been well known for decades, is in many ways simpler than MBE.
CVD is the most advantageous process because it is a high throughput
process and also it has in situ doping capabilities. An ultrahigh vacuum
chemical vapour deposition reactor consists of a diffusion furnace under
ultrahigh vacuum, as shown in figure 2.7. Since the base pressure is
comparable to MBE at 10−9 Torr, the advantages of low contamination
and prevention of native oxide after loading are similar to MBE. UHVCVD
does not use an in situ cleaning step, but relies on the passivation of the
surface immediately after an HF dip [43]. A load-lock is also used to
prevent exposing the deposition chamber to the atmosphere. The gases
SiH4 , GeH4 , B2 H6 and PH3 provide the sources for CVD of p-type and
n-type silicon and Si1−x Gex . The deposition pressure is about 1–2 mTorr,
with deposition rates around 1–2 nm min−1 . The control of the wafer
temperature in a diffusion furnace is extremely good. As a result, a surface
rate-limited reaction results in a very uniform layer.
Limited reaction processing CVD for silicon homoepitaxy and Si1−x Gex
heteroepitaxy was first developed at Stanford University. The unique
feature of this system is that the surface reaction is temperature driven,
and the temperature of the substrate acts as a switch either to initiate
a reaction, terminate a reaction or to change the reaction rate. This
technique employs rapid isothermal processing, and the temperature of
the substrate (hence the reaction rate) can be rapidly varied (as fast as
350 ◦ C s−1 ). In this system, the base pressure is about 1 mTorr and
the gas flows are established at low temperature. Typical gases used
include SiH2 Cl2 , GeH4 , B2 H6 , AsH3 and PH3 as source gases. The
lamps are turned on to raise the substrate temperature and initiate
the deposition, hence the terminology limited reaction processing. As
a result of the rapid temperature transitions, the high-temperature in
situ cleaning step occurs with hydrogen or hydrogen chloride in a short
time, thus reducing the total thermal budget compared to commercial
epitaxial deposition systems. Many other research groups have used
similar configurations and have adopted the name rapid thermal chemical
vapour deposition (RTCVD) instead of LRPCVD because they use gas
switching rather than lamp heating to control the reaction. However, rapid
doping and compositional transitions are possible by using the lamps as
a thermal switch to control the reaction. In situ doping and selective
silicon and Si1−x Gex heteroepitaxy have been demonstrated. Si1−x Gex
layers need to be deposited at a lower temperature to avoid relaxation
and three-dimensional growth problems. The deposition temperature used
for Si1−x Gex is about 625 ◦ C and is increased to 850 ◦ C for silicon cap
layer deposition, if required. One of the major problems with reducing the
temperature, however, is increased oxygen incorporation in the Si1−x Gex
layers. The oxygen incorporation problem may be reduced with the use of
a load-lock and point-of-use filtration of SiH2 Cl2 .
48 Film growth and material parameters
and
qNB xdm
VTS = VFB + φTS − 1 + H(φH ) (2.5)
Cox
where
∆Ev
φTH = 2φF + (2.6)
q
φTH − φH
H(φH ) = ho exp (2.7)
kT /q
where
2
ho = 2Si NB kT / (qNB xdm ) (2.8)
where VFB is the flatband voltage, φTH is the potential at threshold at the
top Si/Si1−x Gex interface, φTS is the potential at Si/Si1−x Gex interface,
φF is the Fermi potential, q is electronic charge, NB is the effective doping
concentration in the bulk of the semiconductor, xdm is the maximum
depletion layer width in strong inversion, tSi is the Si cap layer thickness,
tox is oxide thickness, ox is the oxide permittivity, k is the Boltzmann
constant, T is temperature and ∆VT = VTH − VTS .
By subtracting equation (2.5) from equation (2.4) and rearranging, a
system of two nonlinear equations (2.9) and (2.10) with ∆Ev and φH as
unknown is obtained:
2
kT tSi Cox (∆VT − ∆Ev ) −1
∆Ev = φH −2φF + ln 1 + Cox + −1 (ho )
q Si qNB xdm
(2.9)
and φH is given by
2
kT Si (φH − 2φF ) −1
φH = φTH − ln − 1 (ho ) . (2.10)
q qNB xdm tSi
Figure 2.8. Apparent doping versus distance from the Si/SiO2 interface. Data
obtained from the high-frequency C–V measurements.
2.4.1. Si/SiGe
calculated strained value lies in between the two dotted curves. The
calculations for the bandgap of strained-Si1−x Gex were confirmed by
Lang [93] using photocurrent spectroscopy. The bandgap depends on the
germanium fraction in both cases, but strained-Si1−x Gex experiences a
faster drop in bandgap than the unstrained case due to splitting of the
valence band degeneracies. Figure 2.9 indicates that strained-Si1−x Gex
layers need less germanium to achieve the desired bandgap difference.
The bandgap alignment for strained-Si0.8 Ge0.2 on silicon appears in
figure 2.9 based on pseudopotential and deformation potential calculations
by van de Walle [82] and People [81]. Since the conduction band
discontinuity is much smaller than the valence band discontinuity,
researchers often ignore the conduction band discontinuity. Quantum
confinement of electrons at the Si–strained-Si1−x Gex heterointerface is
difficult because of the small conduction band discontinuity. However, the
56 Film growth and material parameters
state of the initial substrate plays a major role in determining the band
offsets, as shown in figure 2.9. In fact, calculations show virtually any
bandgap alignment is possible [14].
2.4.2. Si/SiGeC
Present knowledge about the band structure of tensilely strained-SiGeC
ternary alloys on Si001 is limited. Assuming an average band structure
for Si1−x−y Gex Cy alloys, Soref [94] has suggested an empirical interpolation
between Si, Ge and diamond (C) for the bandgap which increases in the
fundamental gap of Si1−x−y Gex Cy layers with increasing y. This result
has been contradicted by Demkov and Sankey [95] who have shown that
the fundamental gap is reduced when a small percentage of carbon is
added to the silicon lattice. This reduction in bangap is in agreement
with the photoluminescence measurement data. To describe adequately
the observed energy shifts for pseudomorphic carbon-containing layers,
strain-induced effects and effects due to alloying should be considered
[96]. An estimation for the band offsets and the fundamental bandgap
for Si1−x−y Gex Cy alloys (containing up to 3% carbon and 30% Ge
concentration) tensile or compressive strained has been reported by Osten
[97]. This estimation considers both the band alignment at the interface of
two different materials, as well as strain effects.
Figure 2.10 summarizes the results for the highest valence band
for different tensile and compressive strained-Si1−x−y Gex Cy layers on
Si001. The plot shows ∆Ev as a function of the effective Ge or C
Figure 2.10. Valence band offsets for compressively strained Si1−x Gex and
Si1−x−y Gex Cy (x = 10%, 20% and 30%, y varies between 0% and 3%) and tensile
strained Si1−y Cy and Si1−x−y Gex Cy (y = 1%, 2% and 3%, x varies between 0%
and 30%) plotted as a function of the effective lattice mismatch—expressed in
‘effective’ Ge or C concentrations, respectively. (After Osten H J 1998 J. Appl.
Phys. 84 2716–21.)
Bandgap and band discontinuity 57
2.4.3. Strained-Si
2.5. MOBILITY
Strain not only modifies the bandgap energy and band alignments but also
lowers the effective mass at the band edges and higher mobilities may be
expected [102]. In the following, we discuss some experimental work used
to determine mobility in strained layers. A more comprehensive discussion
of the electron and hole mobility on strain level and the band structure will
be given in chapter 4.
2.5.1. Si/SiGe
Calculations have been made for strained and unstrained Si1−x Gex that
have shown an increased electron mobility perpendicular to the growth
interface and increased hole mobility parallel to the growth interface for
strained layers with increasing Ge content. If an Si1−x Gex strained epilayer
is grown on (100) Si, the splitting of the conduction band minimum due
to strain reduces the effective mass and improves the electron mobility in
a direction perpendicular to the interface by about 50% [103, 104]. These
results, however, have been contradicted by other simulations showing that
the mobility peaked and then decreased with increasing Ge concentration
[105, 106]. If the epilayer is grown on a thick relaxed-Si1−x Gex buffer
layer with a higher Ge concentration than in the epilayer, the mobility
perpendicular to the layer is reduced while the mobility parallel to the
interface increases [107]. As the doping concentration in the semiconductor
increases, the strict periodicity of the lattice is disturbed by the existence
of the impurity atoms, and various heavy doping effects occur. Besides the
dependence of carrier mobilities on the doping concentration and electric
field, in alloy semiconductors, mobilities also depend on the composition.
It is well known that heavy doping of a semiconductor can reduce the
bandgap. In SiGe alloys and strained layers, the combined effect of strain
and heavy doping on the bandgap and bandgap narrowing have been
reported [8, 108].
2.5.2. Si/SiGeC
Given the potential of Si/Si1−x−y Gex Cy , it is imperative to know its carrier
transport properties and compare them with those in the Si/Si1−x Gex
60 Film growth and material parameters
Figure 2.12. Room temperature mobility (a) and hole density (b) of pure Si
(solid square) and two sample sequences. The first sequence (open squares)
starts with Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content
constant, the strain is subsequently reduced until strain relaxation is reached
Si0.935 Ge0.06 C0.055 then the amount of germanium is reduced leading finally
to Si0.995 C0.0053 . The second sequence starts with Si0.96 Ge0.04 and ends with
Si0.996 C0.004 . (After Duschl R et al 1998 Thin Solid Films 336 336–9.)
Figure 2.13. Temperature dependence of the hole mobility for the compressively
strained Si0.94 Ge0.06 , exact strain compensated Si0.935 Ge0.06 C0.055 and tensile
strained Si0.995 C0.053 layers. (After Duschl R et al 1998 Thin Solid Films 336
336–9.)
2.5.3. Strained-Si
Low-temperature Hall mobility measurements are commonly used to
determine the overall quality of a heterostructure and are used to
optimize the growth parameters. At low temperature, where the thermal
effects and scattering by phonons are dramatically reduced, the electron
mobility becomes very sensitive to residual scattering mechanisms due to
background charge impurities, roughness and dislocation. Experimental
electron mobility data from strained-Si/SiGe modulation-doped structures
may be divided into two categories: (i) data from devices with the uniform
composition buffer and (ii) devices with the compositionally graded buffer.
A detailed discussion on the mobility of electrons and holes in strained-Si
may be found in [17].
At room temperature, strained-Si electron mobility values are between
2000 and 2800 cm2 V−1 s−1 for n-channels [118,119], which exceed those in
bulk-Si MOSFETs by a factor of four to six. High hole mobilities in excess
of 9300 cm2 V−1 s−1 at 4 K in p-type modulation-doped Si/Si0.87 Ge0.13 /Si
heterostructures have been reported by Whall et al [120]. For p-MOSFETs,
room temperature values between 1400 and 1800 cm2 V−1 s−1 have been
reported [121], a factor of six to nine above those of conventional Si p-
MOSFETs. The dependence of low-field electron and hole mobility on
strain level is shown in table 2.2. A more comprehensive discussion of the
dependence of low-field electron and hole mobility on strain level and the
band structure will be given in chapter 6.
64 Film growth and material parameters
2.6. SUMMARY
In this chapter we have given the background for growing different strained
layers using various types of reactors. Basic Si1−x Gex properties and
deposition systems have been briefly covered. A variety of methods exist
to deposit high-quality alloy layers. In addition to depositing layers with
germanium concentrations of at least 15%, control of the germanium profile
to within 1% is desirable for bandgap grading. The use of Si/Si1−x Gex
heteroepitaxial structures for heterojunction devices is hindered by the
lattice mismatch between the two materials. However, strained-Si1−x Gex
layers can be deposited on silicon at or above the Matthews–Blakeslee
critical thickness curve without interfacial dislocations. Typical bandgap
engineering applications may require up to 150 meV bandgap difference.
Therefore, the deposition technique must be able to deposit Si1−x Gex
layers with germanium concentrations of at least 20%. Layers deposited
above the Matthews–Blakeslee curve must contend with thermal relaxation
during thermal processing. Unfortunately, the Matthews–Blakeslee critical
thickness at 20% germanium is only about 20 nm, and is a limitation
for applications requiring higher Ge mole fractions. Partially strain-
compensated or fully strain-compensated SiGeC films may extend the
application areas.
Differences in the reactor design, base pressure, gas chemistry and
deposition temperature do not appear to limit the ability to deposit device
quality group IV alloy layers. MBE is commonly used as a research
tool due to its low wafer throughput. UHVCVD appears to have the
www.ebook3000.com
Bibliography 65
BIBLIOGRAPHY
73
74 Principle of SiGe HBTs
diffusion lengths, and np0 and pn0 are the equilibrium minority carrier
concentrations in the neutral base and emitter, respectively.
In conventional homojunction transistors, the doping concentration in
the emitter is considerably higher than in the base, in order to obtain a
high injection efficiency. For a typical gain of 100, the emitter must be
doped 100 times more heavily than the base. As the doping concentration
increases to more than 1018 cm−3 , bandgap narrowing due to heavy doping
becomes significant [4].
The following substitutions can be made in equations (3.1) and (3.2)
n2io
np0 = (3.3)
Nb
n2ie
pn0 = (3.4)
Ne
∆Ebgn
n2ie = n2io exp (3.5)
kT
where nio is the intrinsic carrier concentration and ∆Ebgn represents the
bandgap reduction in the emitter due to heavy doping.
When bandgap narrowing is included, the current gain β becomes
Ne Lpe Dnb −∆Ebgn
βSi = exp . (3.6)
Nb Lnb Dpe kT
is not to achieve a very high current gain, but to trade it against a high
base doping, necessary to reduce the base resistance.
High values of maximum oscillation frequency and low values of gate
delay τd (for digital switching applications) can be obtained in HBTs [6,7].
Base resistance is an important parameter in determining fmax . In a well-
designed HBT, a value of 50 for β is usually sufficient, so emitter injection
efficiency can be traded for increased doping in the base. Increased base
doping gives rise to reduced base resistance which is also desirable in helping
to avoid punch-through as the base–collector voltage is increased.
High base doping may contribute to the onset of tunnelling current at
the emitter–base junction. This can be avoided by deliberately reducing
the doping concentration in the emitter. Indeed, in the HBT, it is in
principle feasible to consider the possibility of interchanging collector and
emitter, providing additional advantage in some digital circuits. Many of
the specific issues involved in transistor design are more fully covered in
chapter 4. For the remainder of this chapter, we focus in more detail on
device physics, showing how the incorporation of germanium significantly
changes the physics of the base region and the emitter–base and base–
collector junctions.
by the potential barrier ∆Vp in the valence band between base and emitter,
which is also controlled by the input voltage Vbe .
The key idea of an HBT is to lower the potential barrier seen by
the carriers responsible for the output current (electrons in npn devices)
compared with the one seen by the carriers constituting the input current
(holes in npn devices), thereby increasing the ratio of output to input
current, the common emitter current gain of the HBT [5]. This is done
by fabricating the emitter and the base using materials having different
bandgaps. Depending on the layer in which the bandgap is changed
compared to a homojunction device, two HBT configurations can be
distinguished:
(i) in a narrow bandgap base HBT, the bandgap in the base is lowered
thereby increasing the collector current, whereas
(ii) in a wide bandgap emitter HBT, the bandgap in the emitter is
increased compared to the base, resulting in a lower base current.
In both cases, the common emitter current gain is increased by a
factor proportional to exp(∆Eg /kT ) if spike and notch effects at the
heterojunctions are neglected. Note that in an HBT, where the emitter
bandgap is larger than that in the base, the current gain β should
increase when the temperature is lowered, making it possible to operate
the transistors more effectively at cryogenic temperature.
Figure 3.4. Bandgap energy diagram across a graded SiGe HBT in forward
active mode of operation. Of and Wf are the electrical boundaries of the neutral
base region on the emitter and collector sides of the base, respectively. (After
Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis
University of Southampton.)
where
(Dnb )SiGe
ζ= >1 (3.13)
(Dnb )Si
where the symbol ‘–’ refers to a position averaged quantity. The ratio of
(Dnb )SiGe to (Dnb )Si accounts for the strain enhancement of the minority
carrier electron mobility with increasing germanium content [12].
Taking the ratio of Jc,SiGe to Jc,Si , the collector current enhancement
due to bandgap engineering can be estimated by,
Jc,SiGe ∆Eg,SiGe (grade) exp (∆Eg,SiGe (Of )/kT )
≈ ζ̄ γ̄ (3.14)
Jc,Si kT 1 − exp (−∆Eg,SiGe (grade)/kT )
Figure 3.5. Uniform (flat), triangle, and trapezoid Ge profiles in the base of
a SiGe HBT. (After Harame D L et al 1995 IEEE Trans. Electron Devices 42
455–68.)
82 Principle of SiGe HBTs
emitter surface, in the neutral emitter, or in the wide bandgap part of the
emitter–base space-charge region. In the narrow bandgap base, electrons
can recombine with holes in the narrow bandgap part of the emitter–
base space-charge region, or in the neutral base. An additional source
of collector and base current consists of electron–hole pairs created by
avalanche multiplication or thermal generation in the base–collector space-
charge region. The various base current components can be distinguished
by their dependence on emitter–base voltage, base–collector voltage, and
temperature. If both base and emitter material have a high minority
carrier lifetime, which is usually the case in SiGe HBTs, the base current is
dominated by emitter surface recombination current or the current in the
neutral emitter.
Since the boundary conditions for the injected minority carriers into
the emitter remain the same as in the homojunction, the reverse injected
hole current can be written as
qDpe n2ie,Si
qVbe /kT
Jp = e −1 . (3.15)
Nde We
where Nde and Lpe are the emitter doping density and hole diffusion length,
respectively. Equation (3.16) implies that Jp has an ideality factor of unity.
The potential barrier for hole injection into the emitter is the same
for both the homojunction and the narrow bandgap heterojunction device,
which implies that this component of the base current should be identical
in the two devices, if they have similar emitters. This has indeed been
observed in experimental SiGe HBTs and is evident from figure 3.6.
Auger recombination deals with the heavy doping effects. This band-
to-band recombination mechanism occurs at dopant concentrations beyond
1019 cm−3 [13]. One of the main objectives in SiGe HBT design is to lower
the base resistance by increasing the base doping concentration. The lower
base resistance improves high-frequency performance. In the highly-doped
emitter of a BJT, the net effect of Auger recombination is a lower effective
lifetime in the emitter, leading to a shortened diffusion length and increased
base current. In a device simulator this effect is easily included as an extra
term in the current continuity equations.
Figure 3.6 shows the collector and base currents of a flat-base SiGe
HBT (x = 0.2) compared to the corresponding Si homojunction device.
Transit time 83
Figure 3.6. Room temperature Gummel plots of a flat-base SiGe HBT and
silicon control device with similar base sheet resistances, and emitter areas,
showing the increased collector current due to the narrow bandgap base. (After
Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si
heterojunction bipolar transistors PhD Dissertation Princeton University.)
Bandgap grading across the base creates a drift electric field that accelerates
the electron minority carriers through the base. The graded electric field
reduces the amount of base stored charge per unit collector current. This
reduces the energy and time required to move charge in and out of the base
during transients. As a result, the base transit time, τb , decreases.
84 Principle of SiGe HBTs
In any bipolar transistor, the base transit time for constant base doping
can be written as [10]
Wf 2
Wf
Qb nie (z) Nb (y)dy
τb = = dz (3.17)
Ic Of Nb (z) z Dnb (y)n2ie (y)
where Qb is the total base stored charge and Ic is the collector current.
Putting equation (3.10) into (3.17) and integrating, τb,Si [13,14] and τb,SiGe
[9] become:
Wb2
τb,Si = (3.18)
2Dnb
Wb2 kT
τb,SiGe = (3.19)
ζ̄Dnb ∆Eg,SiGe (grade)
kT −∆Eg,SiGe (grade)
× 1− 1 − exp .
∆Eg,SiGe (grade) kT
τb,SiGe 2 kT
= (3.20)
τb,Si ζ̄ ∆Eg,SiGe (grade)
kT −∆Eg,SiGe (grade)
× 1− 1 − exp .
∆Eg,SiGe (grade) kT
The emitter transit time can potentially be a limiting factor in HBTs which
include a low-doped emitter region to avoid tunnelling current from base
to emitter. Such structures are discussed in chapter 4. The effect of base
and emitter transit times on ac performance is more fully discussed in
section 3.7.
Early voltage 85
The rate of change of the neutral base width Wb with respect to the
Figure 3.7. Definition of the Early voltage VA . The linear parts of the output
characteristics of a bipolar transistor are extrapolated to zero collector current.
86 Principle of SiGe HBTs
For a constant base profile, combining equations (3.23) and (3.24) one gets
qn2 (Wb )Dnb (Wb ) Wb
VA = ie Nb (x)/ n2ie (x)Dnb (x) dx (3.25)
Cjc 0
where n2ie (Wb ) denotes the intrinsic carrier density at the end of the neutral
base on the collector side. Combining equation (3.25) with the standard
equation for bipolar current gain
−1
Wb 2
q
β= p(x)/ nie (x)Dn (x) dx (3.26)
Jb0 0
Early voltage 87
q2 2
βVA = nie (Wb )Dn (Wb ) . (3.27)
Jb0 Cjc
which is significantly greater than unity for a profile with finite Ge content.
For finite germanium grading, ∆Eg,SiGe (grade), of more than 1% across the
base, τb,SiGe /τb,Si , ratio will be larger than 1. Therefore, grading Ge across
the neutral base improves not only base transit time, but also Early voltage.
Furthermore, since current gain is essentially enhanced by the difference in
bandgap at the emitter–base junction and Early voltage by Ge grading
across the base, respectively, the composite product βVA is significantly
enhanced by up to two orders of magnitude.
Figure 3.9 shows the SiGe/Si ratio for the three parameters of
interest—current gain, Early voltage, and the product of current gain times
Early voltage [9]. This figure needs to be interpreted with some care, as
the integrated Ge dose across the base has been kept constant in order to
provide a meaningful comparison. In this figure, when ∆Eg,Ge (grade) = 0,
a pure Ge box profile of 8.4% Ge is implied, while ∆Eg,Ge (grade) =
125 meV, (the x-axis limit in figure 3.5), implies a purely triangular profile
from 0–18.6% Ge. Any other grading between these limits indicates the
corresponding trapezoidal Ge profile. The triangular profile has the largest
Early voltage and gain–Early voltage product. The Ge box profile has an
88 Principle of SiGe HBTs
Figure 3.9. Early voltage and current gain Early voltage products. (After
Harame et al 1995 IEEE Trans. Electron Devices 42 455–68.)
heterojunction barrier on the Early voltage have also been reported [17].
A more complete discussion on the effects of parasitic barriers is given in
the following section.
Figure 3.11. Simulation of band diagram and electron concentration for a SiGe
HBT with the doping profile of (a). Note the exponential dopant out-diffusion
tail (diffusion length LD ) into the Si collector region. The band diagram (b) shows
the parasitic conduction band barrier at the Si1−x Gex /Si interface. (c) and (d)
show conduction and valence bands, respectively, at the base–collector junction
for various diffusion lengths LD . (e) The parasitic conduction band barrier
causes a deviation from the triangular electron profile in the base leading to
increased minority carrier charge storage in the base even as Ic decreases. (After
Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si
heterojunction bipolar transistors PhD Dissertation Princeton University.)
92 Principle of SiGe HBTs
The deleterious effect of base dopant out-diffusion from the Si1−x Gex
base into silicon emitter and collector can be limited by inserting thin
undoped Si1−x Gex layers on both sides of the base [20, 21]. These
Heterojunction barrier effects 93
Figure 3.13. Doping profile of HBT structure with undoped SiGe spacer
layers. (After Prinz E J 1992 Base transport and vertical profile engineering in
Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton
University.)
Figure 3.14. Simulated boron doping profile (SUPREM III) for various anneals.
If the Si1−x Gex layer thickness is increased by adding 150 Å thick intrinsic
Si1−x Gex spacer layers on both sides of the base, the diffused boron profile is
still contained inside the Si1−x Gex layer for a temperature below 800 ◦ C. (After
Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si
heterojunction bipolar transistors PhD Dissertation Princeton University.)
94 Principle of SiGe HBTs
spacers have to be wide enough to contain the tail regions of the boron
out-diffusion. Inevitably, this change increases the overall width of the
strained-Si1−x Gex layer, making the structure more likely to relax by
forming misfit dislocations at the interface.
To demonstrate the effect of thermal cycle on SiGe HBT performance,
consider the device structure shown in figure 3.13 with a base doping of
5×1019 cm−3 , a base width of 300 Å and box Ge profile (x = 0.18), leading
to a base sheet resistance of ∼800 Ω/square. The 1017 cm−3 collector
doping represents a trade-off between breakdown voltage BVceo and the
onset of high level injection in the collector (Kirk effect) [25, 26]. If the
base is doped above 2 × 1018 cm−3 a lightly-doped n-Si spacer has to be
inserted between base and emitter to prevent tunnelling leakage in the
emitter–base junction [27].
Figure 3.14 shows calculated doping profiles for a 10 min anneal at
various temperatures and figure 3.15 the corresponding band diagrams for a
structure (a) without and (b) with 150 Å thick spacers. Note the absence of
parasitic barriers in the device with spacers up to an annealing temperature
of 850 ◦ C. However, increase in the thermal budget of the process leads to a
strong degradation of the collector current. The intrinsic spacers, therefore,
substantially improve the tolerance of the device structure for the thermal
budget of the process. These simulations show that in the design of a SiGe
HBT process, intrinsic Si1−x Gex spacer layers on both sides of the base,
should be considered according to the thermal budget of the process. The
critical thickness limitation of the strained-Si1−x Gex layer, however, limits
the total permissible thickness of the base including the spacer layers.
Figure 3.15. Simulated band diagrams for a structure (a) without and (b)
with 150 Å thick spacers for a 10 min anneal at different temperatures. (After
Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si
heterojunction bipolar transistors PhD Dissertation Princeton University.)
less than the classical Kirk effect. In addition, excess charge is stored in
the base, which results in decreased current gain and fT .
Cottrell and Yu [29] and Yu et al [30] attempted to model the valence
band barrier effects at high collector current densities for a SiGe HBT.
The authors noted that the valence band barrier effect appears at high
current densities for npn and at all current densities for pnp devices. Other
researchers [31, 32] examined the effect of two-dimensional lateral carrier
diffusion on the gain. In this case, the electrons accumulating in the
96 Principle of SiGe HBTs
1
fT = (3.30)
2πτec
The major components, due to minority carrier stored charge, are τe for the
neutral emitter and τb for the neutral base region (as previously discussed
in section 3.3). The term τeb represents minority carrier transit time in the
emitter–base depletion region, and is often small enough to be included in
the emitter transit time term. The transit time τb , the delay due to the
excess minority carrier storage in the base, is generally the most significant
term in equation (3.31) and the relevant expressions for a SiGe HBT and
the effect of Ge grading have been given in equations (3.19)–(3.20).
The delay term τbc is known as the collector depletion layer transit
time. It can be approximated as [13, 36]
Wjc
τbc = (3.32)
2vscl
where Wjc is the base–collector depletion layer width, vscl is the carrier
scattering limited velocity which is approximately equal to 1×107 cm s−1 at
room temperature for silicon [37]. For high-speed devices, as the base width
is consistently scaled down, τb reduces, and τe and τbc become progressively
more significant.
The delay term τje is the total charging time associated with emitter–
base and base–collector depletion layers and is given by [3]
kT
τje = (Cje + Cjc ) (3.33)
qIc
where Cje and Cjc are the emitter–base and the base–collector depletion
capacitances. As the collector current increases, it is often assumed that
this transit time component becomes negligible. However, for low power
devices, the effect of low Ic on τje becomes more significant, emphasizing
very clearly the importance of minimizing the junction capacitances Cje
and Cjc .
The delay term τc is the collector charging time [3]
τc = Rc Cjc . (3.34)
peak fT , τe , τb and τbc are usually the dominant terms for an optimal
transistor design [13]. Therefore, to improve the peak value of fT , all three
terms need to be minimized. Eventually high injection occurs and the base
transit time increases at high collector current, causing the reduction in fT
as shown in figure 3.16.
The unity gain cut-off frequency provides a good indication of the intrinsic
delay associated with a bipolar transistor. However, it is not a realistic
parameter for a circuit environment, as it assumes that the output is
short circuited. In addition, it is independent of base resistance and hence
does not take the base resistance base–collector depletion capacitance time
constant into account. These are important parameters for determining
the transient behaviour of bipolar circuits. Therefore, another more
practical and widely accepted figure-of-merit, fmax , is commonly used,
which characterizes the power transfer in and out of the bipolar device.
fmax is defined as the frequency at which the unilateral power gain becomes
unity. Here the output is essentially isolated from the input by an
appropriate external matching circuit comprising reactive and resistive
components. The load that it drives is also assumed to be conjugately
matched to the transistor output impedance. It can be shown [38] that:
fT
fmax = (3.36)
8πCjc Rb
Breakdown voltage, BVceo 99
seem to indicate that impact ionization is more likely to occur deeper into
the collector than originally thought [42]. Therefore, a narrow bandgap
Si1−x Gex -base may not affect the breakdown voltage. A trade-off exists
between the breakdown voltage and the collector velocity saturation effects.
Increases in breakdown voltage for both emitter–base and base–collector
junctions have been obtained by placing lightly-doped spacers on both sides
of the heavily-doped base without incurring collector velocity saturation
effects [43–45].
3.9. SUMMARY
The objective of this chapter has been to describe the basic physics of
SiGe HBTs. Use was made of energy band diagrams in deriving the
expression for collector current in the most general case of a graded base
SiGe HBT. It was evident that significant enhancement in current gain,
base transit time and Early voltage is possible with the incorporation of
germanium in the base region. The way in which the resultant reduction
of emitter and base transit times leads to a corresponding enhancement
in high-frequency performance measures such as fT and fmax was clearly
indicated. The onset of a parasitic conduction band barrier at the base–
collector junction through out-diffusion of boron from the base was shown
to be undesirable, since it increases minority carrier storage in the base,
and reduces both collector current and fT . Consequently, the advantage in
use of thin undoped SiGe spacer layers between base and emitter and base
and collector was discussed.
BIBLIOGRAPHY
104
Design of SiGe HBTs 105
kTL
Dn = µn (4.16)
q
kTL
Dp = µp . (4.17)
q
In the case of the energy balance (EB) model, a higher-order solution to
the generalized BTE is necessary to include an additional coupling of the
current density to the carrier temperature (energy). Then the current
density and energy flux densities are expressed as
|y21 − y12 |2
U= (4.25)
4[Re(y11 )Re(y22 ) − Re(y12 )Re(y21 )]
|y21 |2
MAU G = . (4.26)
4Re(y11 )Re(y22 )
Maximum available gain is obtained when both input and output are
simultaneously conjugately matched. MAG exists only when the device
is unconditionally stable when k > 1. As can be seen from equations (4.25)
and (4.26), U equals MAUG only if the device is unilateral, i.e., y12 = 0.
MAG and MSG are equal to each other once the device is unconditionally
stable. The frequency at which MAG becomes unity is often defined as
fmax . However, a full discussion on the interpretation of fmax is given
in [34]. Since common-emitter microwave transistors may have power gain
with no impedance transformation, they can have useful gain when inserted
into a 50 Ω system. This gain is identical to |s21 |2 .
ATLAS has an option to easily convert y-parameters obtained from
ac analysis, to s-, z- or h-parameters. The unity gain cut-off frequency
is extracted from extrapolation of the high-frequency asymptote of a plot
of the magnitude of h21 in dB versus log (frequency). Most BJT devices
at a sufficiently low frequency can be represented as single pole devices.
This assumption is equivalent to a high-frequency asymptote with a slope
of −20 dB per decade. However, both Cbe and Cbc capacitances are bias
dependent, and so is the cut-off frequency. From the MAG (in dB) versus
log (frequency) plot, fmax is extracted at the point where MAG becomes
0 dB.
Electrons and holes in a device are accelerated by electric fields but lose
momentum as a result of various scattering processes. These scattering
mechanisms include lattice vibrations, impurity ions, other carriers,
interfaces and material imperfection. To simplify these mechanisms for
modelling purposes, mobility is usually defined as a function of lattice
temperature, local electric field and doping concentration. In a device
simulator, a mobility model is further subdivided into
• low-field behaviour,
Material parameters for simulation 111
• high-field behaviour,
• bulk semiconductor regions, and
• inversion layers.
model,
2.4 × 107
vsat (T ) = (4.28)
1 + 0.8 exp (T /600)
but specific values for holes and electrons can be specified, if required.
The incorporation of germanium significantly changes the properties
of the base region and the emitter–base and base–collector junctions in a
SiGe HBT. While silicon has been well characterized over the past 40 years,
still not nearly as much is known about strained-SiGe. Many simplifying
assumptions are made in the SiGe material parameters. The addition of
Ge reduces the bandgap of Si, leading to the narrow bandgap SiGe base of
the HBT, as discussed in chapter 3. The lattice constant of the strained-
Si1−x Gex alloy differs considerably from that of Si. The incorporation
of Ge also modifies the energy band structure, and density of states in
the conduction and valence bands. In addition, carrier mobilities and
diffusivities change owing to changes in the effective masses and alloy
scattering. Finally, the dielectric constant, built-in potentials and depletion
widths in the p–n heterojunctions depend on the Ge concentration. As all
the device simulations reported in this book have been carried out using
the Silvaco–ATLAS simulator [8], we consider in the following section, the
material parameters used in the simulations.
where
(µmax (x) − µmin (x))
ρ= µmin (x) +
1 + (Ntot /2.35 × 1017 )0.88
−1
µmax (0) − µmin (0)
× µmin (0) + (4.31)
1 + (Ntot /2.35 × 1017 )0.88
where
µmin (x) = 68.7 exp 51.2x3 − 34.2x2 + 8.7x (4.32)
and
µmax (x) = 461.9 exp 32.5x3 − 22.2x2 + 6.4x . (4.33)
5.5 × 1018 T
µalloy
⊥ = (4.34)
22.0Nc x(1 − x)m2t
5.5 × 1018 T
µalloy
= (4.35)
4.0Nc x(1 − x)m2l
where Nc is the effective density of states for silicon.
It may be noted that the alloy mobility decreases with increasing Ge
content. At low doping levels, alloy scattering and phonon scattering
predominate, both of which have an E 1/2 dependence. At high doping
levels, impurity scattering becomes important, and it too has the same
energy dependence. Since the conduction band of SiGe for x < 0.3 is
similar to that of silicon, and all the predominant scattering rates have an
114 Design of SiGe HBTs
where the mobility of silicon for parallel and perpendicular to the growth
plane is expressed as [43]
3.0µSi
µSi
⊥ = (4.38)
(mt /ml + 2.0)
3.0µSi
µSi
= (4.39)
2.0(ml /mt ) + 1.0
where ml and mt are longitudinal and transverse density of state masses
in silicon.
At very high concentrations, the Caughey–Thomas relationship [38]
no longer suffices to describe the carrier mobility. The effect of ultrahigh
concentrations on mobility have been analysed by Klaassen [36], and the
modified expression for majority and minority mobility for electron in sili-
con is given by:
2.0µSiGe
⊥ exp(−∆Ex /kT ) + µSiGe
exp(−∆Ez /kT )
µzz = (4.44)
2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT )
where ∆Ex = −0.21x and ∆Ez = 0.42x are the splitting energies due to
the shift in the [001], [010] and [100] bands.
Despite the apparent complexities of the latter model, a more
straightforward model has been proposed in the 1D SCORPIO simulator
[18], which describes the mobility enhancement of both carriers in SiGe as
a linear function
µSiGe (x) = (1 + K.x)µSi (4.45)
where K is a fitting constant taken to be 10. Although there are conflicting
reports concerning the degree of SiGe mobility enhancement which occurs
in a HBT, Richey et al [18] conclude that their much simpler model gives
excellent agreement with measured data.
A linear fit is used for 0.6 < x < 1.0, which assumes that the bandgap of
strained pure Ge on (100) Si is 0.6 eV. Note that the bandgap of strained-
SiGe is considerably smaller than that of bulk-SiGe.
In ATLAS, to give increased accuracy, the SiGe bandgap is modelled
by a complex piecewise linear function of x, as defined in full in the ATLAS
manual. For values of x likely to be encountered in a SiGe HBT (x < 0.245),
the following equation applies
α = (4.73(1 − x) + 4.77x)10−4
β = 636.0(1 − x) + 235.0x.
where h is Planck’s constant, and m∗n and m∗p are the effective masses of
the electron and hole density of states.
The effective density of states decreases with increasing Ge content,
because the amount of degeneracy in both the valence and conduction
band decreases [43, 47]. In ATLAS, an empirical function used to give the
composition dependence of densities of states for SiGe is given by:
By using equations (4.53) and (4.54), one can calculate the intrinsic carrier
concentration as a function of the Ge content
2 Eg (x, T )
nio (x) = Nc Nv exp − . (4.55)
kT
(4.56)
In early 1989, Won and Morkoc [60] examined theoretically the high-
speed capability of the SiGe HBTs. They included alloy scattering and
strain effects on the mobility in the model. Several doping concentrations
were considered. The collector and base doping concentrations were
optimized by making a compromise between speed and breakdown voltage.
If the parameters are optimized to obtain an fT of 75 GHz, the estimated
fmax value is 35 GHz at a current density of 1×105 A cm−2 and Vbc = 5 V.
The theoretical work done during this period showed that the HBTs had
great promise, once technological problems encountered in their fabrication
were resolved.
Hueting et al [61] have optimized a SiGe HBT design for high-
frequency performance and claimed that a box type Ge profile with the
leading edge approximately in the middle of the base is optimal. The
doping concentrations in the emitter, base and collector were 2 × 1021 ,
2.2 × 1018 and 1 × 1017 cm−3 , respectively, while the Ge concentration in
the base was 11.5%. An fT value of 45 GHz for a base thickness of 600 Å
was obtained. Hueting et al studied the effect of grading the Ge profile
in the base and concluded that (in their opinion) the grading of Ge in the
base is of minor importance. Several other simulation techniques such as
Monte Carlo [62–64], energy transport [19, 65] have also been employed for
the simulation studies of SiGe HBTs.
Figure 4.1. Doping profile and Ge profile (flat or box) of a SiGe HBT.
122 Design of SiGe HBTs
Figure 4.3. Comparison of dc current gain of an Si BJT and a flat base SiGe
HBT.
Figure 4.4. Simulated cut-off frequency of an Si BJT and a flat base SiGe HBT.
for lower base resistance. Using this approach, both fT and base resistance
can be tailored to significantly increase fmax . It is seen from figure 4.6 that
for a graded Ge profile in the base, fT has increased from 42 GHz (Ge box
profile) to 63 GHz, but the gain has dropped from 360 to 200, as shown in
figure 4.7.
A trapezoidal profile would appear to be a logical compromise between
the two previous Ge profiles. This type of profile was used successfully
to realize the first 1.0 Gb s−1 12-bit digital-to-analogue converter [77].
Figures 4.8 and 4.9 show a simulation of a trapezoidal profile where the Ge
mole fraction at the emitter–base edge is 5% and it has been graded to reach
a maximum Ge concentration of 15% at the base–collector junction. It is
seen that the trapezoidal grading results in a good compromise between
peak current gain of 200, and fT of 50 GHz.
126 Design of SiGe HBTs
Figure 4.6. Comparison of peak cut-off frequency of a graded base versus a flat
base SiGe HBT.
Figure 4.7. Comparison of dc current gain of a graded base and a flat base SiGe
HBT.
is ideal to decouple the base from the emitter, thereby allowing arbitrarily
high base dopant concentrations. Furthermore, it allows a reduction in
emitter–base capacitance, leading to higher fT at lower collector current
density, as long as the delay associated with minority carrier charge storage
in the quasi-neutral emitter can be minimized by maintaining sufficient
current gain. A high–low emitter profile, consisting of a heavily-doped
polysilicon contact on top of a thin epitaxial emitter cap addresses both
requirements [78]. The emitter cap thickness should be small to minimize
charge storage and is typically 200–300 Å. The highly-doped polysilicon
contact ensures low total emitter resistance.
128 Design of SiGe HBTs
taking full advantage of the Ge grading to minimize the base transit time.
The slope of the Ge profile at the edge of the emitter–base space-charge
region on the base side can affect the ideality of the collector current [79].
Figure 4.10. Emitter with different low-doped spacer layers. Ge and Boron
profiles in the base are also shown.
applications, as they increase the input capacitance of the device via the
Miller effect. Optimizing the collector profile consists therefore in trading
an increased transit time τec , arising from an increase in τbc with reduced
collector doping, for a reduction in the base–collector capacitance. This
point is considered again in chapter 5 where two variants of a process are
considered: one to achieve very short ECL gate delay by using a relatively
low collector doping and the other using a much higher collector doping to
achieve fT of more than 100 GHz. Figure 4.13 shows the effect of collector
doping on the simulated output characteristics. It is evident that the profile
with the highest fT yields the lowest BVceo .
Zπ
Z11 = rbb + ree + (4.61)
1 + gm Zπ
Zπ
Z12 = ree + (4.62)
1 + gm Zπ
Zπ gm
Z21 = ree + 1− (4.63)
1 + gm Zπ jωCbc
1 1 Zπ
Z22 = rcc + ree + + (4.64)
jωCbc 1 + gm Zπ 1 + gm Zπ
where
rbe
Zπ = . (4.65)
1 + jωrbe Cbe
If small-signal ac simulations are carried out at relatively high frequency
(typically in the range 0.02–0.1 fT ), then since gmo ≥ 1/|Zπ |
1
ree = Re (Z12 ) − (4.66)
gmo
Im(y12 )
Cbc = − (4.69)
ω
at a frequency low enough that the reactance of Cbe does not affect Re(y11 ).
Figure 4.15 shows how the value of base resistance, extracted using
equation (4.67), varies with frequency, as collector current is increased.
The well-established mechanism of reduction in base resistance at higher
collector current due to current crowding is evident in this figure. The
choice of frequency is important in so far as one would like to evaluate
the base resistance at a frequency where the extracted value is relatively
insensitive to the choice of frequency. Based on the pattern of variation
seen in figure 4.15, it would appear that extraction of rbb at a frequency
of around 1 GHz, significantly below fT would appear to be a reasonable
choice.
Figure 4.16 shows that the equations (4.67) and (4.68) for rbb and
rcc based on z-parameters are relatively independent of frequency in the
range 1–8 GHz and it is clear that while rbb can be relatively accurately
determined from z-parameters (rather than h-parameters), the small value
of rcc , believed to be of the order of 20 ohms from sheet resistance
calculations, is masked by the much higher value of more than 200 ohms of
the additional term involving the ratio of capacitance. This point is further
illustrated in figure 4.17, which shows that the total output resistance can
be estimated by two methods: one using z-parameters, the other using
h-parameters. As indicated on the figure, both expressions nominally give
the same value. Neither equation however, is exact. Both involve a degree
of approximation, and the expected value of rcc is of the same order as the
likely error in using either of the two expressions. This example highlights
the difficulty which can occur in determining collector series resistance from
small-signal parameters.
To evaluate gm , it transpires that the most appropriate method is to
use h-parameters, rather than y-parameters. It has been shown that for
the small-signal equivalent circuit shown [34]
Re(h21 )
gm = . (4.72)
Re(h11 )
Figure 4.18 shows that the above equation involving the ratio of
5 rbb
τdel = rbb Cbc + τF + (3Cbc + CL ) RL (4.79)
2 RL
142 Design of SiGe HBTs
where summation over i includes all the resistances and capacitances of the
logic gate and those associated with the emitter, base and collector of all
the transistors in the circuit.
Shafi et al [92] calculated the numerical values of gate delay for SiGe
HBTs and compared these with similar computations for homojunction
devices. A Ge concentration of 12% was shown to be required in the SiGe
base to provide sufficient gain enhancement to allow the reversal of the
usual emitter and base doping concentrations. This results in a transistor
with a low base resistance and low emitter–base depletion capacitance. For
a fully optimized device, predicted propagation delays were 15 ps for the
SiGe HBT and 29 ps for the Si BJT. Subsequently, as SiGe technology
has developed over the last decade, bipolar scaling to ultrathin base and
0.2 µm self-aligned technology has given rise to a propagation delay as low
as 6.7 ps by a research group from Hitachi [75].
In order to simulate ECL delay, circuit simulation using SPICE must
be used. If the two-dimensional structure of the transistor is known, device
simulation can be used to extract key SPICE parameters such as τF , Cje , Cjc
and rbb from small-signal ac analysis, as illustrated in the previous section.
These SPICE parameters can then be used in a circuit simulation to predict
variation in ECL gate delay with collector current. The advantage of this
approach is that it provides insight into how the process can affect the
circuit performance.
Table 4.1 presents a representative sample of key SPICE parameters
extracted for a scaled SiGe HBT process based on silicon-on-insulator (SOI)
technology [94]. The technology, outlined more fully in chapter 5, utilizes
an epitaxial base and lightly-doped emitter. To allow for effects of boron
Small-signal ac analysis 143
well below the current level at which peak fT is predicted. In addition, the
creation of the bipolar transistor in an SOI rather than a silicon substrate
yields approximately 20% improvement in fmax due to lower collector–
substrate capacitance in the SOI substrate, as shown in figure 4.21. In this
figure, circuit simulation using SPICE parameters extracted from ATLAS
has been used to determine fmax .
With the simulated values of base resistance as an input parameter
for SPICE, ECL gate delays have been computed as a function of base
resistance and are tabulated in table 4.2. It is seen that, as expected, the
ECL gate delay decreases with the decrease in rbb and the minimum value
is comparable to the experimentally reported values for a SiGe HBT of
comparable dimensions [95].
Table 4.2. The dependence of ECL gate delay on base resistance. SPICE
parameters used: VAF = 130 V, Cje = 7.5 pF, Cjs = 13 pF, Cjc = 5.5 pF.
4.8. SUMMARY
This chapter has considered how a SiGe HBT can be modelled in a device
simulator. The relevant equations, relating to current flow in a structure
where the bandgap is varying, were considered. Basic concepts employed
in a simulation program were given. Key material parameters for SiGe,
in so far as they differ from silicon, were outlined. A more accurate
strained layer SiGe mobility model should be used to take into account the
different mobilities (parallel and perpendicular to the growth direction) of
the strained-SiGe layer.
The way in which ac simulation can be utilized to determine small-
signal y-parameters was considered. Knowledge of y-parameters then
permits any other small-signal parameter to be evaluated. In this way,
both fT and fmax can be determined. A specific study of the design of an
HBT with a base width of approximately 60 nm was fully described. Base,
emitter and collector profile design issues were discussed in detail. High
βVA product necessary for analogue applications is of special interest, as
it is achievable using SiGe HBTs. Devices with three different Ge profiles
(flat, triangular and trapezoid) were considered. The optimum Ge profile in
the base was shown to be a trapezoidal profile. A retrograde collector profile
allowed the condition fT = fmax to be optimized, whilst still achieving
acceptable BVceo .
The significance of the ECL gate delay and the way in which device
simulation can be used to predict ECL gate delay was outlined. Gate
delays of ECL circuits involving SiGe HBTs were computed using SPICE
parameters extracted using small-signal analysis.
BIBLIOGRAPHY
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1999 Full-band Monte Carlo device simulation of an Si/SiGe HBT with a
realistic Ge profile Int. Conf. on Simulation of Semiconductor Processes
and Devices, SISPAD’99 pp 219–22
[65] Bartels M, Decker S, Neinhus B, Bacht K H, Schuppen A and
Meillerzhagen B 1999 Comprehensive hydrodynamic simulation of an
industrial SiGe heterobipolar transistor IEEE BCTM Proc. pp 105–8
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Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Profile leverage
in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM
Tech. Dig. pp 21–4
[67] Burghartz J N, Comfort J H, Patton G L, Meyerson B S, Sun J Y-C,
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[68] Harame D, Nguyen-Ngoc D, Stern K, Larson L, Case M, Kovacic S,
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and Meyerson B 1995 SiGe HBT technology: device and application issues
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Megdanis A C, Sun J Y-C and Stork J M C 1992 73 GHz self-aligned
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1995 Enhanced SiGe heterojunction bipolar transistors with 160 GHz fmax
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150 Design of SiGe HBTs
152
Simulation of SiGe HBTs 153
Figure 5.1. Doping profile and Ge profile (graded base) of a SiGe HBT.
154 Simulation of SiGe HBTs
associated with the extrinsic base region [15]. The lower bandgap of
SiGe therefore has a great impact on the propagation delay of integrated
injection logic. It is shown by simulation in section 5.7 that that
SiGe I2 L may be a useful technology in high-performance and low-power
applications, such as portable electronic systems [16].
As SiGe HBT technology appears to be exceptionally promising for RF
and microwave analogue applications, the low-frequency noise performance,
a key figure-of-merit, needs to be studied in detail. Section 5.8 presents
a comprehensive study on the noise performance of SiGe HBTs with
Figure 5.2 shows the simulated Gummel plot and it is seen that almost
ideal base current characteristics are observed, with a peak dc current gain
of approximately 210, as shown in figure 5.3. A unilateral power gain of
22 dB at 10 GHz was achieved at a base–collector voltage of 2 V. Even
for a base width of about 500 Å, a high base doping (> 6 × 1018 cm−3 )
maintains a low base resistance and avoids punch-through.
In particular, the high fmax of 74 GHz originates from the integration
of the SiGe base, providing high cut-off frequency at low intrinsic base
resistance. The design can be tailored for optimum ECL or CML
performance by obtaining high fT at low base resistance leading to a CML
gate delay time of 11 ps.
The effect of collector doping on the Early voltage obtained from
the simulated output characteristics is shown in figure 5.4. These
characteristics are obtained by utilizing a constant base current, (Ib =
15 nA), as opposed to the more usual fixed base voltage boundary
conditions. It is seen that as the collector doping concentration increases,
the Early voltage decreases. This reduction in Early voltage with the
increase in collector doping density is expected from the consideration of
equation (3.25) in chapter 3, as a higher collector concentration gives a
higher base–collector capacitance and hence lower Early voltage. The Early
voltage for the lowest collector doping of 5 × 1016 cm−3 is 110 V, leading
to a βVA product of 22 000. A Ge fraction of 12% at the base–collector
junction has helped to provide a high Early voltage.
The dependence of cut-off frequency on the collector current is shown
in figure 5.5 for two different base–collector voltages, while figure 5.6 shows
Figure 5.5. Effect of base–collector reverse bias voltage on the cut-off frequency
of a graded base SiGe HBT.
158 Simulation of SiGe HBTs
Figure 5.7. Schematic cross section of the ultra low-power SiGe base bipolar
transistor with a wedge-shaped CVD-SiO2 isolation and a BPSG-refilled trench.
(After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)
160 Simulation of SiGe HBTs
Figure 5.8. A SIMS impurity profile of the emitter and the base in the intrinsic
region. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)
Figure 5.9. Comparison of Gummel plot for a SiGe HBT. (After Hamel J S and
Tang Y T 2000 Proc. ESSDERC pp 620–3.)
Figure 5.12. Germanium and doping profile for a SiGe HBT with 15% Ge
content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)
Figure 5.14. Cut-off frequency versus peak collector doping in a graded base
SiGe HBT.
Energy balance simulation 165
Figure 5.15. Simulated emitter and base transit time of a SiGe HBT, as a
function of collector current for both drift–diffusion and energy balance models
for Ge mole fraction x = 0.1.
Figure 5.16. Extracted carrier velocity using drift–diffusion and energy balance
models.
166 Simulation of SiGe HBTs
as a function of base bias, for two Ge fractions (x = 0.1 and 0.2), is shown in
figure 5.16. The EB model shows a significant overshoot in the saturation
velocity, sufficient to account for the lower base transit time in figure 5.15,
while the maximum velocity possible with the DD model is limited by
the saturation velocity, vsat = 8 × 106 cm s−1 . A plot of the simulated
electron temperature in figure 5.17, taken as a one-dimensional section
through the active device, shows the expected carrier heating associated
with the high-field region at the base–collector junction. The maximum
of the temperature profile is, however, shifted into the collector region,
as the carriers are accelerated through the high-field region to reach the
maximum temperature. Velocity overshoot occurs in the base region, where
the electric field is high and the temperature is only beginning to rise.
Jn2 Jp2
H= + (5.2)
qµn n qµp p
where Jn,p and µn,p represent current density and carrier mobility of
electrons and holes, respectively. The temperature dependence of κ in
the semiconductor is modelled by [23]
1
κ= (5.3)
a + bTL + cTL2
Figure 5.21. Simulated Gummel plot with and without inclusion of the heat
equation. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator
Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3,
ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)
Figure 5.22. Comparison of heating effect between SOI and silicon substrates.
(After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and
Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment
(Pennington, NJ: Electrochemical Society) pp 249–54.)
The peak temperature occurs, as expected, within the active area of the
transistor. However, it is clear that the thermal via is effective in providing
a heat conduction path to the silicon substrate.
Although an attempt has been made to predict the thermal behaviour
of HBT transistors fabricated on SOI substrates, absolute accuracy is
difficult to achieve because of the error in estimating the degree of
external heat loss, which has been approximated using a thermal resistance
boundary condition at the electrical contacts. The variation in temperature
within the transistor and the dependence of the maximum temperature
rise on thermal resistance have been demonstrated. The reduction in
temperature, which occurs if a thermal via is included, depends on its
alignment relative to the active area.
Table 5.2. Typical SiGe HBT parameters at 310 and 84 K at the wafer level.
(After Cressler et al 1994 IEEE Electron Device Lett. 15 472–4.)
spacer layer reduced the low level parasitic base leakage but gave rise to
carrier freeze-out and an increase of base resistance at 77 K. However, it was
shown that a thin abrupt base profile attainable with epitaxial processing is
particularly useful for low-temperature operation since the resultant profile
is less sensitive to base freeze-out than ion-implanted profiles. The authors
also fabricated homojunction Si BJTs and showed that properly designed
homojunction transistors also have sufficient current gain and switching
speed at 77 K for many digital applications. In several applications,
however, the flexibility offered by using SiGe for base layer yields great
benefits.
Gruhle et al [12] have reported a high-performance SiGe HBT,
fabricated using MBE, having a base doping of 2 × 1019 cm−3 , largely
exceeding the emitter impurity level and a base sheet resistance of about
1 kΩ/square. The device exhibited an Early voltage of 500 V, a maximum
room temperature current gain of 550 rising to 13 000 at 77 K. Devices
built on buried-layer substrates exhibited an fmax of 40 GHz and an fT of
42 GHz.
Sturm et al [32] also fabricated high-quality SiGe HBTs using rapid
thermal chemical vapour deposition. Both graded-base and uniform Ge
profiles in the base were considered. In a transistor with 20% uniform Ge
concentration in the base, currents gain of about 2000 at room temperature
and 11 000 at 133 K were observed. The performance of SiGe HBTs at
liquid helium temperature has been reported by Joseph et al [8]. The
current gain of a self-aligned, UHVCVD-grown SiGe HBT showed an
increase in current gain from 110 at 300 K to 1045 at 5.85 K, although
parasitic base current leakage limits the useful operating current to above
about 1.0 µA at 5.84 K. A very high base doping (peak at 8 × 1018 cm−3 )
was used to suppress the base freeze-out at 4.48 K and resulted in a base
sheet resistance of 18.3 kΩ/square.
Figure 5.26 shows Gummel plots at 300 and 100 K, respectively, for
constant Ge concentration. The simulated collector current characteristic
is ideal over more than ten decades of current. As the temperature is
lowered, the intrinsic carrier concentration decreases exponentially, and for
an observable current to flow at low temperature, the emitter–base voltage
176 Simulation of SiGe HBTs
Figure 5.25. Doping profile and Ge profile (graded case) in a SiGe HBT.
Figure 5.26. Gummel plots of a SiGe HBT (flat base) at 300 and 100 K.
Figure 5.27. The dc current gain of a flat base SiGe HBT at different
temperatures. For comparison, dc current gain at 150 K for a graded base
transistor is shown.
Figure 5.32. Output characteristics (upward mode) of the npn SiGe HBT.
(After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)
182 Simulation of SiGe HBTs
been shown that at low injector currents, the use of SiGe offers only a
marginal benefit, since the switching speed is dominated by depletion region
charge. However, at high injection currents, where the switching speed
is dominated by stored minority carrier charge, the use of SiGe in I2 L
technology has been shown to have important benefits. The inclusion of
16% Ge in the substrate-fed I2 L gate leads to a decrease in the dominant
stored charge by a factor of more than ten, which suggests that gate
delays well below 100 ps should be achievable, even at a geometry of
3 µm. The model has also been applied to predictions of the performance
of a self-aligned structure, specifically optimized for SiGe I2 L. For a Ge
concentration of 16% in the base, a maximum delay of 34 ps was predicted
using 1.4 µm design rules.
Figure 5.35. Noise spectral density at two different temperature points (358
and 218 K) of Si and SiGe devices of an emitter area of 3 × 0.5 µm. (After
Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)
Noise performance 185
demonstrate that the Ge incorporated in the base does not degrade the
noise performance and that SiGe HBTs have better noise performance than
AlGaAs/GaAs HBTs and conventional ion-implanted Si BJTs.
Even though SiGe HBTs have demonstrated better noise performance
over Si BJTs at low frequency, even better high-frequency noise
characteristics may be expected if the Ge profile is optimized specifically
to address this issue. The SiGe HBT design issues associated with
minimization of broadband noise have been considered by Ansley et al [43].
Using the 1D simulator SCORPIO, the effect of the Ge profile in the base on
the minimum noise figure at high frequency was theoretically investigated.
The analysis was based on an equivalent circuit noise model originally
formulated by Hawkins [44], as shown in figure 5.36. The model accounts
for thermal noise in the source (vs ), base resistance (vb ), shot noise in the
emitter (ve ) and collector partition noise (icp ). The resulting expression
for noise factor may be approximated with sufficient accuracy by
Rb Re (1 − (2πf )Cje Xs )2 2
F 1+ + + (2πf )Cje Rs
Rs 2 Rs
1 + (2πf )2 τb2 Rs Xs2
+ −1 + (5.5)
α0 2Re 2Re Rs
where Rs is the source resistance, Xs is the source reactance, Re is the
dynamic emitter resistance (thermal voltage divided by emitter current)
and Cje is the emitter–base depletion capacitance, α0 is the common base
dc current gain and f is the frequency at which the noise factor is evaluated.
This formulation helps in determining the relative contribution of each of
the terms which control the noise factor. As a guide, the presence of Ge
Figure 5.36. Equivalent circuit schematic of Hawkin’s noise model for bipolar
transistors. (After Hawkins R J 1977 Solid-State Electron. 20 191–6.)
186 Simulation of SiGe HBTs
Figure 5.37. Ge profile which allows optimization for NFmin compared to the
conventional graded Ge profile. Emitter and base carrier concentrations are
shown for reference from polySi interface in emitter to base–collector junction
(at right edge). (After Ansley W E et al 1998 IEEE Trans. Microw. Theory
Tech. 46 653–60.)
Figure 5.38. Effect of base doping level on the noise factor sources for the
scaled base profile using a base link sheet resistance of 500 ohms/square. (After
Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)
188 Simulation of SiGe HBTs
Dose-rate effects and proton energy effects have been studied in detail for
this technology, mainly by Cressler and his group [45–47]. Characteristics of
proton and gamma irradiated SiGe HBTs and gated lateral pnp transistors
(GLPNPs) have been reported [48].
Figure 5.41. Device cross section for the gated lateral pnp transistor and SiGe
HBT. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.)
Figure 5.42. Simulated electron (solid curve) and hole (dashed curve) densities
versus depth with VGB (gate-to-base bias) change at Vbe = 0.45 V. (After Niu G
et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.
192 Simulation of SiGe HBTs
5.9. SUMMARY
BIBLIOGRAPHY
STRAINED-SI
HETEROSTRUCTURE FETS
196
Strained-Si heterostructure FETs 197
Figure 6.1. Band alignments between Si and Si0.70 Ge0.30 on two substrates:
(a) Si and (b) Si0.70 Ge0.30 .
The effect of both strain and alloying on the bandgap of the strained-
Si/SiGe material system has been reported in detail by People [10]. In
particular, the computed conduction and valence band discontinuities have
been based on the calculations of van de Walle and Martin [48]. The
extracted valence and conduction band offsets between the strained-Si and
relaxed-Si1−x Gex layers [49] are plotted against theoretically estimated
values in figure 6.3, showing a good match, particularly at low Ge
concentration. Substituting the extracted conduction and valence band
offset values, the overall bandgap of the strained-Si can be obtained and is
shown in figure 6.4, along with the theoretical calculations of People [10].
The heterojunction band offsets (∆Ec , ∆Ev ) in a strained-Si/SiGe
heterostructure have also been determined from measurement of the
threshold voltages of a surface channel strained-Si p-MOSFET structure
(see figure 6.5(a)) [50]. To determine the threshold voltage at the strained-
Si/SiGe interface (VTH ) and the threshold voltage at the strained-Si/SiO2
√
interface (VTS ), the zero current intercept of the IDS –VGS and IDS / gm
characteristics were used. The measured values of threshold voltages VTH
and VTS were −1.0 V and −1.7 V, respectively [50, 51]. The extracted
experimental valence band offset ∆Ev was found to be 160 meV. Using
the valence band offset value, conduction band offset was obtained from
equations (2.11) and (2.12) where x is the Ge concentration in the top part
of a completely relaxed-SiGe buffer cap. The conduction band offset ∆Ec
was found to be about 126 meV for a Ge mole fraction x = 0.18 in the
relaxed-SiGe layer, and agreement with reported results was found to be
good [10, 33].
204 Strained-Si heterostructure FETs
Figure 6.3. Band offsets: (a) valence band and (b) conduction band for
strained-Si to relaxed Si1−x Gex . Calculated curves are from People R 1986 IEEE
J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958
Phys. Rev. 109 695–710.
Figure 6.5. Device structures for strained-Si MOSFETs with (a) Si on the
surface, (b) Si buried and (c) dual strained-Si channels.
206 Strained-Si heterostructure FETs
Figure 6.6. Effective low-field mobility versus effective field for different
n-MOSFETs. The surface channel strained-Si mobility shows a fairly constant
mobility enhancement compared to that of the control-Si device, while the
buried strained-Si mobility peaks at low fields, but decreases rapidly at higher
fields. (After Welser J J 1994 The application of strained-silicon/relaxed-silicon
germanium heterostructures to metal–oxide semiconductor field-effect transistors
(Stanford University).)
Figure 6.8. Effective mobility, µeff versus vertical effective field, Eeff . For
high Eeff , µeff is enhanced by 75% for strained-Si compared to the epi control-Si
device and state-of-the-art universal MOSFET mobility. Data from Welser J et
al 1994 IEEE IEDM Tech. Dig. pp 373–6, Takagi S et al 1994 IEEE Trans.
Electron Devices 41 2357–62. (After Rim K et al 1998 IEEE IEDM Tech. Dig.
pp 707–10.)
of 0.1 µm. In figure 6.8, the effective mobility µeff , measured on large
devices, is shown as a function of vertical effective field Eeff . Even for high
Eeff (>0.5 MV cm−1 ), the effective mobility µeff for the strained-Si device
is enhanced by ∼75% compared to the epi control-Si.
Electron mobility enhancements observed at lower Eeff [25] are thus
sustained at higher effective fields, as predicted theoretically for the
phonon-limited mobility in strained-Si MOS inversion layers [16]. The
measured µeff for strained-Si (peak µeff ∼ 575 cm2 V−1 s−1 ) is also
enhanced over the state-of-the-art n-MOSFET mobility [55]. These results
demonstrate that, unlike conventional Si which is constrained to the
universal MOSFET mobility curve (figure 6.8, dotted curve), strained-Si
provides mobility improvement at a given Eeff . Such an enhancement in µeff
at high channel doping and Eeff enables fabrication of high mobility, deep
submicron devices with channel doping suitable to counter short-channel
effects (SCE).
Device applications 209
Figure 6.12. Comparison of the field-effect and effective hole mobility of long
channel strained-Si and control-Si p-MOSFETs at 77 K: (a) µfe of strained-Si; (b)
µfe of control-Si; (c) µeff of strained-Si; and (d) µeff of control-Si. The effective
electric field values applicable at 77 K for a current threshold value of −1.0 V are
also indicated. (After Maiti C K et al 1997 Solid-State Electron. 41 1863–9.)
Simulation of strained-Si HFETs 213
(150 Å) and relaxed-Si1−x Gex layer (0.7 µm) to avoid the problem of
hole confinement at the strained-Si/SiGe interface, as the valence band
discontinuity is reduced because of Ge grading. For simulation, a channel
length of 0.8 µm and a 130 Å gate oxide thickness were considered.
To account for the enhanced mobility both in strained-Si and SiGe
layers, the low-field hole mobility for Si1−x Gex was modelled following
[61]. The doping concentration and temperature-dependent mobility due
to Arora [62] was modified by using an analytic expression involving Ge
content, x, as
µ(x, T, N ) = µArora (T, N ) 1 + 4.31x − 2.28x2 (6.1)
where µ1p = 54.3 cm2 V−1 s−1 , µ2p = 407.0 cm2 V−1 s−1 , αp = −0.57,
βp = −2.23, γp = 2.546 and Ncp = 2.67 × 1017 cm−3 . Mobility due to alloy
scattering is given by [61]
−1
[µalloy ] = x(1 − x) exp(−7.68x)/124.1 (6.3)
6.5. MODFETS
340 mS mm−1 for a 1.4 µm gate length [72], 390 mS mm−1 for a 0.5 µm
gate device [66], and 330 mS mm−1 for a 0.25 µm gate device [73] have
been obtained. At room temperature, the highest reported Hall mobility
was 2830 cm2 V−1 s−1 [72]. At 77 K and for 1.2% strain, transconductance
of 670 mS mm−1 for a 1.4 µm gate device [72], 520 mS mm−1 for a 0.5 µm
gate device [73] and 600 mS mm−1 for a 0.25 µm gate device [66], have been
measured. Ismail et al [73] have also shown an improved gate design that
220 Strained-Si heterostructure FETs
Figure 6.19. Simulated and experimental current gain and maximum unilateral
gain (MUG) as a function of frequency. Experimental data is from Gluck M et
al 1997 Electron. Lett. 33 335–7.)
Figure 6.23. Computed performance potential for n-type HFETs with and
without velocity overshoot. (After Konig U et al 1998 J. Vac. Sci. Technol. B
16 2609–14.)
one can expect higher transconductance, higher speed, lower gate delay,
lower noise and low power consumption. Due to the enhanced performance
of p-HFETs, equally sized p- and n-FETs can be designed for higher
packing density. While standard CMOS need a gate length below 0.2 µm
for transconductance around 400 mS mm−1 [83, 84], these are even found
at gate lengths of 1.2–1.4 µm with HFETs.
The advantages to be gained by using strained-Si/SiGe in conventional
Si-CMOS technology have been examined by several workers [64,85–88]. As
high electron mobility (2200–3000 cm2 V−1 s−1 ) [28] in strained-Si channels
under tensile strain and hole mobility (800–1500 cm2 V−1 s−1 ) [89] in
compressively strained SiGe channels have been achieved, both n- and p-
type modulation-doped FETs have been fabricated using both strained-Si
and SiGe layers.
For the n-MODFET, the n-doped (phosphorus, 25 keV, 5×1014 cm−2 )
Si0.7 Ge0.3 layer was separated from the Si channel by a spacer of 30 Å thick
Si0.7 Ge0.3 . The Schottky gate was formed by Pt. At a 0.4 µm gate length,
the measured peak transconductance of 420 mS mm−1 was a factor of
two higher than an equivalent Si n-MOSFET, and comparable to GaAs
technology. The microwave performance was also impressive, with an fT
of 40 GHz and an fmax of 56 GHz for a 0.4 µm gate length [85]. This level
of performance is comparable to that of a GaAs/AlGaAs HEMT, and may
potentially be further improved if an insulating SOI substrate is used [90].
For the corresponding p-MODFET, the Si0.7 Ge0.3 layer was doped
with boron, followed by a 25 Å thick spacer, and then a strained 40 Å
Si0.3 Ge0.7 channel, which was finally capped with a 200 Å thick Si0.7 Ge0.3
layer. The peak intrinsic transconductance of 280 mS mm−1 at a 0.23 µm
gate length was more than double the value of the equivalent Si p-MOSFET
at the same gate length, with corresponding high values of fT of 30 GHz
and fmax of 45 GHz [85].
It has been predicted that sub-0.2 µm SiGe HFETs will yield more
than 800 mS mm−1 at room temperature and above 1000 mS mm−1
at 77 K [9]. Figure 6.26 shows the predicted transconductance for
HCMOS extrapolated from measurements on 1.2–1.4 µm MODFETs in
comparison to the best Si-MOSFETs. These results are corroborated by
experimental demonstrations [77,85], which are both based on s-parameter
measurements on mesa-type devices with submicron gates defined by e-
beam lithography.
Based on the above experimental demonstration, using computer
simulation, O’Neill and Antoniadis [64, 87] have investigated the high-
frequency (microwave) performance of submicron p- and n-channel
Si/SiGe-based FETs suitable for CMOS technology. Two-dimensional
simulation of devices, having gate lengths down to 0.1 µm using a
hydrodynamic model, demonstrated an enhancement in fT of around 50%
for n-channel devices and more than 100% for p-channel devices.
228 Strained-Si heterostructure FETs
(a)
(b)
Figure 6.29. (a) Cross section of a proposed Si/SiGe HCMOS technology and
(b) schematic diagram of channel layers and conduction and valence band for
gate bias just above VT . (After Armstrong M A et al 1995 IEEE IEDM Tech.
Dig. pp 761–4.)
Figure 6.30. Power delay product versus stage delay for Si/SiGe HCMOS and
bulk-Si CMOS. The corresponding drain bias values are indicated on the curves.
(After Armstrong M A et al 1995 IEEE IEDM Tech. Dig. pp 761–4.)
6.7. SUMMARY
BIBLIOGRAPHY
and carrier mobility in strained Si, Ge and SiGe alloys J. Appl. Phys. 80
2234–52
[16] Takagi S, Hoyt J L, Welser J J and Gibbons J F 1996 Comparative study
of phonon-limited mobility to two-dimensional electrons in strained and
unstrained Si metal–oxide semiconductor field-effect transistors J. Appl.
Phys. 80 1567–77
[17] Kay L E and Tang T-W 1991 Monte Carlo calculation of strained and
unstrained electron mobilities in Si1−x Gex using an improved ionized-
impurity model J. Appl. Phys. 70 1483–8
[18] Schaffler F, Tobben D, Herzog H-J, Abstreiter G and Hollander B 1992
High-electron-mobility Si/SiGe heterostructures: influence of the relaxed
SiGe buffer layer Semicond. Sci. Technol. 7 260–6
[19] Nelson S F, Ismail K, Nocera J J, Fang F F, Mendez E E, Chu J O and
Meyerson B S 1992 Observation of the fractional quantum Hall effect in
Si/SiGe heterostructures Appl. Phys. Lett. 61 64–6
[20] Tobben D, Schaffler F, Zrenner A and Abstreiter G 1992 Magnetotransport
measurements and low-temperature scattering times of electron gases in
high-quality Si/Si1−x Gex heterostructures Phys. Rev. B 46 4344–7
[21] Monroe D, Xie Y H, Fitzgerald E A, Silverman P J and Watson G P 1993
Comparison of mobility-limiting mechanisms in high-mobility Si1−x Gex
heterostructures J. Vac. Sci. Technol. B 11 1731–7
[22] Rashed M, Shih W-K, Jallepalli S, Kwan T J T and Maziar C M 1995
Monte Carlo simulation of electron transport in strained Si/Si1−x Gex n-
MOSFETs IEEE IEDM Tech. Dig. pp 765–8
[23] Vogelsang Th and Hofmann K R 1993 Electron transport in strained-Si
layers on Si1−x Gex substrates Appl. Phys. Lett 63 186–8
[24] Miyata H, Yamada T and Ferry D K 1993 Electron transport properties
of a strained-Si layer on a relaxed Si1−x Gex substrate by Monte Carlo
simulation Appl. Phys. Lett. 62 2661–3
[25] Welser J, Hoyt J L, Takagi S and Gibbons J F 1994 Strain dependence of the
performance enhancement in strained-Si n-MOSFETs IEEE IEDM Tech.
Dig. pp 373–6
[26] Basu P K and Paul S K 1992 Reduced intervalley scattering rates in strained
Si/Si1−x Gex quantum wells and enhancement of electron mobility: a
model calculation J. Appl. Phys. 71 3617–9
[27] Yamada T, Miyata H, Jhou J-R and Ferry D K 1994 Monte Carlo study of
the low-temperature mobility of electrons in a strained-Si layer grown on
an Si1−x Gex substrate Phys. Rev. B 49 1875–81
[28] Ismail K, Nelson S F, Chu J O and Meyerson B S 1993 Electron
transport properties of Si/SiGe heterostructures: measurements and
device implications Appl. Phys. Lett. 63 660–2
[29] Gamiz F, Lopez-Villanueva J A, Roldan J B, Carceller J E and Cartujo P
1996 Electron velocity overshoot in strained Si/Si1−x Gex MOSFETs Proc.
ESSDERC’96 pp 411–4
[30] Rim K, Welser J, Hoyt J L and Gibbons J F 1995 Enhanced hole
mobilities in surface-channel strained-Si p-MOSFETs IEEE IEDM Tech.
Dig. pp 517–20
[31] Nayak D K, Goto K, Yutani A, Murota J and Shiraki Y 1996 High-mobility
234 Strained-Si heterostructure FETs
Over the past 20 years, the channel length of MOS transistors has halved at
intervals of approximately three or four years. This continual shrinking of
the size of MOS transistors has led to increasing performance in electronic
systems and increasing packing density. The question that arises now is
‘how long can this trend continue?’ A number of factors are posing a threat
to the evolution of CMOS technology. Firstly, the channel length of the
MOS transistor is defined using optical lithography, which is limited by
the wavelength of the radiation used. The current thinking is that optical
lithography can reach channel lengths of around 0.15 µm, but it is not clear
that it can meet the challenge of smaller geometries. Other lithography
techniques exist, such as electron beam and x-ray lithography, but these
have associated problems that remain to be solved.
Improvements in MOSFET saturated drain current have been achieved
by shrinking the source-to-drain separation or effective gate length (Leff )
and through the use of thinner gate oxides to increase the gate capacitance
to improve inversion charge density. Predictions for static random access
memory (SRAM) technology anticipate gate oxide thicknesses of the order
of 4 nm and gate lengths of 0.15 µm (see table 7.1) [1]. However, the
requirement for highly uniform gate oxide films across a large wafer calls
into question the continuous reduction of gate oxide thickness to improve
inversion charge density. Also, below 0.35 µm gate lengths, the carriers
in the channel of the MOSFET attain a saturated velocity that is nearly
independent of Leff . As a result of these two limits—oxide scaling and
carrier velocity saturation—it appears that the MOSFET saturated drain
current is approaching a fundamental physical limit.
In chapter 6, on strained-Si, it has been shown that electron or hole
confinement structures (n-HFET or p-HFET) require more complex growth
techniques for strained-Si on relaxed thick SiGe layers, and are limited in
terms of processing thermal budget. In contrast, the p-HFET is more easily
realized, since it involves the growth of strained-Si1−x Gex epitaxial films
238
SiGe heterostructure FETs 239
Table 7.1. CMOS scaling guidelines. (After Davari B 1996 IEEE IEDM Tech.
Dig. pp 555–8.)
buried-SiGe
0.25 167 201 71 Å Ther. TiSi2 [3]
(enhanced)
buried-SiGe
0.7 64 – 50 Å Ther. polySi [4]
(enhanced)
buried-SiGe
0.9 – – 70 Å PECVD n+ poly [5]
(enhanced)
surface-SiGe
1.0 48 60 100 Å ECR n+ poly [6]
(enhanced)
buried-SiGe
1.0 80 – 65 Å WRTO p+ poly [7]
(depletion)
buried-Ge
4.0 – 50 500 Å CVD Al [8]
(enhanced)
HFETs: structures and operation 241
the SiGe layer can be modulated, due to the increased physical separation
from the gate potential and the presence of a surface inversion layer
that forms at high gate overdrive. However, the buried channel provides
benefits, such as the suppression of hot carrier injection into the gate
oxide and reduced carrier surface scattering, which tend to enhance device
performance and reliability. The next important feature of the device is
the presence of an optional δ-doping spike, which is generally realized using
boron. The doping spike is separated from the SiGe channel by an Si spacer
to reduce ionized acceptor scattering which occurs if the spike is placed
too close to the channel. Furthermore, the doping spike is placed below
the SiGe channel, so that the application of a negative gate bias draws
holes upward towards the SiGe channel. The doping spike has two major
functions:
(i) it creates a retarding electric field for holes at zero gate bias to
suppress source/drain leakage current (threshold adjust); and
(ii) it provides holes for the SiGe quantum well for improved device
transconductance.
Figure 7.3. Cross section of a 0.18 µm p+ -polySi gate Si0.85 Ge0.15 -channel
p-HFET. (After Bouillon P et al 1996 IEEE IEDM Tech. Dig. pp 559–62.)
244 SiGe heterostructure FETs
the Si-cap with increasing gate bias. As more holes populate the Si-cap
inversion layer, the effect of the gate potential is screened out and the
quantum well effectively ‘sees’ no increase in the gate potential. The point
at which the number of holes in the SiGe well equals the number in the
Si-cap is termed the ‘cross-over point’.
Figure 7.7 is a plot of the integrated hole density in the SiGe well and Si-
cap layer as a function of cap thickness, for two oxide (tox = 70 and 140 Å)
thicknesses. The plot reveals that when VG = −2.0 V, for tox = 140 Å, the
hole density in the well decreases slightly as the cap thickness is increased,
while the hole density in the Si-cap shows a modest increase. The hole
density in the well drops more dramatically (for tox = 70 Å) as the cap
thickness is increased while the hole density in the cap increases. Therefore,
it is advantageous to keep the cap thickness as small as possible to keep the
hole population in the Si cap low and reduce the effects of charge screening
on the SiGe quantum well.
If the gate oxide is kept thin (∼100 Å), then an initial Si-cap thickness
of 50 Å is sufficient for a uniform oxide to be grown across a wafer surface.
However, it should be noted that a remaining cap thickness of only 10 Å is
enough to support an inversion layer. Hence, the charge screening problem
Design of SiGe p-HFETs 247
will still be present with such a structure. Consequently, the device can
be operated at low gate voltages, where the SiGe quantum well dominates
device electrical characteristics. A thinner gate oxide results in a higher
current drive and gm due to the improved capacitive coupling between
gate and channel charges. These improvements in performance will always
overcome the disadvantage of the small reduction in VG arising with the
thinner oxide.
Figure 7.8. Simulated Si-cap and SiGe-channel hole density for n+ -poly gate
SiGe HFETs as a function of mole fraction for a flat Ge profile.
Figure 7.9. Simulated high-frequency (x = 0.2, 0.3 and 0.4) and low-frequency
(x = 0.40) capacitance–voltage characteristics showing the hole confinement in
a p+ -poly gate SiGe HFET with an Si-cap (70 Å), oxide thickness (65 Å) and
a SiGe channel 100 Å wide as a function of Ge mole fraction, x, with a flat Ge
profile.
Design of SiGe p-HFETs 249
well. Hence, the structure exhibits a lower effective capacitance due to the
series combination of the oxide and Si-cap capacitances. As the structure
is biased more negatively, the inversion layer in the Si-cap forms and the
capacitance of the structure approaches the oxide capacitance, Cox .
Figure 7.10. Threshold voltage versus substrate doping for p+ - and n+ -poly
gate SiGe-channel p-HFETs.
250 SiGe heterostructure FETs
and a SiGe layer (300 Å) are defined to be doped (1 × 1016 cm−3 and
1 × 1017 cm−3 , respectively), and the underlying substrate (or n-well),
uniformly doped to 1 × 1016 cm−3 . The oxide layer thickness is 80 Å
and interface states are neglected. An n+ -polySi gate is used and the
threshold voltage is allowed to shift freely according to channel doping
and layer thicknesses. The dc output characteristics and small-signal
transconductance have been generated and the respective inversion layer
carrier populations in the Si cap and SiGe channel have been extracted by
integrating the carrier profiles across the depths of the respective layer.
The effect of Ge content on the linear transconductance is shown in
figure 7.11 as a function of gate voltage. When compared to an Si device,
the enhanced mobility in the SiGe-channel p-HFETs gives rise to higher
transconductance, which increases further with Ge content x. The effect
of Ge content on the output characteristics is shown in figure 7.12. As
expected, the drain current increases with Ge content x in a similar manner.
A useful measure for characterizing the subthreshold behaviour of a
MOSFET is its subthreshold swing, S, which is defined as the slope of
the log (ID ) versus VG characteristic, just prior to the threshold voltage,
VT . A low value of subthreshold slope is desirable in submicron gate
length p-HFETs to achieve low threshold voltage and a negligible off-state
leakage. Figure 7.13 illustrates that the incorporation of Ge merely shifts
the threshold voltage and has a negligible effect on the subthreshold slope.
If a δ-doping spike is placed below the active Si1−x Gex channel separated
by a spacer, then the subthreshold characteristic can be significantly
improved [17]. The doping spike creates an electric field that repels holes
for gate voltages below the threshold voltage, significantly improving the
subthreshold swing of the p-HFET.
places severe limitations on its fabrication since the SiGe channel should
remain undoped.
Figure 7.14 shows the output characteristics of a device with a 30 Å
thick Si cap and effective gate length of 0.5 µm is enhanced by the addition
of a 50 Å thick δ-doping layer (Nδ of 2 × 1018 cm−3 ) with a spacer of 30 Å
below the channel. This very significant increase in the device current
demonstrates the improvement in performance possible through epitaxial
growth capabilities, such as in situ modulation doping, apart from gains
achieved through increased mobility. Note that, in this case, an n+ -polySi
gate is required to ensure enhancement mode operation (negative VT ) in
the same manner as for a conventional buried channel p-MOSFET. The
increase in VGS is largely due to the reduction in the transverse field
achieved by the presence of the fully depleted δ-doped layer.
Figure 7.15. Schematic diagrams of a bulk SIMOX substrate and a SiGe SIMOX
substrate in which a p+ -poly gate SiGe-channel HFETs are fabricated. (After
Nayak D K et al 1993 IEEE Electron Device Lett. 14 520–2.)
SiGe p-HFETs on SOI 255
the Si0.7 Ge0.3 quantum well of the SiGe SIMOX device is located farther
away from the Si/SiO2 interface when compared to that in the SiGe bulk
device, which reduces Si/SiO2 surface scattering for the SiGe SIMOX device
and results in a further improvement in channel mobility. Experimentally
verified improvement in channel mobility of a SiGe SIMOX device over that
of an identically processed SIMOX device is 90% at 300 K [7], whereas the
maximum improvement in channel mobility of a SiGe bulk device over that
of an Si device has been found to be 50% [3, 4]. This large enhancement
of channel mobility for the SiGe SIMOX device is believed to be due to
improved hole confinement in the buried quantum well of this device.
Silicon-on-sapphire (SOS) technology, which integrates both the
microwave and the VLSI digital/analogue signal processing functions, is
ideally suited for microwave circuits since it has a low dielectric loss
substrate, low noise figure, excellent radiation hardness and reduced
punch-through effects. Recent studies of SiGe CMOS on sapphire
technology [29, 30] have shown improvements in p-MOSFET mobility and
transconductance at 300 and 77 K, compared to Si. Both cut-off frequency
and low-field mobility, µeff improve with the integrated Ge dose in the
SiGe channel. Table 7.3 compares the performances of several devices
while figure 7.18 shows a comparison of the measured and simulated linear
transconductance of a SiGe p-HFET (flat Ge 20%) fabricated in sapphire
technology at 300 and 85 K.
SiGeC p-HFETs 257
Since the increase in the Ge content leads to a larger strain and reduced
thermal stability in the pseudomorphic SiGe films, limitations exist in
the application of the binary SiGe alloys. By incorporating smaller-
sized C atoms substitutionally to form Si1−x−y Gex Cy , the strain can
be compensated, extending the Si-based heterostructures to allow more
258 SiGe heterostructure FETs
Figure 7.19. Room temperature IDS –VGS for epitaxial Si, Si0.8 Ge0.2 SiGe and
Si0.793 Ge0.2 C0.007 SiGeC p-HFETs for linear and saturation values of VDS for
10 × 10 µm devices. Inset shows IDS versus VDS for increasing values of VGS –VT .
The curves have been normalized for oxide thickness variations between the
samples. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)
flexible device design [31, 32]. The ternary alloys are promising for p-
channel HFETs, since the addition of C increases the stability of the
material and reduces the amount of process-induced strain relaxation
[33, 34].
Figure 7.19 shows the normalized room temperature characteristics of
10 µm gate length Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 , and control Si transistors
with the same doping. The respective subthreshold slopes are 101, 90 and
75 mV dec−1 for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007 and control Si devices. All
devices exhibit good saturation and turn-off characteristics. However, the
Si0.793 Ge0.2 C0.007 transistor exhibits a higher drive current at the same
effective gate voltage, as shown in the inset.
In figure 7.20, the field-effect mobilities for Si0.8 Ge0.2 , Si0.793 Ge0.2 C0.007
epitaxial Si and lightly-doped bulk Czochralski–Si (CZ–Si) p-MOS are plot-
ted at room and liquid nitrogen temperatures. The peak mobility at 300 K
is enhanced to 190 cm2 V−1 s−1 for Si0.793 Ge0.2 C0.007 in comparison to
140 cm2 V−1 s−1 for the Si0.8 Ge0.2 devices. The ternary alloy sample
Devices using poly-SiGe 259
Figure 7.20. Linear field-effect mobility (µFE ) for 1.3 × 1015 cm−3 doped
bulk-Si, 2.3 × 1017 cm−3 doped epitaxial Si/Si0.8 Ge0.2 and Si0.793 Ge0.2 C0.007
SiGeC p-HFETs as a function of VGS –VT for 10 × 10 µm devices at room
temperature and 77 K. (After John S et al 1999 Appl. Phys. Lett. 74 847–9.)
shows the highest peak mobility, whereas the mobility for the Si0.8 Ge0.2
devices is only slightly higher than that of epitaxial Si and lower than that
of a bulk doped CZ–Si device. It is known that the in-plane hole mobility
in compressively strained Si1−x Gex is enhanced due to the lifting of valence
band degeneracy and modification of the band structure.
Although performance enhancement has been demonstrated in
partially strain-compensated Si1−x−y Gex Cy channel p-HFETs over
Si1−x Gex channels as a result of less process-induced relaxation in the
Si1−x−y Gex Cy layer, complete strain compensation of the SiGe layers,
however, degrades the performance of p-HFET devices. The incorporation
of a controlled amount of C can provide a wider process window for device
fabrication.
Poly-Si0:75 Ge0:25 -gated p-MOS transistors with a very thin gate oxide
have been fabricated. In addition to reduced gate-depletion effect (GDE)
and reduced boron penetration, an enhancement in performance has been
reported [37]. As a p+ -poly-SiGe film has a tunable work function; the
carrier mobility which is affected by the vertical electric field differs from
that in the device with a conventional polySi gate [38]. Due its superior hole
mobility and smaller work function, which leads to a lower effective field
in the inversion layer, an improved current drive is obtained for poly-SiGe.
The output characteristics for both p+ -polySi and poly-SiGe gate devices
with various gate biases are shown in figure 7.21. For each gate voltage,
the drain current of the poly-SiGe gated device is higher than that of the
polySi gated device. Given its compatibility with current VLSI fabrication
processes, incorporating SiGe into existing CMOS processing should be
relatively easy and should lead to higher performance of MOSFET devices
[37]. The gate tunnelling currents (hole and electron) in p+ -polySi and
poly-SiGe gated p-MOS transistors with ultrathin gate oxides of 25 and
29 Å have been measured by employing the charge-separation measurement
techniques [39]. The authors have concluded that the hole direct tunnelling
is the dominant gate leakage mechanism under normal operating conditions
for p+ -polySi gated p-MOS devices with very thin gate oxide.
Devices using poly-SiGe 261
Figure 7.21. IDS –VDS characteristics for both p+ -polySi and poly-SiGe gated
devices with various gate biases. For the same VDS and VGS , the drain current of
the poly-SiGe gated device is always higher than that of the polySi gated device.
(After Lee W-C et al 1999 IEEE Electron Device Lett. 20 232–4.)
the gate influence on the effective barrier height seen by the carriers play
an important role in the device operation. It consists of a source layer,
a graded SiGe source layer, a lightly-doped SiGe source layer, an n-type
doped channel region and finally a p-type doped drain layer (as shown in
figure 7.23). The gate dielectrics consists of an oxide grown on the vertical
sidewalls and the gate electrode is an in situ doped p-type polysilicon layer.
The basic principle of operation of this novel device is: in the on-
state, the barrier is decreased by using the gate action on the lightly-doped
source layer. In the case of a p-channel device, a strained-SiGe layer on
top of an Si substrate is used to create a barrier for the holes [21]. For the
n-channel devices, the barrier for the electrons will be formed by a strained-
Si source layer on top of a SiGe buffer layer, leading to a band alignment
of type II [21]. In that case, SiGe will also be used for the channel and
drain layers. Using the Si/SiGe layer stack for both p- and n-MOSFETs,
it is possible to include source engineering in the vertical transistor design.
This is an important improvement to vertical Si-only devices, which lack the
possibility of channel engineering that has pushed their planar counterparts
toward the deep submicron regime. Vertical MOSFETs suffer from drain-
induced barrier lowering (DIBL), causing reduction threshold voltage roll-
off and an increase in subthreshold slope. By using ultrathin pillars (width
100 nm), the channel region can be fully depleted by surrounding gates,
resulting in an improved subthreshold slope and a suppression of short-
channel effects [47, 48]. To reduce the DIBL effect, a material-dependent
barrier between source and channel may also be introduced [45, 49].
Enhanced in-plane hole mobility in strained-SiGe alloys, compared to
bulk-Si has been employed for the fabrication of planar SiGe-channel p-
HFETs [5, 14, 50]. The enhancement of hole mobility in a direction normal
to the growth plane of the strained-Si1−x Gex and graded SiGe channel has
also been found to be effective in the enhancement of the drive current
in implanted-channel MOSFETs. As the vertical structures combine the
merits of a very short channel and enhanced hole mobility in strained-SiGe
layers, the results are very promising in terms of the possibilities offered
by the SiGe technology. Indeed, a deep submicron vertical SiGe-channel
p-HFET using strained-Si1−x Gex grown using solid phase epitaxy and the
standard CMOS process has been reported [46].
The scaling of vertical p-MOSFETs with the source and drain doped
with boron during low-temperature epitaxy is limited by the diffusion
of boron during subsequent side wall gate oxidation. By introducing
SiGeC diffusion barrier layers, boron diffusion from source and drain into
the channel region has been suppressed during the gate oxidation. The
characteristics of scaled vertical p-MOSFETs down to 25 nm in channel
length [51] are shown in figure 7.24. These devices suffer from the onset of
punch-through, but the gate can still control the drain current in the linear
region.
Noise in p-HFETs 265
Figure 7.24. (a) Output I–V and (b) subthreshold drain current versus gate
voltage for devices with L = 25 nm with a gate oxide thickness of 10 nm. (After
Yang M et al 1999 IEEE Electron Device Lett. 20 301–3.)
Figure 7.25. Spectral density of the input-referred gate voltage noise for the
flat Ge 20% and the Si p-MOSFET in saturation. (After Mathew S J et al 1999
IEEE Electron Device Lett. 20 173–5.)
been given to the noise properties of SiGe p-HFETs [29, 53]. The noise
in MOSFETs is generally related to the fluctuations in the inversion layer
carrier density due to traps located at the Si–SiO2 interface. SiGe p-HFETs
are bandgap-engineered such that the holes confined to the SiGe channel
are physically separated from the Si–oxide interface by an Si-cap layer.
Intuitively, one would expect lower noise in SiGe p-HFETs because of such
a physical separation. However, an examination of the trapping-based noise
theory [54] shows that this separation changes only the frequency range over
which the noise shows a dependence, but not the magnitude of the noise.
Figure 7.25 shows the input referred gate voltage noise for Si/SiGe
p-HFETs on SOS and bulk-Si. It is observed that all SiGe p-HFETs
consistently show a lower noise than Si p-MOSFETs at all gate biases.
The SiGe p-HFETs show a 70% lower noise than the Si p-MOSFETs, due
to the enlarged separation between the hole quasi-Fermi level and valence
band edge, which results in the sampling of a lower density of traps. Thus,
the SiGe p-HFETs should have an intrinsic advantage in microwave circuit
applications.
Collaert et al [55] have measured the low-frequency noise
characteristics for several vertical SiGe-channel HFETs. Figures 7.26(a)–
7.26(d) show the noise spectra measured between 3 Hz and 100 KHz for
devices with source top and drain top configurations at constant drain
current. As can be seen from the figures, the source top configuration
exhibits a dominant generation–recombination (g–r) noise behaviour while
the drain top measurements show 1/f γ -type noise behaviour with γ
between 0.9 and 1.5.
Summary 267
Figure 7.26. Low-frequency noise characteristics for (a) an Si0.90 Ge0.10 device;
(b) an Si0.80 Ge0.20 device, Nsub = 5 × 1017 cm−3 ; (c) an Si0.90 Ge0.10 device; and
(d) a bulk-Si device, Nsub = 1 × 1018 cm−3 . (After Collaert N et al 1999 Proc.
ESSDERC pp 308–11.)
7.8. SUMMARY
valence band discontinuity can be obtained at the top of the SiGe channel
leading to an increase in transconductance for a given integrated Ge dose.
It has been shown that for maximum utilization of the strained-Si1−x Gex
quantum well, the p-HFET should have the following characteristics:
BIBLIOGRAPHY
[1] Davari B 1996 CMOS technology scaling, 0.1 µm and beyond IEEE IEDM
Tech. Dig. pp 555–8
[2] Bouillon P, Skotnicki T, Kelaidis C, Gwoziecki R, Dollfus P, Regolini J-L,
Sagnes I and Bodnar S 1996 Search for the optimal channel architecture
for 0.18/0.12 µm bulk CMOS experimental study IEEE IEDM Tech. Dig.
pp 559–62
[3] Kesan V P, Subbanna S, Restle P J, Tejwani M J, Aitken J M, Iyer S S
and Ott J A 1991 High performance 0.25 µm p-MOSFETs with silicon–
germanium channels for 300 K and 77 K operation IEEE IEDM Tech.
Dig. pp 25–8
[4] Nayak D K, Woo J C S, Park J S, Wang K L and MacWilliams K P 1991
Enhancement-mode quantum-well Gex Si1−x PMOS IEEE Electron Device
Lett. 12 154–6
[5] Verdonckt-Vandebroek S, Crabbe F, Meyerson B S, Harame D L, Restle P J,
Stork J M C and Johnson J B 1994 SiGe-channel heterojunction p-
MOSFETs IEEE Trans. Electron Devices 41 90–102
[6] Li P W, Yang E S, Yang Y F, Chu J O and Meyerson B S 1994 SiGe
pMOSFETs with gate oxide fabricated by microwave electron cyclotron
resonance plasma processing IEEE Electron Device Lett. 15 402–5
[7] Nayak D K, Woo J C S, Yabiku G K, MacWilliams K P, Park J S and
Wang K L 1993 High mobility GeSi PMOS on SIMOX IEEE Electron
Device Lett. 14 520–2
Bibliography 269
METALLIZATION AND
HETEROSTRUCTURE SCHOTTKY
DIODES
272
Metallization and heterostructure Schottky diodes 273
Property Al Au Pt Ni Cr
Molecular weight (amu) 26.98 196.96 195.09 58.69 52.02
Density (g cm−3 ) 2.699 19.288 21.452 8.903 7.19
◦
Melting point ( C) 659.4 1062.2 1768 1454 1875
does not does not does not
Oxidation potential (V) 1.66 0.25
oxidize oxidize oxidize
Work function
4.25 5.1 5.7 5.1 4.5
at vacuum (eV)
Schottky barrier
0.69 0.79 0.9 0.61 0.61
to n-Si (eV)
Schottky barrier
0.38 0.25 0.51 0.50
to p-Si (eV)
Schottky barrier
0.48 0.59 0.49
to n-Ge (eV)
Schottky barrier
0.3
to p-Ge (eV)
A 350 ◦ C anneal for 1 h was used to alloy the capping Si and Ge layers
into the Al. Contact resistivity measurements between room temperature
and 400 ◦ C demonstrated the stability of the contacts. However, the room
temperature contact resistivity of 0.01 Ω cm−2 was considered too high for
device applications.
The second approach to contact formation involved deposition of a
layer of Pd:Si (3:1, 600 Å) on the SiGe, followed by a layer of pure Ge
(1000 Å). The contacts were annealed for 1 h at 350 ◦ C. During annealing
the Pd3 Si phase was formed. Concurrently, the surface Ge layer diffused
through the silicide and grew epitaxially on the underlying SiGe layer.
Contact resistances for these films were typically 5 × 10−4 Ω cm−2 at room
temperature.
Liou et al [2] reported the interfacial reactions of Pt and Pd with
epitaxial Si1−x Gex alloys and the effects of these reactions on Schottky
barrier height. They reported that the barrier heights of Pd and Pt
on n-Si0.8 Ge0.2 were the same, about 0.68 eV, and were not modified
significantly when annealed at a temperature below 550 ◦ C. This value is
close to that previously reported by Buxbaum et al [3] for Pd on n-Si1−x Gex
films.
Kanaya et al [4] reported the Schottky barrier height of Pd(Pt)/p-SiGe
contacts for infrared detection. It was shown that the barrier height
274 Metallization and heterostructure Schottky diodes
More than half of the elements in the periodic table react with silicon to
form one or more intermetallic compounds (silicides). In Si technology,
uniform and stable contacts are achieved by reacting metal films with Si
until the most Si-rich silicides are formed. These silicides not only offer a
choice in electrical barrier heights but also serve as protective layers against
oxidation. Al is commonly used as the ohmic contact metal in Si technology.
The solid solubility of Si at 525 ◦ C is 1.5% and Si molecules from the
substrate dissolve into Al to satisfy its solubility. Though Al and Al–Si
have been successfully used in Si devices, they do not make good contacts to
group IV alloy films. The choice of metals for ohmic contacts should satisfy
several requirements. Firstly, the composition of the unreacted alloys must
remain unchanged after contact reactions. Secondly, a single compound,
not a mixture of compounds (e.g., silicides and germanides), should be in
contact with the alloy films. Thirdly, the consumption of alloy films during
the reaction must be small since the thicknesses of the strained layers are
limited by the critical thickness.
Silicidation of group IV alloy films 277
the pinning position of the Fermi level [7]. In Si, reproducible rectifying
and low resistance ohmic contacts can be achieved by choosing appropriate
transition metals with various Schottky barrier heights and by doping the
semiconductor with the desired level. Transition metals react with Si
at low temperature so that no liquid phase forms. As a result, uniform
silicide layers with reproducible compositions at the silicide/Si interface
are formed. The electrical properties of Schottky junctions require the
understanding of chemical reactions at the metal–semiconductor interface.
In the following, we discuss the formation and characterization of silicides
of various group IV alloy films with Ti, Pt and Pd.
Figure 8.2. The 2.551 MeV 4 He++ backscattering spectra of the TiSi/Si sample
annealed at 600 ◦ C for 20 min: (· · · · · ·) experimental and (——) simulation.
280 Metallization and heterostructure Schottky diodes
4
He+2 ion beam. The scattered He+2 from the TiSi2 layer appears at
higher energies (channel nos 576–541) while those from the Si substrate
appear at lower energies (channel nos 445–100). Computer simulation of
the backscattered spectra (using the GISA-3.95 program) is usually done
to obtain the thickness and composition of different layers.
Figure 8.3 shows the RBS spectrum for a Ti/SiGe sample annealed
at 600 ◦ C. It is evident from figure 8.3 that the scattered He+2 from Ge
appears at a higher energy (channel nos 643–591) and the scattered atoms
from Ti and Si appear at relatively lower energies (channel nos 576–543
and 445–200, respectively). From the simulation, it is found that the total
Ti signal is contributed partly from the TiSi layer and a part from the
unreacted Ti. Similarly, the Si fraction is contributed partly from the
TiSi layer and partly from the SiGe epitaxial layer as well as from the Si
substrate.
Silicidation with titanium 281
where Z is the atomic number of the atom and ξ is the work function
of the surface. The third term on the right-hand side of equation (8.1)
has an extra component ∆ which is included to take account of the fact
Silicidation with titanium 283
that the atom is in a charged state when the final electron is ejected.
Experimentally, ∆ is found to have a value between 12 and 32 .
In sputter depth profiling analysis of thin films, an ion beam is used
to etch the surface at rates up to 2 µm h−1 . For AES depth profiles, the
electron beam is placed in the middle of the ion beam crater and, if the
system alignment is suitable, the crater size may be limited to 100 µm or
less. If a monoenergetic argon ion of current density Ji is used to sputter
a target with a sputtering yield of S atoms per ion, the rate of removal is
given by
dz Ji SM
= (8.2)
dt qρNA na
where M is molecular weight of the material with na atoms per molecule,
q is electronic charge, ρ is density and NA is Avogadro’s number. In the
above equation, dz/dt is the sputter rate. Thus, for a given material, the
removal rate may be determined if Ji and S are known.
Figure 8.6 shows typical AES depth profiles for Ti, Si and Ge of the
Ti/Si/Si1−x Gex sample having a Ti thickness of 700 Å annealed at 600 ◦ C
for 20 min. The spot size of the beam was 0.5 µm and the etch rate for
profiling was 5 Å min−1 . As seen from the depth profile, about 600 Å of Ti
remains unreacted and only 100 Å of Ti takes part in silicide formation. It is
clear from the profile that TiSi formation is observed up to a depth of about
100 Å below the interface. An accumulation of Ge atoms is also observed
below the interfacial region. It is desirable to consume the sacrificial Si-cap
layer completely by Ti to obtain a pure TiSi/Si1−x Gex interface.
Figure 8.6. AES depth profiles of Ti, Si and Ge for the TiSi/Si0.81 Ge0.19 sample
annealed at 600 ◦ C for 20 min.
284 Metallization and heterostructure Schottky diodes
Figure 8.7. Sheet resistance versus annealing temperature curves for the
Ti/Si1−x Gex and Ti/Ge samples. (After Lai J B and Chen L J 1999 J. Appl.
Phys. 86 1340–5.)
Silicidation using Pt and Pd 285
Pd2 Si or Pd2 Ge with a measured plane symmetry of 5.5 Å. There is also
a report of strain relaxation in the underlying Si1−x Gex layer due to high-
temperature annealing of Pd at about 550 ◦ C [25,26]. In these compounds,
a decrease in the vertical lattice parameter has been observed. Annealing
of Pd–Si1−x Gex at about 550 ◦ C results in the formation of a double layer
structure: the top layer contains a relatively small amount of Ge and the
adjacent Si1−x Gex layer is enriched with Ge. Hong et al [5] have studied
Pt/SiGe systems and have observed the formation of PtGe2 at annealing
temperatures beyond 450 ◦ C.
XRD spectra for the SiGe sample annealed at 400 ◦ C for 30 min
containing 19% Ge and a 50 Å Si sacrificial layer are shown in figure 8.9.
The resulting silicide peaks are oriented along the (200), (021), (1̄15) and
(222) directions. Figure 8.10 shows the XRD pattern of the SiGe sample
with 29% Ge and a 50 Å thick cap layer. As seen in figure 8.10, the PtSi
peak is oriented in the (200), (2̄22) and (1̄15) directions along with the
Figure 8.9. XRD spectrum for PtSi/Si0.81 Ge0.19 film annealed at 400 ◦ C for
20 min.
Heterostructure Schottky diodes 287
Figure 8.10. XRD spectrum for PtSi/Si0.71 Ge0.29 film annealed at 400 ◦ C for
20 min.
peak arising from the Si(400) plane. It is observed from x-ray analysis that
there is no evidence of germanide formation.
and
−qφb
po = Nv exp (8.6)
kT
where k is the Boltzmann constant and Nv is the effective density of state
in the valence band.
Assuming thermionic emission as the main mechanism of current flow
across a Schottky junction, the barrier height can be calculated using the
relation
kT AA∗ T 2
φb = ln (8.7)
q I0
where A∗ is the effective Richardson constant, A is the area of the diode
and I0 is the saturation current. The ideality factor, m, is obtained from
the relation [28]
q ∂v
m= (8.8)
kT ∂ (ln I)
Heterostructure Schottky diodes 289
∂v
where ∂(ln I) is the slope of the linear extrapolated part of the current–
voltage characteristics.
The barrier height of a Schottky junction can also be determined from
the measured reverse capacitance value. The determination of the Schottky
barrier height by the capacitance–voltage method is based upon the voltage
dependence of the charge in depletion region of the diode. Capacitance per
unit area of a reverse biased Schottky junction is expressed as [27]
qs Na s
CD = = (8.9)
2(Vbi − V − kT /q) W
diode will be a straight line. From the intercept on the voltage axis, the
barrier height is determined from the relation
kT
φb = Vi + ψp + (8.10)
q
where Vi is the voltage intercept and ψp is the potential difference between
the hole quasi-Fermi level and the top of the valence band, which can be
computed from the doping concentration and is given by
kT Nv
ψp = ln . (8.11)
q Na
averages over the whole sample area and measures the mean barrier
height. Using the C–V technique, the energy distribution of the interface
state density at a metal–semiconductor interface has been measured by
Chattopadhyay et al [29].
as the thickness of the SiGe layer is small (limited by the critical layer
thickness) to retain the strain in the epitaxial layer. Moreover, the layers
get unintentionally doped during film growth in an MBE system. As the
valence band discontinuity is in close proximity to the Schottky junction,
the total effective barrier can be changed by changing the applied reverse
bias. The sensitivity of the barrier height change can be controlled by
changing the SiGe layer thickness. As a result, the barrier height decreases
with the applied reverse bias [30].
Room temperature experimental and simulated forward current–
voltage characteristics of PtSi/Si1−x Gex (x = 0.19 and x = 0.29) Schottky
diodes are shown in figure 8.14 [31]. For simulation of forward current–
voltage characteristics, thermionic emission, image force lowering and
thermionic field emission models were considered. Since the existence of a
thin interfacial layer (typically a few atomic layers) between the Schottky
contact and the semiconductor affects the current–voltage characteristics
significantly, interfacial layers of a thickness of 8 Å and 10 Å were included
in the simulation of the current–voltage characteristics of PtSi/Si0.81 Ge0.19
and PtSi/Si0.71 Ge0.29 Schottky diodes, respectively. The interfacial layer
was assumed to be transparent to the carriers, so that they tunnel through
it without any reflection, but able to withstand a potential drop across
it. Associated series resistances were computed to be 12.2 Ω cm−2 and
0.70 Ω cm−2 , respectively. Fermi level pinning was also incorporated in
the model. To fit the experimental current–voltage characteristics, the
interface state density for both the diodes was taken to be the same,
1 × 1012 cm−2 eV−1 . The simulated current–voltage characteristics agree
well with the experimental data for both the heterostructure Schottky
diodes, as shown in figure 8.14.
2
Figure 8.19. Plots of 1/CD versus applied reverse bias at room temperature for
(a) TiSi/Si0.81 Ge0.19 and (b) TiSi/Si0.71 Ge0.29 Schottky diodes.
Table 8.2. Schottky barrier height and ideality factor of group IV alloy layers
with Pt, Pd and Ti.
Parameter Film Si0.71 Ge0.29 Si0.79 Ge0.20 C0.01
with Si-cap with Si-cap
Metal Pt Pd Ti Pt Pd Ti
Ideality 300 K 1.15 1.12 1.03 1.11 1.20 1.20
factor (n) 100 K 1.32 1.52 1.53 1.48 1.47 1.30
Barrier 300 K 0.52 0.54 0.56 0.56 0.57 0.58
height (eV) 100 K 0.19 0.23 0.27 0.21 0.22 0.23
8.9. SUMMARY
2
Figure 8.28. Plot of 1/CD versus applied reverse bias of Ti/strained-Si Schottky
diode at room temperature.
BIBLIOGRAPHY
[36] People R 1986 Physics and applications of Gex Si1−x /Si strained layer
heterostructures IEEE J. Quantum Electron. 22 1696–710
[37] Tung R T 1992 Electron transport at metal–semiconductor interfaces:
general theory Phys. Rev. B 45 13 509–23
[38] Tung R T 1993 Schottky barrier height—do we really understand what we
measure? J. Vac. Sci. Technol. B 11 1546–52
[39] Schneider M V, Cho A Y, Kollberg E and Zirath H 1983 Characteristics of
Schottky diodes with microcluster interface Appl. Phys. Lett. 43 558–60
[40] Maiti C K and Chattopadhyay S unpublished data
[41] Green M A and Shewchun J 1973 Minority carrier effects upon the small-
signal and steady-state properties of the Schottky diodes Solid-State
Electron. 16 1141–50
Chapter 9
SIGE OPTOELECTRONIC
DEVICES
310
SiGe optoelectronic devices 311
Table 9.2. ICs for optical fibre communication systems fabricated by using
SiGe HBTs.
chip. This approach combines the high-speed and light emission advantages
of III–V semiconductors and the mature and reliable Si technology. It is
practical and has achieved some success for optoelectronic signal processing
in the last few years [7, 13]. However, the fabrication of hybrid OEICs is
more complicated, expensive and less reliable than monolithic OEICs. Also,
interconnection density and speed in hybrid OEICs are limited.
As applications of SiGe HBTs, various ICs for optical-fibre-link
systems, have been developed (see table 9.2) [14, 15]. These include both
digital ICs of a static frequency divider and a time-division multiplexer
(MUX), demultiplexer (DEMUX) and analogue ICs of a pre-amplifier, an
AGC amplifier core and a decision circuit. A maximum operating frequency
of up to 50 GHz for a 1/8 static frequency divider has been achieved. A
2:1 time-division MUX and a 1:2 DEMUX built from basic circuit core
modules operated at 40 Gb s−1 . In a pre-amplifier with an input stage
consisting of a common base transistor, a bandwidth of 35 GHz was also
achieved. In an AGC amplifier core, a bandwidth of about 32 GHz with a
dynamic range of 19 dB was obtained by using a transimpedance amplifier
as an active load circuit and a peaking capacitor.
Highly porous silicon (PS) has attracted much attention because it
exhibits strong photoluminescence (PL) from the near-infrared to visible
green–blue range by varying the porosity at room temperature [9, 16]. The
external quantum efficiencies of light emission of highly porous silicon can
be as high as 1–10%. There is still a debate in the scientific community
regarding the physics of this phenomenon. The common views of the origin
of light emission are:
given by
hc 1.24
λc = = (9.1)
Eg Eg
where c is the velocity of light. The external quantum efficiency of the
photodiode is defined as the number of electron–hole pairs generated per
incident photon and is given by
Ip /q
η= (9.2)
Popt /hν
where Jdrift and Jdiff are the drift and diffusion components, respectively.
For a p+ –n junction diode, the total current is given by
e−αW Dp
Jtot = qφopt 1 − + qpn0 (9.5)
(1 + αLp ) Lp
Optoelectronic devices in silicon 317
where φopt is the total photon flux, W is the width of the depletion
layer, q is the free electron charge, α is the optical inter-band absorption
coefficient, pn0 is the equilibrium hole density, and Lp and Dp are the
diffusion length and the diffusion constant, respectively, for holes. The last
term in equation (9.5) represents the reverse leakage current (dark current).
When the reverse leakage current is very small, then the quantum efficiency,
η is given by
Ip /q e−αW
η= =1− . (9.6)
Popt /hν 1 + αLp
It is clear that the quantum efficiency is determined mainly by the
absorption coefficient, α, of the semiconductor. In order to maximize η, it
is desirable to make the products αW and αLp as large as possible, i.e.,
the depletion layer must be sufficiently wide to allow a large fraction of
the incident light to be absorbed. On the other hand, the depletion region
must be kept narrow to reduce the transit time for high-speed devices.
The avalanche photodiode is essentially a p–n junction operated in
a reverse bias condition at or above the avalanche breakdown voltage.
Photogenerated carriers in the depletion region travel at their saturation
velocities. When these photogenerated carriers acquire enough energy
from the electric field, impact ionization occurs and results in avalanche
multiplication of the carriers. Therefore, the gain of the APD can be
substantially increased over conventional p–i–n photodiodes, but with
elevated noise inherent to the avalanche process.
(i) When qφb < hν < Eg , i.e., the energy of incident photon flux is higher
than the corresponding Schottky barrier height but smaller than the
bandgap energy of the semiconductor, electrons will be photoexcited
in metal and surmount the barrier by thermionic emission. Emitted
electrons transit through the semiconductor and are collected at the
318 SiGe optoelectronic devices
Figure 9.1. (a) Schematic structure of an MSM photodiode and (b) analysing
area. (After Chattopadhyay S and Maiti C K, unpublished data.)
are responsivity, dark current and capacitance, which are discussed below.
The dark current (which decides the minimum detectable power) of
a photodetector significantly contributes to the noise at the input of an
optical receiver, which in turn plays a crucial role in deciding the sensitivity
of a receiver. Excess carriers responsible for dark current increase the
capacitance and decrease the response speed of a detector. The detector
noise associated with its dark current is a shot noise and its mean square
value is given by
i2d = 2qId ∆f. (9.7)
Furthermore, the minimum optical power required to achieve a
photocurrent equal to the noise current id is usually regarded as the
minimum detectable power of a detector. In an MSM structure, the dark
current is a metal/semiconductor interface phenomenon and is attributed
to thermionic emission of the carriers across the Schottky barriers [37].
Usually, thermionic emission of the carriers across a reverse-biased Schottky
junction accounts for the dark current in MSM photodiodes [38] and the
dark current density is given by
It is noted that a low Schottky barrier height would result in excess carrier
injection in the semiconductor from the cathode and would lead to a large
dark current. It has been proposed that equation (9.8) is valid until the
conduction band profile of an MSM photodiode does not reach the flat band
condition at the forward-biased contact [39]. When the conduction band
at the anode reaches the flat band condition, thermionic emission of holes
across the barrier at anode starts and is accounted for the dark current
which is given by
where A∗ are the respective Richardson constants and ∆φ are the respective
barrier height lowering due to image force. The flatband voltage VFB can
be expressed as [37]
qNd S 2
VFB = (9.10)
2s 0
where S is the electrode spacing and Nd is the donor concentration in the
layer.
The dark capacitance of an MSM photodetector is contributed by the
electrostatic field around the alternatively charged parallel metal fingers.
The speed of an MSM detector is limited by RL C time constant if it is
longer than the transit time or recombination time. Here, RL consists
of the load resistance and series resistance of the metal fingers. The
detector capacitance can be estimated by using a model based on conformal
Optical properties of SiGe and SiGeC films 321
mapping [40]. If W is the finger width and P is the finger pitch (sum of
width and spacing, i.e., P = W +S), the total detector capacitance is given
by
C0 A
Ctotal = (9.11)
P
where A is active area of the detector.
Figure 9.2. Optical absorption coefficients of Si, Ge and undoped SiGe alloys.
322 SiGe optoelectronic devices
data are taken from [41]. It is seen from figure 9.2 that Si is transparent
in the wavelength region 1.20–1.60 µm, while the SiGe absorption edge
shifts towards the red with increasing Ge concentration in the alloy. The
shift offers a means for absorbing 1.3–1.6 µm light, by choosing x > 0.3 for
1.3 µm and x > 0.85 for 1.55 µm. From figure 9.3, it may be noted that
the refractive index increases with the increase in Ge concentration. While
intrinsic Si and Ge are transparent from near-infrared up to 20 µm and
beyond, the optical transmission of group IV alloys is found to reduce by
heavy doping [2]. For unstrained (bulk) SiGe alloys, the absorption data
have been provided by Braunstein et al [42].
Orner et al [43] have measured the optical absorption at phonon
energies near the bandgap of a Ge-rich SiGeC (x ≈ 0.90, y ≤ 0.02) film
by employing Fourier transform infrared (FTIR) spectroscopy. As the film
Optical properties of SiGe and SiGeC films 323
Figure 9.4. Optical absorption coefficient (α) of a Ge-rich Si0.11 Ge0.88 C0.01
film: (a) C is primarily substitutional and (b) C is primarily interstitial. (After
Orner B A et al 1996 Appl. Phys. Lett. 69 2557–9.)
was Ge-rich, their bandgap energies are less than that of Si. Absorption
data and the best fit curves are as shown in figure 9.4. Figure 9.4(b)
shows a comparison between two films with carbon at the interstitial and
substitutional sites. In both cases the infrared absorption edge of the alloy
shifts towards the red.
Figure 9.5 shows the refractive index of the epitaxial Ge1−x Cx as a
function of donor concentration and compares it to Ge epitaxial layers
grown under identical conditions. Introducing carbon into epitaxial Ge
films doped with P decreases the refractive index near the absorption
edge. Figure 9.6 illustrates the absorption coefficient, α, of phosphorus-
324 SiGe optoelectronic devices
Figure 9.5. Refractive index versus donor concentration for Ge1−y Cy and Ge
epitaxial films on Si(100). (After Dashiell M W et al 1998 Thin Solid Films 321
47–50.)
doped Ge1−y Cy films grown epitaxially on Si(100) for α > 100 cm−1 .
The absorption edge experiences a redshift with increasing phosphorus
concentrations for both Ge1−y Cy and Ge films. High-purity Ge data are
also included in the figure. Note that undoped Ge1−y Cy epitaxial layers
exhibit the same absorption coefficient as does intrinsic bulk germanium
for α > 100 cm−1 . Thus, a significant band structure modification was not
observed by optical absorption for these C concentrations.
Figure 9.7. Infrared photoresponse at 77 K of (a) Pd2 Si/Si1−x Gex and (b)
PtSi/Si1−x Gex Schottky barrier detectors. (After Xiao X et al 1993 IEEE
Electron Device Lett. 14 199–201.)
Optical devices using SiGe alloys 327
Figure 9.12. Energy band diagram showing the shift of the absorption edges in a
symmetrically strained-Si1−x Gex /Si multiple quantum wells (MQWs). Electrons
are confined in the wider bandgap of Si layers and holes are confined in the
narrower bandgap of Si1−x Gex layers. E1 and HH1 are the minimum electron
and hole energy levels in the quantum wells. L is the width of the quantum well.
by taking into account the different buffer layer thicknesses and Ge content
in the structures.
A monolithic SiGe/Si p–i–n HBT front-end transimpedance
photoreceiver circuit, as shown in figure 9.13, has been fabricated by Rieh et
al [76]. Figure 9.13 shows the circuit diagram with a transimpedance
amplifier which consists of a photodiode, common-emitter gain stages, two
emitter follower buffers and a resistive feedback loop. For fabrication, a
mesa-type SiGe/Si p–i–n HBT technology was used. Fabricated HBTs
showed an fmax of 34 GHz with dc gain of 25. SiGe/Si p–i–n photodiodes,
which share base and collector layers of HBTs, demonstrated a responsivity
of 0.3 A W−1 at λ = 850 nm (incident optical power of 22 mW) at
a reverse bias of 5 V, and steadily increased as the reverse bias was
increased. The corresponding external quantum efficiency was 43%. The
bandwidth of the photodiode was about 450 MHz (see figure 9.14(a)).
The frequency response of the monolithically integrated single-feedback
p–i–n HBT photoreceiver, excited with λ = 850 nm light, is shown in
figure 9.14(b) and exhibited a bandwidth of about 460 MHz, which is
limited by the bandwidth of p–i–n photodiode.
The integration of Ge photodetectors on silicon substrates is
also advantageous for various Si-based optoelectronics applications [77].
Figure 9.15 shows the schematic diagram of an integrated p–n mesa
Optical devices using SiGe alloys 333
Figure 9.14. (a) Measured frequency response of the SiGe p–i–n photodiode
and (b) measured frequency response of the SiGe photoreceiver. The solid curves
show the fit to the measured response. (After Rieh J-S et al 1997 IEEE Photonics
Technol. Lett. 10 415–7.)
334 SiGe optoelectronic devices
Figure 9.15. A schematic diagram showing the optimized relaxed graded buffer
growth sequence with the Ge mesa photodiode on top. (After Samavedam S B et
al 1998 Appl. Phys. Lett. 73 2125–7.)
external quantum efficiencies were less than 1%. These results show that
Ge-rich SiGeC diodes have a higher photoresponse to 1.3 µm excitation
than Si-rich SiGeC diodes, because of the narrower bandgap of Ge-rich
SiGeC, and hence the larger absorption coefficient at a 1.3 µm wavelength.
It was observed that the C blueshifted the photoresponse edge from the
spectral response, suggesting that carbon increased the bandgap of the Ge-
rich SiGeC alloys. This is consistent with the decrease of quantum efficiency
with the increase of carbon composition in p-GeC/n-Si photodiodes, which
agrees with the absorption studies [43]. However, SiGe and/or SiGeC MSM
photodiodes operating in the near-infrared or infrared wavelength region
have not yet been explored.
p–n heterojunction photodiodes on epitaxial p-type Ge1−x Cx films
with carbon percentages of 0.2, 0.8, 1.4 and 2% on n-Si substrates
have also been studied. Photoresponse characteristics of the diodes are
shown in figure 9.16. The photocurrents of the p-Ge0.992 C0.008 /n-Si, p-
Ge0.986 C0.014 /n-Si, and p-Ge0.98 C0.02 /n-Si photodiodes under an applied
reverse bias of −20 V are 4.4, 4.0 and 2.6 µA, respectively, corresponding
to external quantum efficiencies of 2.2%, 2% and 1.3%, respectively, for an
incident power of 192 µW. The measured external quantum efficiencies at
λ = 1.3 µm for different diodes are shown in figure 9.17. For the purposes
of ηext comparison, data of a p–i–n diode using SiGeC films are shown.
The initial photon flux can be calculated from the incident optical power
density and from the wavelength as
Popt
φopt = (9.15)
hν
where h is Planck’s constant and ν is the optical frequency.
The generation rate of photo carriers can be expressed as
dφ
Gopt = − = αφ (9.16)
dy
where dy is the differential distance along the direction of propagation of the
incident beam and α is the absorption coefficient. The quantum efficiency, η
is calculated from the equivalent beam current at unity quantum efficiency
[83] and is given by
Ia
η= (9.17)
Ieq
where Ia is the p–i–n diode terminal current and Ieq is the equivalent
beam current at unity quantum efficiency. The responsivity is the ratio of
photocurrent and incident optical power and is obtained from the external
quantum efficiency. The diode capacitance can be computed from small-
signal ac analysis using y-parameters in a similar manner to that described
in chapter 4.
Figure 9.19. (a) Schematic structure of Si0.7 Ge0.3 p–i–n diode; (b) computed
band diagram; (c) doping profile; (d) electric field; and (e) optical generation.
(After Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)
Figure 9.21. Dark current versus reverse voltage characteristics of Si1−x Gex
p–i–n photodiodes: (a) x = 0; (b) x = 0.2; (c) x = 0.3. (After Chattopadhyay S et
al 1999 Solid-State Electron. 43 1741–5.)
Figure 9.22. Computed spectral response of Si1−x Gex p–i–n photodiodes for:
(a) x = 0; (b) x = 0.1; (c) x = 0.2; (d) x = 0.3; (e) x = 0.5; (f ) x = 0.75. (After
Chattopadhyay S et al 1999 Solid-State Electron. 43 1741–5.)
Figure 9.21 shows the dark currents in three photodiodes (Si, Si0.8 Ge0.2
and Si0.7 Ge0.3 ) of identical geometry with a 1 µm thick intrinsic layer. It
is seen from figure 9.21 that the dark current increases as the Ge mole
fraction is increased. This is attributed to the decrease of bandgap due to
the increase in Ge content in the intrinsic layer. For a 30% Ge content in
the i-layer, the value of the dark current is in the nA range and saturates
at a reverse bias of about 3 V or above.
Figure 9.22 shows the computed responsivities of Si1−x Gex
photodiodes of different Ge concentrations (x = 0.0, 0.1, 0.2, 0.3, 0.5 and
0.75) as a function of wavelength (0.6–1.5 µm). It is seen from figure 9.22
that the cut-off wavelength of the photoresponse curves increases as Ge
content in the absorbing i-layer increases. It is observed that the cut-off
wavelengths for x = 0.0 (i.e., for Si) and for x = 0.75 are about 1.10 µm
and 1.50 µm, respectively. This is due to the fact that, as the Ge content
Simulation of optoelectronic devices 343
is increased in the i-layer, the bandgap decreases which in turn extends the
absorption tail towards the higher wavelength region.
The reported experimental value of the photoresponse for Si1−x Gex
p–i–n photodiodes (x = 0.08–0.69) in this wavelength range is about
0.4–0.5 A W−1 [87, 88] and is compared with simulation results in
figure 9.23 for x = 0.1 and 0.3. The agreement is found to be very
good. Photoresponse characteristics of a constant Ge content (x = 0.30)
photodiode as a function of i-layer thickness (1.0, 1.5, 2.0 and 2.5 µm) are
shown in figure 9.24 in the wavelength range of 0.6–1.4 µm. It is seen that,
for a particular wavelength of the incident photon, responsivity increases
with the thickness of i-layer. This is obvious because as the i-layer thickness
increases, more incident photons get absorbed in the thicker i-layer region
which in turn generates more photo-carriers.
344 SiGe optoelectronic devices
Figure 9.25. Variation of capacitance with applied reverse bias of an Si0.7 Ge0.3
p–i–n diode for: (a) W = 1.0 µm; (b) W = 1.2 µm; (c) W = 1.5 µm and
(d) W = 2.0 µm. (After Chattopadhyay S et al 1999 Solid-State Electron. 43
1741–5.)
Figure 9.26. Variation of capacitance with applied reverse bias of an Si1−x Gex
p–i–n diode for: (a) x = 0.1; (b) x = 0.2 and (c) x = 0.3. (After
Chattopadhyay S et al Solid-State Electron. 43 1741–5.)
Figure 9.27. Computed capacitance versus applied voltage for (a) Si and (b)
Si0.80 Ge0.20 MSM photodetectors. Detectors have an active area of 500 × 500 µm
with 1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S and
Maiti C K, unpublished data.)
Computed dark and photo currents for Si, Si0.80 Ge0.20 and Si0.70 Ge0.30
MSM-PDs are shown in figure 9.28. The dark current I–V characteristics
are typical for a back-to-back Schottky contact. The Si0.80 Ge0.20 MSM-PDs
have higher dark current compared to Si, increasing with the increase in
Ge concentration in the Si1−x Gex epitaxial layer. Si has a dark current of
15 µA at 8 V and Si1−x Gex has a dark current of 60 µA (x = 0.2) and
95 µA (x = 0.3) at 6 V.
Figure 9.29 shows the plot of computed responsivities of an Si
MSM-PD in the wavelength range 0.4–1.20 µm for different voltages (1, 3
and 5 V). An active area of 500 Kc ×500 µm, a finger spacing of 2 µm and
a finger width of 1.5 µm were simulated. It is seen that the photoresponses
are strongly dependent on applied reverse bias. It is expected that the
cut-off wavelength of an Si MSM-PD will correspond to its bandgap energy.
Figure 9.30 shows the plot of computed responsivities of an Si1−x Gex MSM-
PD in the wavelength range 0.4–1.40 µm, for different values of x (0.10, 0.20
and 0.30) at 3 V. As shown in figure 9.30, the responsivity drops rapidly
348 SiGe optoelectronic devices
Figure 9.28. Dark and photo currents versus applied voltage of Si and Si1−x Gex
MSM photodetectors. The detectors have an active area of 500 × 500 µm with
1.5 µm finger width and 2 µm finger spacing. (After Chattopadhyay S and
Maiti C K, unpublished data.)
fingers. Figure 9.32 shows the responsivity variation of an Si0.8 Ge0.2 MSM-
PD with different thicknesses of top absorbing layer. It is seen that the
responsivity increases as the top absorbing layer thickness under the metal
fingers increases. This is expected because a thicker layer will absorb more
photons, which in turn increases the photocurrents.
The Si1−x Gex MSM-PDs have a dark current which increases with the
increase in Ge concentration. Si has a dark current of 10 µA at 6 V and
Si1−x Gex has dark currents of 60 µA (x = 0.2) and 90 µA (x = 0.3, not
shown in figure 9.32) at 6 V. Si MSM-PDs have a peak photoresponsivity
of 0.60 A W−1 at 0.72 µm at an applied voltage 5 V. Si0.80 Ge0.20 PDs
have peak responsivities of 0.76 A W−1 at 0.80 µm at an applied voltage
of 3 V while Si0.70 Ge0.30 MSM-PDs have the responsivity of 0.88 A W−1
350 SiGe optoelectronic devices
9.6. SUMMARY
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RF APPLICATIONS OF SIGE
HBTS
359
360 RF applications of SiGe HBTs
As of 2000, SiGe-based HBTs exhibiting fT and fmax values above 100 GHz
(values which are 50% higher than the best Si BJTs, but some two to six
times lower than the best GaAs devices). Only five years previously, many
applications such as optical networks and wireless RF technology in the
1–20 GHz range, which had been difficult to achieve with conventional
CMOS and bipolar technologies, were demonstrated with SiGe HBT
technology, as evidenced by reports of circuits for 20 Gb s−1 optical
networks [13] and RF wireless circuits up to 24 GHz [14–17]. At that
time, the availability of SiGe BiCMOS technology [18], with both very
high-performance HBTs with fmax of 60 GHz and 0.25 µm Leff CMOS for
logic and memory, offered the possibility of combining analogue and digital
components on the same chip in a new ‘single chip’ architecture.
The first evidence that SiGe HBT technology can successfully compete
with GaAs technology in the rapidly emerging wireless communication
market, with comparable performance in high volume production, was first
demonstrated by Harame et al [19] using a commercial UHVCVD system
for SiGe film growth. Within five years, this technology has matured to
a volume production, very high-performance SiGe BiCMOS process [20]
which can be tailored for low-voltage, low-power RF and mixed-signal
applications. The utilization of SiGe has modified the original market
split between silicon and GaAs technology and allows for a silicon-based
technology to address existing wireless communication market applications,
as well as future requirements in the 5700–5800 MHz ISM band.
The figures-of-merit that apply to SiGe HBTs for use in wireless
communication ICs are:
Circuit type
Performance Year Process
D/A converter
12-bit, 1.2 Gbits s−1 , 750 mW 1994 ADI/IBM
Frequency divider
Divide-by-128, 6.4–23 GHz, 1.5W 1995 NORTEL/IBM
Divide-by-8, up to 50 GHz, 226 mW FF−1 , 5.5 V 1998 Hitachi
Return-to-zero comparator
5 GHz, 1.5 V, 89 mW 1995 NORTEL/IBM
Monolithic VCO
12 GHz, l9 dBm, 5% tuning, −80 dBc phase noise 1996 Hughes/IBM
17 GHz, −110 dBc, on-chip LC resonator 1997 IBM
Active mixer
12 GHz, >0 dB gain @ +3 dBm LO 1996 Hughes/IBM
LNA
2.4 GHz, 10.5 dB gain, 0.95 dB NF 1996 NORTEL/IBM
PCS CDMA, 12 dB gain, 13 dB NF, 3 V/5 mA, 1999 IBM
IIP3 > +10 dBm
DECT, 1.8 GHz, 20 dB gain, 1.8 dB NF 1998 TEMIC
Broadband amplifier
8 dB gain, 17 GHz BW, 16.8 mA @ 2.5 V 1996 NORTEL/IBM
35 GHz BW, 270 mW 1998 Hitachi
Timing circuit
10 Gb s−1 , 150 mA @ 5 V 1996 NORTEL/IBM
Power transmitter
2.4 GHz, 1W Pout , 48% PAE, 1998 IBM
3.5 V, @ 1.5 V 150 mW Pout W, 47% PAE
Technology comparison 367
CMOS ASIC
chip 1998 IBM
Multiplexer
2:1, 40 Gb s−1 output 1998 Hitachi
Demultiplexer
1:2, 60 Gb s−1 output 1997 Siemens
Mixer, VCO
Mixer: 16.4 dB Power conversion gain,
IIP3 11.1 dBm, NF 6.6 dB, <10 mA/3 V
VCO:differential, 15% tuning range,
−90 dBc Hz−1 @ 100 kHz offset, 22 mW/3 V
include buried ground planes for reduction in cross talk [34], ultrathin layer
MOSFETs [35] and eventually double gate transistors [36] for realization
of volume inversion, leading to enhanced mobility, subthreshold swing and
reduced 1/f noise.
SiGe HBTs have also recently been successfully produced on SOI
substrates fabricated using wafer bonding. Associated with this approach is
the creation of thermal vias to remove heat from the SOI islands. Thermal
vias have been produced with high breakdown voltage, and a factor of four
improvement in thermal conductivity over a conventional buried oxide. The
wafer bonding approach [37] can also permit the incorporation of a buried
silicide layer above the insulator layer, to minimize collector resistance.
Such is the flexibility of this approach that the buried silicide can be
created below the insulator layer (GPSOI). This substrate is intended for
use as a buried ground plane in electronic systems that combine digital
and analogue circuitry on the same chip. Measurements of cross talk on
patterned GPSOI ground planes show world record suppression of cross
talk at frequencies in the range 1–50 GHz [34].
The trade-off between the use of GaAs, Si bipolar and/or MOS devices
for RF applications is a very complicated task due a number of factors. RF
transceiver circuits have a very broad range of requirements, including noise
figure, linearity, gain, phase noise and power dissipation. The advantages
and disadvantages of each of the competing technologies Si-CMOS, BJTs,
Si/SiGe HBTs, and GaAs MESFETs, p-HEMTs and HBTs has been
examined recently by Larson in the light of these requirements [9].
CMOS technology development proceeds at a rapid pace, so any
comparisons can only relate to the state of the art at a particular time.
However, as an example, in a 1995 CMOS process, a 0.5 µm n-MOS
device exhibited peak fT and fmax of approximately 20 and 40 GHz,
respectively. By comparison, the peak fT and fmax of the corresponding
npn bipolar transistor fabricated in a comparable process are 20 and
28 GHz, respectively. The improvement in microwave gain of MOS devices
is primarily due to the lower gate resistance compared to the base resistance
of a bipolar device. MOS devices exhibit a substantial speed advantage at
low currents compared to bipolar devices, but bipolar devices exhibit better
performance at low voltages as shown in figure 10.3.
When properly scaled for width and normalized for power dissipation,
MOS devices exhibit a slightly lower minimum noise figure than bipolar
devices, but their associated optimum source resistance is not well matched
to 50 Ω (close to an open circuit because of the low equivalent input noise
current), making optimum low-noise impedance matching difficult. The
optimum source impedance can be moved closer to 50 Ω in a MOS device,
but only at the expense of increased power dissipation or noise figure [38].
With SiGe, there are excellent prospects of rejuvenating CMOS
technology. The major potential market for heterostructure FETs
MOS versus bipolar 373
Table 10.4. Summary of the key figures-of-merit of the devices realized in SiGe
BiCMOS technology.
SiGe
HBTs Small-signal/low voltage High power/high voltage
(npn) high-speed device low-noise device
BVceo 3.3 V 5.5 V
Gain 100 80
fT 47 GHz 30 GHz
65 GHz @ Vbc = 1 V 55 GHz @ Vbc = 1 V
fmax
Vbe = 0.72 V Vbe = 0.72 V
VA 65 V 124 V
that β also remains virtually flat over a broad temperature range. Because
of its large peak fT , the SiGe HBT retains significant high-frequency
performance even at low currents, allowing the designer the choice to trade-
off speed for low-power operation.
This HBT and CMOS integration, without any loss of HBT
performance, makes it possible to implement a complete system on a
chip with, for example, high-performance analogue functionality and A/D
conversion implemented using the SiGe HBT device, combined with CMOS
for digital signal processing.
10.5. RF CIRCUITS
Figure 10.8. Gain-to-dc power ratio plotted versus noise figure for
state-of-the-art 2 GHz LNAs. Note that the SiGe HBT circuit provides the
best result when power dissipation is a critical factor. (After Larson L E 1998
IEEE J. Solid-State Circuits 33 387–99.)
380 RF applications of SiGe HBTs
Prf,out
ηc/d = (10.2)
Pdc
where Prf,out is the power delivered to the load at the desired RF frequency
and Pdc is the total power taken from the dc supply. Secondly, the power
added efficiency (PAE) of a power amplifier is given by the well-known
expression
Prf,out − Prf,in
P AE = (10.3)
Pdc
where Prf,in is the power needed to drive the input. Thirdly, the overall
efficiency is defined as
Prf,out
η= . (10.4)
Pdc + Prf,in
Both the PAE and the overall efficiency are better gauges of the true
performance of a PA, since they include the power needed to drive the
PA in the determination of the efficiency.
The complications associated with power amplifiers for RF
applications are challenging, as in the case of LNAs. The PA must
satisfy the requirements of linearity, gain, output power and power added
efficiency. In addition, mobile applications which require a lower power
supply (3 V and even lower), have made it difficult to maintain the required
output power and efficiency due to impedance matching limitations.
Ideally, the PAE of the amplifier should not degrade significantly, as the
output power varies from near zero to its maximum value.
In the past, a host of different architectures in which a PA could be
implemented have been proposed [53]. The number of different types of
classes of power amplifiers is too numerous, and they range from entirely
linear to entirely nonlinear, as well as from quite simple to a very complex
one. A class A PA is the simplest and most basic form of power amplifier.
In a class A operation, the transistor is in its active region for the entire
input cycle, and thus is always conducting current. As such, the device
maintains approximately the same gain throughout the entire region and,
in the case of a MOS device, is linear in that region. The problem with class
A structures, however, is their inherently poor efficiency since it is on at all
times, and the current represents a continuous loss of power in the device.
The efficiency of an RF class A PA is limited to 50%. As a result, class A
amplifiers are used only in those situations where the linearity requirements
are stringent.
In a class B structure, there are two devices: one which provides
current to the load during the positive half cycle and one which removes
current from the load during the negative half cycle. The structure is
usually called a push–pull structure. When no signal is applied, however,
RF circuits 383
there is no current flowing, as both the devices are biased at their turn-on
voltages. As a result, in an ideal case, any current through either device
goes directly to the load, and thus attempts to maximize the efficiency.
Although this is generally a linear amplifier, there is an instant during
each cycle when both devices are off, which produces distortion in the
output known as crossover distortion. This architecture allows for very high
efficiencies, as theoretically the efficiency can approach 78%. Hence, this
architecture can be useful in applications where the linearity requirements
are a little less stringent. In situations where the linearity is still an
important issue, the class AB structure, a cross between a class A and
a class B structure, is used. The above classes are examples of linear
structures, where the output amplitude and phase are linearly related to
the input amplitude and phase.
In a communication system, power amplifiers are used to amplify the
signal to the proper power level to reliably transmit the signal which is often
quite high. In many applications, the amount of power consumed by the
amplifier is not critical, as long as the signal being transmitted has adequate
power. However, in a situation where there is a limited amount of energy
available, e.g., in mobile communication systems, the power consumed by
all devices must be minimized in order to maximize the length of time for
which that energy is available.
Power amplifiers are typically operated in class AB mode for most
RFIC applications, in an attempt to achieve a compromise between
linearity and power added efficiency. In this case, the factors of key
importance for amplifier performance are the transistor specification
(for high power gain), linearity (for lowest possible adjacent channel
interference) and breakdown voltage (BVceo for bipolar devices). However,
the breakdown voltage has become less critical for handsets in recent years,
due to the reduction of operating voltages in most handheld units.
In cases where linearity is not critical, and efficiency is highly critical,
class C power amplifiers are used. A class C power amplifier is the most
basic of the nonlinear power amplifiers used at RF frequencies. This
architecture is based on the idea of a class B structure, where the device
is biased at the edge of conduction and the device conduction angle is less
than 180◦ . As a result of the pulsed nature of the output current, the input
and output voltages are not linearly related, and the output of the PA will
be highly distorted if the input voltage amplitude changes.
Since gain is very critical for achieving the best performance, most
high-performance power amplifiers in the 2 GHz frequency range have been
implemented in GaAs or SiGe technology, to achieve the highest possible
power added efficiency. At lower frequencies, silicon MOS devices are
often employed for power amplifiers because of their low cost and robust
operation, despite their poor performance compared to GaAs technology.
A comparison of monolithic power amplifier performances for mobile
384 RF applications of SiGe HBTs
Table 10.5. Summary of maximum PAE, Pout at maximum PAE, gain, PAE at
3 dB compression and Pout at 3 dB compression under four biasing conditions,
tuned for maximum PAE. (After Greenberg D et al 1997 IEEE IEDM Tech. Dig.
pp 799–803.)
A 2.4 GHz VCO for wireless local loop (WLL) applications, with a
power dissipation of 28 mW and phase noise of −110 dBc Hz−1 (at 1 MHz
off carrier), has been fabricated using RPCVD-grown SiGe HBTs and a
resonator consisting of a chip varactor and a microstrip line inductor [61].
An 11 GHz 3 V SiGe VCO with integrated resonator has been reported by
Soyuer et al [62] with a fully differential architecture. This architecture
minimizes noise coupling from digital parts of a highly-integrated chip
into a sensitive analogue VCO. The added circuitry of a fully differential
architecture typically comes at the cost of increased power levels, but
SiGe achieves this result with minimum increase in power consumption.
In the case of SiGe, the VCOs are fully monolithic and contain no
external components, such as inductors or varactor diodes. Recently, IBM
has reported a VCO operating at 17.1 GHz, an ultrahigh transmission
frequency recently allocated for wireless uses in Europe (HiperLAN). The
record setting VCO, operating on a single 3.3 V supply, could be tuned
over a 600 MHz range and exhibited a phase noise of −104 dBc Hz−1 at
a 1 MHz offset from centre frequency, with an output power of −5 dBm,
dissipating only 65 mW. Another VCO, tuned for a new American standard
of 5.x GHz (U-NII), has also performed exceptionally well, with a tuning
range of 840 MHz and a phase noise of −115 dBc Hz−1 at 1 MHz offset at
the centre frequency of 5.6 GHz [63].
(i) higher conductivity metal layers to reduce the loss of the inductor;
(ii) multi-layer metal to either shunt inductors to reduce loss, or to reduce
the area;
(iii) low loss substrates to reduce losses in the substrate at high frequency;
and
(iv) thick oxide to isolate the inductor from the lossy substrate.
Passive components 387
Spiral inductors
2-turn: Q (12 GHz) = 10, 1.5 nH
4-turn: Q (2 GHz) = 7.5, 4.2 nH
6-turn: Q (1 GHz) = 5.8, 9.8 nH
8-turn: Q (1 GHz) = 5.2, 16.6 nH
Capacitors
MIS capacitor C = 1.5 fF µm−2
MIM capacitor C = 0.7 fF µm−2
Resistors
Polysilicon resistors 340 Ω/square and 220 Ω/square
Implant resistors 1.7K Ω/square, 23 Ω/square and 8 Ω/square
Diodes
Schottky barrier diode Vf = 300 mV@100 µA
PIN Vf = 790 mV@100 µA
Varactor 1.4 fF µm−1 @ 0 V, Vf = 810 mV @ 100 µA
ESD 2000 VHBM
IBM and Daimler–Chrysler have been involved in the SiGe area for a
long time. Corporations such as Lucent, Motorola, ST-Microelectronics,
Philips, Infineon, Maxim, Temic, Hitachi and many others have recently
begun development or deployment of SiGe-based HBT processes, and are
likely to make the transition from present efforts in discrete technology to
integrated SiGe BiCMOS technology. SiGe-based mixed-signal technology
is rapidly making its way into the consumer mainstream, at the high
end of the telecommunications market. Present trends indicate that SiGe
technology will find applications in the frequency range 2–30 GHz, above
which GaAs is well established. Components for personal communication
services devices operating between 1.8–2.2 GHz are a fast growing market
segment, along with pagers and wireless local area networks. Other
wireless opportunities might include direct-broadcast satellite TV and
local multipoint distribution services (LMDS). Devices based on SiGe
technology will be able to move data across networks at speeds traditionally
considered beyond the reach of silicon technology. This will bring better
performance at low costs to fibre transport networks, high-speed cellular
voice/data phones and wireless devices such as global positioning satellite
(GPS) receivers. Another application is a differential global positioning
system (DGPS) satellite receiver that uses several GPS channels centred on
1.5 GHz. A related product is targeted for the automobile industry, which
has significant potential to use wireless technology for traffic management
and control, and collision avoidance systems. Inexpensive 24 GHz collision
warning radar systems for mainstream automobiles are also needed.
Figure 10.12. Application circuit using U7004B SiGe front-end IC. (After Temic
Semiconductors, Germany.)
390 RF applications of SiGe HBTs
10.7.2. IBM
The mainstream SiGe chips introduced by IBM include basic building
blocks—low noise amplifiers, voltage controlled oscillators, power amplifiers
and discrete transistors. SiGe is well suited to realize innovative high-
frequency products, e.g. antenna switches for the transmit/receive path,
satellite communication applications or wireless local area networks.
Several of the chips are designed as low-cost, highly-reliable direct
replacements for gallium arsenide parts for a broad spectrum of
communications applications and are listed below. Several system-level
hardware and software products [66] are now in production and a brief list
is given in table 10.7:
• SiGe 3 V GSM tri-band low-noise amplifier
• SiGe 3 V tri-band image reject mixer with low-noise amplifier
• SiGe 3 V GSM tri-band voltage controlled oscillator
• SiGe PDC linear power amplifier
Commercially available products 391
10.8. SUMMARY
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Index
397
398 Index