Fault models

0
Stuck-at-0 1 Stuck-at-1
0
Transition ↑/0 0 11 Transition ↓/1
0
Reset coupling 1
0 1 1
0 Set coupling
0
Inversion coupling 0
1 1 10 1
0 Inversion coupling
0 0
AND bridging 0 1 11 0
1 OR bridging
Neighborhood 0 1 Neighborhood
pattern sensitive 0 pattern sensitive
faults (active) 1 0
1 1
0 1 0 1 faults (passive)
1 0

Address decoder
faults ADR
ADR ADR
ADR ADR
ADR ADR
ADR ADR
ADR
Elements of march test

↑
↑ (w0) ↓ (w1) ↑ (r1,w0) ↓ (r0,w1)

7 x 0 1 1
0 1 1
0 0
6 x 0 1 1
0 1 1
0 0
5 x 0 1 1
0 1 0
1 0
4 x 0 1 1
0 1 0
1 0
3 x 0 1 1
0 1 1
0 0
2 x 0 1 1
0 1 1
0 0
1 x 0 1 0
1 1 1
0 0
0 x 0 1 0
1 1 0
1 0
C - algorithm
↑ (w0) ↑ (r0,w1) ↑ (r1,w0) ↓
↓ (r0,w1) ↓ (r1,w0) ↓ (r0)
0 1
0 0 1
0 1 1
0 0 1
0 1 0 0
0 1
0 0 1
0 1 1
0 0 1
0 1 0 0
0 0
1 0 1
0 1 0
1 0 1
0 1 0 0
0 0
1 0 1
0 1 0
1 0 1
0 1 0 0
0 1
0 0 1
0 1 1
0 0 1
0 1 0 0
0 1
0 0 0
1 1 1
0 0 0
1 1 0 0
0 1
0 0 0
1 1 1
0 0 0
1 1 0 0
0 0
1 0 0
1 1 0
1 0 0
1 1 0 0
 Number of steps: 10n
 Fault coverage: AFs, SAFs, TFs, CFins , CFids
Checkerboard test and data retention

 Designed to test refresh

1 0 1 0
operations of DRAMs
0 1 0 1  Maximizes leakage current
and detects leakage faults
1 0 1 0  Used as data retention test
0 1 0 1  To be effective it must
consider address
scrambling and layout
Data backgrounds for word memories
Multiple
Multipledata
databackgrounds
backgroundsto todetect
detectcoupling
couplingand
andbridging
bridgingfaults
faultsbetween
betweencells
cellsof
ofthe
thesame
sameword
word
For
Forevery
everypair
pairof
ofcells
cellsall
allfour
fourcombinations
combinationsare
arechecked
checked

 22(log
(log2ww++1)
2 1)backgrounds
backgrounds

 16
16backgrounds
backgroundsfor
for

 128-bit
128-bitwide
widememory
memory

 Normal
Normaland
andinverse
inverse




D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
Data in word-oriented memory
↑ (w0) ↓ (r0,w1) ↓ (r1,w0) ↑ (r0,w1)
Parallel memory BIST
Clock Hold System logic

Data
Data generator
generator
FF
SS Address
Address generator
generator
M
M Control
Control generator
generator Fail
⊕

BIST
Start Done mode

Memory
 Serial memory BIST
System logic
Data output
Serial input Serial output
Address M
0 0 0 0
r0 0 0 0 0
w1 1 0 0 0
r0 1 0 0 0
Memory w1 1 1 0 0
r0 1 1 0 0
w1 1 1 1 0
r0 1 1 1 0
 Minimal logic and routing w1 1 1 1 1
 Longer test time r1 1 1 1 1
Serial-parallel data interface trade-offs

Memory Memory

Memory Memory
Memory BIST collar
Functional logic

Memory
Memory BIST
BIST
controller
controller

Memory controller at the top level

To / From
•TAP controller as test engine
TAP controller
+ Embedded memory BIST collar
•mux address / control bus and data lines
•local comparator with single pass/fail
•local data generator to reduce routing
area and timing problems
•local address validation
Memory
array
 Shared controller and parallel test
Functional logic

Memory
Memory BIST
BIST
controller
controller

To / From
TAP controller
+ +
 Insert collars
 Connect them
through memory test
bus
to memory BIST
•
controller
Memory Memory
• to TAP
array array
Parallel memory BIST collar
BIST address BIST data

Functional control
Functional address Functional data

BIST control
Pass / Fail

MBIST mode
Sin =?
⊕

⊕
Sout Address Ctrl Data in Data out

Memory array
Clock
Full-Speed test application
 Runs at system clock speeds with single cycle
read/write operations
 Uncovers speed-related defects
 Reduce test application time.
Clock Clock Clock Clock Clock
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

Clock

Addr/Cntrl/ Setup
Setup Setup Setup Setup Setup
Data Read
Read 11 Write 1 Read 2 Read 3 Write 2

Memory
Output Read 1 Read 2 Read 3
•••
Compare Compare Compare Compare
Circuitry Read 1 Read 2 Read 3

Circuit Pass/Fail Pass/Fail

Output Read 1 Read 2

Write Write 1
Diagnostics
 Detect failing location/data during test
 Should diagnose speed related defects
 Two types - Hold and resume, Hold and restart
 How it works?
• BIST controller stops after 1 (or 2) failures
• Fail data is scanned out
• BIST session resumes from where it stops (Hold and
resume)
• BIST session restarts after fail data is scanned out
(Hold and restart)
Full-speed diagnostics

MBIST
controller

+ Diagnostic monitor ATE

Restart

Memory
Memory
array
array
Yield improvement with memory redundancy
 Memory percentage, defect rate, and redundancy
amount affect yield
Redundancy Yield Improvement
100
90
Optimal
80
Memory Yield

70
Level 3
60 Redundancy
50 Level 2
40 Redundancy
30 Level 1
20 Redundancy
10 No Redundancy
0
0 10 20 30 40 50 60 70 80 90 100

Chip Memory Percentage

Source: Zorian, Rodgers, DATE 2002
Redundancy and repair

Memory
Memory BIST
BIST
controller
controller

+  Extra columns, rows, or rows

and columns
 At the end of test - good,
repairable, or non-repairable
 Repair data scanned out at
Memory
Memory the end of test
Array
Array
Full-Chip memory BIST integration
Read in SOC netlist
Identify memories

BIST GENERATION
Assign memories to
controller
(BIST Scheduling)

Memory BIST Generation

(Generate Controller/Collars)

BIST INSERTION
Insert controllers in the design
Stitch controllers to top-level
Full Chip Memory BIST Control
SOC
TM S Block
BIST Block
TCK TAP Controller
TRST
Memory 1
rst_l

BIST
CLK Controller
BIST Block
test_done

fail_h Memory 2

test_h

MBIST Data
Register
TDO
TDI Boundary Scan Register
Programmable algorithms
 Selection of algorithms
• March1, March2, March3, Unique Address, Checkerboard, …
• address jumping
 Synthesizable algorithms
• user defined prior to synthesis
• simple language
• number of sequences, backgrounds, sequence elements etc.,
 Programmable algorithms
• defect mechanisms may not be known before fabrication
• memory BIST controller implements a class of algorithms
• field programmable parameters define active elements of test
sequences
Summary
 Key components of a BIST controller
• algorithm controller
• data background generator
• address generator
• comparator
 Very high quality test of embedded arrays
 BIST controller shared across a number of memory
arrays to reduce area
 BIST diagnostics helps in gathering failure
information
 Built-in repair results in yield improvement