FRAM MCUs For Dummies, Part 3: FRAM

reliability, operating life and error rates

V.C. Kumar, Texas Instruments - September 03, 2012

Editor’s note: Demand for memory is insatiable at all levels of systems design. As
designers look to respond with larger memory stores and more complex memory
architectures, a greater understanding about a broad range of memory types becomes
more critical. This excerpt of Texas Instruments FRAM MCUs For Dummies by V.C.
Kumar offers a detailed look at FRAM technology and its characteristics. In part 1 of
this series, author Kumar reviewed the basics of FRAM technology. Part 2 examined
FRAM's characteristics and its advantages. In this concluding part, Kumar discusses
more about FRAM reliability, operating life and error rates.

Excerpted from Texas Instruments FRAM MCUs For Dummies®, © 2012 John Wiley & Sons, Inc.
Available exclusively from Mouser Electronics, Inc. To request your free copy, please visit
www.mouser.com/framfordummies.

Gaining System Robustness with FRAM

The unique features of FRAM technology not only allow for increased functionality and capability but
also increase reliability and robustness of low-power products.

FRAM technology allows products to offer an inherent write guarantee during a write cycle even in
case of power loss. Because very little energy is needed for write cycles (see Chapter 4), all the
necessary power for a write cycle can be front-loaded in a small capacitor at the beginning of a write
cycle. This front-loading guarantees that the write process will be robustly and accurately completed
every time even if there is a power loss in the middle of writing. EEPROM and flash are more prone
to data corruption in case of a power loss due to the long write times, high voltage, and increased
power needs.

Also, it is important to note that with flash, you can erase only an entire block or sector (typically
256 or 512 bytes, sometimes larger) and not specific bytes or words. This limitation adds
complications in applications where programming/writing data is key. For reliability and robustness,
much overhead is needed, leading to the need for complicated, expensive, and time-consuming
safety features.

FRAM technology is also used in the automotive market, which provides another proof that the
technology is robust and reliable. More information is available on the Ramtron website
(www.ramtron.com).

Seeing Results from Production and Reliability Testing

Reliability of a nonvolatile memory is all about robust data retention and update capability over time
and the operating temperature range. The most common question and one of the biggest concerns
from customers regarding FRAM is whether the technology is robust and reliable and whether there
is test data to back up the claims. The answer is unequivocally yes. This section highlights some of
the key items that define the reliability and robustness of FRAM as a memory technology.

TI has been working on FRAM for more than 12 years and has been exhaustively testing the FRAM
architecture as well as the manufacturing process for reliability in this time period. TI has already
proven FRAM data retention to the industry standard of ten years at 85°C.

Explaining FRAM reliability

Reliability is typically judged using several factors that include data retention (over time and
temperature), read/write cycling endurance, and high temperature operating life (HTOL). TI also
looks at the SER when the memory is subject to radiation.

The reliability tests to prove FRAM reliability were carried out on a 4 Mb, 2T-2C architecture,
standalone FRAM memory device, and the bit behavior as a function of electrical stress conditions
was analyzed by measuring the internal 8 Mb bit signal distributions.

data retention

Data retention
Reliable 2T-2C FRAM operation requires that the logical data states have sufficient signal separation
across all temperature and stress corners for reliable data state reads (see Chapter 2 for a
discussion of the architecture involved). There are two key mechanisms that directly impact FRAM
data retention:

● Thermal depolarization (TD): Thermal depolarization is the phenomenon whereby an increase in

the temperature of the ferroelectric material reduces the polarization effect and therefore the
signal margin. Although the scale of reduction is temperature dependent, it is not strongly time
dependent. When the memory returns to room temperature, the impact (reduced signal margin) is
seen only on the first read/write operation. This reduction in polarization is not permanent, and the
original margins are restored in subsequent read or write operations.
● Imprint: Ferroelectric memories experience a phenomenon known as imprint when exposed to
high temperatures for long periods of time, especially after data is written. When the memory cells
are baked for a long time at elevated temperatures in a particular state (0 or 1), this imprint
phenomenon could impact the ability of the cell to be rewritten with the opposite state.
Specifically, in a 2T-2C architecture (see Chapter 2) the switched polarization capacitor signal is
reduced, leading to a loss of signal margin in the circuit (note that the nonswitched polarization
capacitor signal has been proven to be quite stable in the TI design). The effect is almost as if the
original data value is imprinted in the cell and the opposite state cannot be written to the cell,
resulting in a failure to read/write the opposite state.

Data retention test flow

TI uses a specific data retention test flow to test FRAM devices (see Figure 3-2). This test flow starts
with baking an initial data state (“same-state,” or SS) at a high temperature for a specified amount
of time. After reading the SS, the complement data state (“opposite-state,” or OS), is written to the
memory, which is stressed at the maximum operating temperature rating (85°C) to test thermal
depolarization (TD). The bake time was set at 30 minutes to allow enough time for the samples to
reach the desired temperature. Following the OS data read, the SS is again rewritten, and the high-
temperature bake continues to the next read-point in the bake test.
 Figure 3-2. FRAM Data retention test process.

The data retention test flow process was optimized to test both potential thermal depolarization and
imprint issues, addressing both SS and OS data. The amount of time the bits spend at high
temperature in the SS is maximized because this has the biggest impact on the imprint condition,
which will be observed as an OS read fail. The key issue is to identify the temperature/time
combination curve, which poses a risk to robust/reliable accurate reads and writes.

For TI’s FRAM technology, this imprint degradation happens only after 1,000 hours at 125°C (which
equates to ten years at 85°C), as shown in Figure 3-3. The data used is from a 2T-2C architecture,
where bits were preprogrammed with a pattern of both 0s and 1s, reflecting a real-life application.
Note that this is a special case in which the bit distributions were measured as the last step of the
read-point tests after both the SS and OS data reads were completed.

Figure 3-3. Prolonged exposure to high temperature reduces Data '1' signal level and
signal margin.

The data retention reliability tests looked at the signal margin loss by monitoring the bit signals
(measured at room temperature) as a function of bake time over a temperature range of 85°C to
175°C. Half of the bits were baked as Data ‘1’ and the other half as Data ‘0’, representing a mixture
of data states.

lessons learned

Lessons learned
A key outcome of the data retention tests was to understand long-term data retention as a function
of initial signal margin. Results for both SS and OS data retention were obtained for units and
plotted against the initial signal margin. Units with insufficient signal margin window at the
beginning of the bake test either failed the SS read, a consequence of the thermal depolarization at
the high temperature bake step, or after a period of time failed the OS read as imprint reduced the
margin.

Identifying the minimum initial signal margin allowed design of a margin test screen, which includes

● The needed tolerance for the expected signal drift that occurs during typical use conditions in the
field
● Tolerance for the depolarization at the maximum operating temperature in the field
● Data-sensing circuitry parameters

In embedded memory applications, program, code, and device trim information is often written prior
to solder reflow assembly. This means that the memory will be exposed to temperatures in the range
of 245°C to 260°C for short amounts of time (a few minutes). Prolonged high-temperature exposure
could expose the memory to thermal depolarization. Chapter 4 discusses the appropriate design
safeguards to ensure that an embedded FRAM device retains data through this process.

Write/read cycling endurance

FRAM data access is different from other embedded nonvolatile memories in that it requires a
restore/refresh operation after a read operation, not just with a write step. Therefore the number of
read/write cycles (endurance cycles) for FRAM memory cell during normal use can be quite high.
This is especially true if FRAM is targeted to replace cache/data memory (SRAM). TI targeted
greater than 1014 cycles to ensure at least ten-year life even under the most extreme operating
conditions.

The reliability tests for endurance consisted of two distinct tests:

● An intrinsic test that accessed 128 bits up to 5.4x1012 cycles in a 30-day stress period. This test
accessed five different rows simultaneously, each at a different duty cycle, in order to cover a
cycling range of 5.4x109-5.4x1012 during the 30-day stress period.
● The second test was a “full-chip” test, which accessed all 8 Mb cells for 108 cycles each within the
same 30-day stress period.

To separate the wear effects of endurance cycling from data retention effects, the endurance tests
were run at 25°C. This is reasonable because the polarization wear-out in thin film ferroelectric
capacitors resulting from data cycling is strongly accelerated by voltage but is not strongly
dependent on temperature.

Table 3-1 summarizes the endurance results measured on over 1,300 total assembled units with the
standard 30-day cycling tests.
 Table 3-1. Endurance Cycle Test Results.

In addition, the tests showed no polarization reduction (from the initial margin) after 1013 cycles. As
additional characterization, TI also evaluated 37 packaged devices with the intrinsic test pattern for
an extended stress period of three hundred days, achieving a maximum 5.4x1013 switching cycles,
again with all units passing the post-cycling functional tests.

TI also ran additional accelerated stress

TI also ran additional accelerated stress tests to estimate the endurance cycle limit. We tested an
additional 150 packaged parts as a function of operating voltage up to 5.4x1012 cycles. All 150 units
passed the post-cycling functional tests. Voltage increase accelerates stress, emulating additional
cycles; each 0.1 V operating voltage increase leads to an approximate 10x reduction in the number
of cycles required to reach an equivalent signal level. Based on the results of the voltage
acceleration tests, the intrinsic read/write cycle endurance limit at 1.5 V operation is currently
shown to be greater than 1015 cycles.

TI’s test results haven’t reached the limit of endurance, but they have not seen any failures in their
testing. Empirical data from other FRAM manufacturers show that this limit could be as high as 1016
cycles or greater.

The signal margin results from the pre/post 108 cycles measured on 160 devices tested with the full
8 Mb chip cycling pattern show an increased margin after cycling for the lowest ‘1’ bit (in the range
of approximately 5 percent).

TI also evaluated the impact of endurance cycling on Data retention reliability after both the
intrinsic and full-chip cycling tests. The FRAM data retention was not impacted by the cycling. TI
continues to test FRAM products and expects to update its current endurance specification limits as
it gets more information.

High Temperature Operating Life (HTOL)

HTOL testing is a common test methodology used for many products and technologies. HTOL
stresses the device under test, when operating, over temperature. TI used test patterns similar to
SRAM test patterns because this would be the most stressful operation that a FRAM memory would
see - acting as traditional RAM. The tests included solids, scan, and march patterns. In total, the bits
that were tested experienced approximately 107 access cycles during the 1,000-hour life test, at 1.8
V, 125°C stress conditions.

TI tested the devices at 125°C to accelerate the testing. One thousand hours at 125°C is equivalent
to ten years operation at 85°C. Also, the HTOL stress voltage was 1.8 V, 0.3 V above the 1.5 V
nominal operation condition. These test conditions were equivalent to 1010 cycles at normal 1.5 V
operation.

TI initially tested more than 3,800 units for 168 hours to understand Early Life failure. Table 3-2
summarizes the results from these tests.

Table 3-2. Early Failure Rate Test Results.

The HTOL test combined the effects of endurance and retention bake into one test. The initial result
showed an increased signal margin from the bit accesses and switching. However, over time
(approximately 750 hours stress time), the high temperature caused imprint signal reduction similar
to a data retention bake. The initial signal margin screens are important to assure reliability during
normal operation.

soft error rate

Soft Error Rate (SER)

FRAM devices exhibit a relatively high immunity to radiation effects compared to flash and EEPROM
technologies because data state is stored as polarization and not as an electronic charge. Switching
the polarization requires local application at the cell level of an electric field to the capacitor, so the
bit cells are resistant to standard gamma/neutron radiation.

TI evaluated its 4 Mb devices at a Neutron Beam Facility totaling more than 130 hours of beam time.
All testing followed the JEDEC JESD-89A protocol. Two types of experiments were conducted:

● Retention mode (static), which consisted of data write, power down, static retention time, power-
up, and data read while exposed to radiation
● A dynamic mode where all the bits were accessed using the periphery circuits

The retention mode test yielded a FIT rate less than 0.051/Mb with a 90 percent confidence interval.
Dynamic access of a checkerboard pattern resulted in a FIT rate less than 0.16/Mb at 90 percent
confidence, which is more than three orders of magnitude lower than standard 6T-SRAM devices.

TI has conducted comprehensive reliability tests on their FRAM memory arrays over the past several
years. Data retention, cycling endurance, and high temperature operating life tests all show that our
FRAM technology is reliable and robust for operating life for ten years at 85°C. In addition, SER
tests of the FRAM confirm that the FIT rate is dramatically lower than that of standard 6T-SRAM
devices (and also flash/EEPROM).

Excerpted from Texas Instruments FRAM MCUs For Dummies®, © 2012 John Wiley & Sons, Inc.
Available exclusively from Mouser Electronics, Inc. To request your free copy, please visit
www.mouser.com/framfordummies.

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