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Ee2255 - Digital Logic Circuits April-May 2010
Ee2255 - Digital Logic Circuits April-May 2010
Ee2255 - Digital Logic Circuits April-May 2010
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Reg. No. :
Fourth Semester
(Regulation 2008)
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Answer ALL Questions
1. Show that
a
a u
u ll .
p
p
(a) a + a' b = a + b
(b)
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x ' y' z + x ' yz + xy' = x ' z + xy' .
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2. Draw the Truth table and logic circuit of half adder.
3.
w w
w . Draw the circuit of SR Flip flop.
w
w w
4.
5.
6.
What are synchronous sequential circuits?
8. Which IC family offers (a) low propagation delay, and (b)low power dissipation?
12. (a) Design a synchronous sequential circuit using JK for the given state
diagram. (16)
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a
a u
u ll .
(b)
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p
Design a BCD counter using T flip flop.
Or
(16)
13.
w .
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r e
e
(a) Design BCD ripple counter using JK flip flop.
Or
(16)
w w
w w (b) (i) Reduce the number of states in the following state table. (12)
w
Next state Output
Present state
x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
(ii) Starting from a, find the output sequence generated with input
sequence 01110010011. (4)
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14. (a) (i) Design a combinatorial circuit using ROM. The circuit accepts 3-bit
number and generates an output binary number equal to square of
input number. (8)
(ii) Repeat the above problem using PLA. (8)
Or
(ii)
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Describe the different types of memories.
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(8)
15. (a)
a
a u
u ll .
Write HDL program for full adder and 4 bit comparator.
Or
(16)
(b)
jjiin
(i)
np
p Write an HDL behavioral description of JK flip flop using if-else
statement based on the value of present state. (8)
w .
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e (ii) Draw the logic diagram for the following module.
module seqcrt (A, B, C, Q, CLK) ;
(8)
w w
w w input A, B, C, CLK ;
w
output Q ;
reg Q, E ;
always @ (Posedge CLK)
begin
E<=A&B;
Q < = E/C ;
end
end module
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