2017 IEEE Computer Society Annual Symposium on VLSI
Ultra-Low Energy Data Driven Computing
Using Asynchronous Micropipelines and
Nano-Electro-Mechanical Relays
Haider Alrudainy, Andrey Mokhov, Fei Xia and Alex Yakovlev
School of Electrical and Electronic Engineering,
Newcastle University, Newcastle upon Tyne, NE1 7RU, England, UK
Emails: {h.m.a.alrudainy, andrey.mokhov, fei.xia, alex.yakovlev}@ncl.ac.uk
Abstract—Asynchronous logic and power gating are promising
techniques for low duty cycle applications which need maxi-
mal energy efficiency, which are becoming more common-place
with the popularity of wireless and embedded systems. This
paper investigates the potential use of Nano/Micro- Electro-
Mechanical (N/MEM) switches as the means of power gating
asynchronous computation. A systematic optimization of the
N/MEMS parameters is performed using finite element analysis
(FEA) in the multiphysics COMSOL tool. An asynchronous
FIR filter with a 4-phase bundled-data handshake protocol is
designed and implemented in the 90nm technology node. The
N/MEMS switches are comparatively studied with conventional
sleep transistors in a system where both the computation and the
timing controls for the asynchronous FIR circuits are power gated
appropriately. It is demonstrated that our N/MEMS solution
offers a 69% energy improvement when 32-tap FIR filter is power
gated at a data rate of 1KHz compared to a 39% savings realized
by using sleep transistors in the same design.
I. I NTRODUCTION
Ultra-low-power digital circuit design has become a key
challenge given the growth in demand for energy-constrained
devices that consume the minimum energy possible, and have
less emphasise on circuit performance. These devices include
wireless sensor network, biomedical devices, baseband posses-
sor, and autonomous sensors for the IOTs [1]. Traditionally,
the scaling down of supply voltage has been used to reduce
the dynamic energy quadratically [2]. However, operating at
low voltage introduces a significant increase in propagation
delay, which in turn leads to longer task completion time
resulting in significant increases in leakage energy. This is even
exacerbated as the technology node is scaled down further
past the 90nm transistor size. Since the target applications in
this paper generally demand non-invasive power gating of the
combinational circuit, the idle time between operations is non-
trivial which in turn leads to more energy consumption.
To alleviate idle energy consumption, power gating tech-
niques [3] as well as body biasing approaches [4] were used in
both asynchronous and synchronous circuit designs. Of the two
methods, power gating has been demonstrated to be an effec-
tive technique to mitigate leakage power during the idle period.
Typically, sleep transistors are inserted between the main
power supply rail and combinational circuit (CC). However,
these transistors themselves contribute high leakage current
making the reduction in idle energy of energy-constrained
2159-3477/17 $31.00 © 2017 IEEE
DOI 10.1109/ISVLSI.2017.36
applications more challenging. In most synchronous designs,
switching circuits off during idle periods is usually performed
by adopting shut-off instructions within the program code. In
contrast, it is difficult to employ this approach with circuit
systems which operate without using instructions.
Although, a recent proposed approach performs power
gating during active computation time within the sub-clock
cycle [5], synchronous circuits will still require proper timing
analysis. It is essential to ensure that the hold and set-up
time conditions are satisfied during circuit switching on/off.
In asynchronous circuit designs, however, local handshake
protocols are used as control signals to power gate during
the idle period, as these control signals specify when the
circuit starts and ends computation. A plethora of research has
been conducted to investigate power gating in asynchronous
designs. In [6] the request signals of a four-phase bundled
data scheme are utilized as a control signal to power on/off
the idle circuits in each stage of a micropipeline. A further
improvement has been proposed to power gate both the com-
binational circuit (CC) block and the latches within each stage
of the pipeline [7]. The latter approach proposes monitoring
the states of the adjacent blocks, and thereby shutting them
off when required. Generally, depending on how the delay line
(DL) block is implemented in asynchronous designs, this can
be a major source of a significant amount of leakage current.
Therefore in the present work, zero-leakage N/MEMS-based
devices are employed to power gate each combinational circuit
(CC) block as well as the delay line (DL) block (i.e. N/MEMS
provides free mechanical delay time) in micropipeline stages.
Furthermore, the conditions where N/MEMS-based power
gating circuitry can achieve greater energy savings than sleep
transistor counterparts are investigated, including questions of
design architecture, and behaviour of operation.
This work addresses the limitations and drawbacks of
the previous work utilizing N/MEMS for energy-constrained
implementations. Since these studies are either based on
theoretical demonstrations [8] or showing a lack of the model
developed and simulation environment utilized [9]. Therefore,
a novel work based on 3D FEA performed on COMSOL
multiphysics simulation tool is presented to target applications
which exhibit low duty cycles as well as bursty computation
behaviour. It should be noted that, depending on the data
158
 Table I: Key features of N/MEMS actuation characteristics. IDS Gate dielectric
Gate
h
MEMS Piezoelectric Electrostatic Magnetic Thermal g0 gd
Fast switching () () (∼) (∼) Source Body Drain CL
Simple fabrication () () () () + V
Low pull-in voltage () () () () S + Vgb
Bias current [mA] () () () () Vgb
Low power () () () () Vrl Vpi
High force () () () ()
Scalability () () () () Figure 1: Cross-section of N/MEMS with its Vgb vs. Ids curve.

Table II: key Features of the fabricated N/MEM relays.

Ref. No. Geo. A. D. S. M. C.R.(Ω)
[10] 4 PP V Poly-SiGe 1.4k
proposed 4 PP V Poly-SiGe NR
[11] 3 CB L SiO2 5K
rate (target throughput) and design architecture, the total
energy consumed by the power gated circuits can be greater
or smaller compared to cases with no power gating. This
work investigates the extent to which power gating in the
asynchronous micropipeline based N/MEM switches can be
beneficial compared to using sleep transistors at different data
rates and levels of design architecture complexity.
II. BACKGROUND
Due to recent advances in planar fabrication process, me-
chanical computing has been revived for energy-constrained
applications [10]–[12]. Typically, N/MEMS can be classi-
fied, based on the method of actuation, into electrostatic,
electrothermal, magnetostatic, and piezoelectric. Each type of
actuation scheme has specific advantages and drawbacks as
listed in Table I. It can be deduced from Table I that the
electrostatic actuated MEM relay is attractive candidate for
digital logic applications due to its low active power consump-
tion, scalability, fast switching, and ease of manufacture using
conventional planar processing techniques [10]. Alternatively,
they could also be classified according to the axis of deflection
(lateral, vertical), contact interface (ohmic or capacitive), and
geometric shape (see-saw beam (SS), cantilever beam (CB),
dual bridge (DB), clamped-clamped beam (CC), parallel plate
(PP), sidewall perimeter beam (SW)). Table II summarises
the key features of various N/MEM relays. These features
including the number of terminals (No.), geometric shape
(Geo.), actuation dirction (A. D.), structure material (S. M.),
contact resistance (C. R.), and switching energy (Es ). In the
present work, for coherent comparison analysis, relays in Table
II are simulated using the COMSOL multiphysics tool with
comparable footprint size (see Section III).
Operating principles of an electrostatic relay can be sum-
marised as follows. Firstly, As Vgb is increased, as shown in
Fig. 1, an electrostatic force is generated between the gate-
body terminal. As a result, the gate bends toward the body
terminal, and thereby an elastic spring force is generated which
counteracts the electrostatic force. Increasing Vgb leads to an
increase in the gates deflection at a higher rate due to the
positive feedback which in turn decreases the gap distance and
leads to an increased of electrostatic force. As Vgb reaches a
level above the pull-in voltage (Vpi ), a large enough spring
Es (pJ) force can not be produced to balance the electrostatic force.
1.8 Consequently, the gate electrode collapses into the drain-
1 source terminal. To turn off the N/MEM relay, Vgb is lowered,
0.082
which decreases the electrostatic force between the suspended
gate and the body terminal. Eventually, as Vgb continues
to decline, the spring elastic force becomes larger than the
electrostatic force, and thus the dimples pull out of contact.
The release voltage of the N/MEMS is referred to as Vrl , as
can be seen in Fig. 1.
III. F INITE E LEMENT O PTIMIZATION
In the present study, 3D Finite element analysis (FEA) is
used to accurately simulate and evaluate N/MEMS physical
parameters. Figs. (2-3) show the 3D FEA simulation results
of various geometric shapes of MEMS at comparable foot-
print size (450um2 ) and material type (poly-SiGe). These
experiments were carried out using 3D FEA in COMSOL
multiphysics tool. The pull-in voltage, bending out of plane,
and residual stress of these relays have been evaluated and
analysed. Fig. 3 (b) illustrates that 4-terminal relays with
double springs, as expected, are pulled-in with lower voltage
and switching energy compared with that of Fig. 3 (a) and
Fig. 2. However, the indicated results demonstrate that 4-
terminal relay with double spring suffers from high residual
stress which may affect their functionality of operation. In
the present work, due to its higher recorded on/off switching
cycles without exhibiting any failure (2.1× 109 ) as well as
lower switching resistance, the relay in Fig. 2 is used to shut-
off the idle circuits. For example, if these relays switch on/off
on average of 1KHz for 1 second followed by 4 minutes
process of idle, then they roughly can last for 17 year without
experiencing any failure in operation.
LA
W
Channel
WA L
(a) (b)
Figure 2:Demonstrates the: (a) FEA-simulated pull-in voltage; (b)
simplified sketch, symbols L, W, LA, and WA denote, respectively,
spring (length/width), and actuation area (length/width) [10].

159
 Table III: Current and scaled MEM relay physical parameters based on COMSOL multiphysics tool.

MEMS Pull-in Switching Mechanical Stiffness Mass Damping Actuation Actuation

Area (um2 ) voltage(v) energy (pJ) delay(μs) (N/m) (pg) (μN.s/m) gap(nm) Capacitance(fF)
450 (existed) 11.3-2.6 0.1-3.2 0.15-0.69 10.14-192.6 1.1-2.9 50 200 40
45 (NEMS) 0.19-1.97 0.049-0.003 0.06-0.28 5.51-68.2 0.15-0.25 0.07 40 17
4.5 (NEMS) 0.1-0.31 (0.037-0.36)× 10−3 (24-85)× 10−3 0.15-1.51 (3-3.77)× 10−3 0.007 20 3.54

(a) (b)
Figure 3: Demonstrates the 3D FEA of: (a) anchor MEMS [11]; (b) 4-terminals with double spring MEMS.

A. Energy-Latency Analysis of N/MEMS
An extensive parametric sweep simulation is performed
using the COMSOL multiphysics tool, in this work, to estimate
the range of electo-mechanical parameters for both fabricated
450um2 and scaled 45um2 , and 4.5um2 relays respectively,
thereby energy-latency trade-offs of N/MEMS can be opti-
mised. These parameters can be seen in Table III.
The result in Fig. 4 (a) shows the switching energy con-
sumption of MEMS by using 3D FEA as a function of
the dimple gap (gd ), and resonant frequency (w). As can
be seen, increasing (gd ) causes an almost linear increase in
switching energy at low (w). Alternatively, switching energy
increases exponentially with increasing resonant frequency (w)
by sweeping the ratio of (L/W), at high (gd ). Fig. 4 (b) shows
the simulation results of mechanical delay time as a function
of the gap ratio (gd /g0 ), and resonant frequency (w). One
Fig. 4 (d) demonstrates a significant reduction in the switch-
ing energy of the scaled MEMS. Furthermore, these results
clearly indicate a better trade-off between switching energy
and mechanical delay time compared to that of the fabricated
MEMS (A=450um2 ). As an example, it is found that at,
(gd /g0 )=0.5, every ∼5× increase in switching energy can be
trade-doff for a ∼5× reduction in the scaled delay, as can be
seen in Fig. 4 (c-d).
IV. A SYNCHRONOUS PIPELINE STAGE
The asynchronous micropipeline, as shown in Fig. 5, pro-
vides an event-driven scheme utilizing localized handshaking
signals to transfer data through the pipeline sequentially from
one stage to another [14]. When the input data is ready to
be sent, a request signal req_in is generated resulting in
12
x 10
¡

observation which can be made is that Tmech is inversely x 10

6
x 10
-11

1 10
Mechanical delay time (sec)

proportional to (w), and it is linearly proportional with the

Switching energy (J)

1
0.8 8
increase in (gd /g0 ), which is consistent with the theoretical 0.6
0.8
0.6 6
predictive analytical equation in the previous study [13]. 0.4
0.4 4
B. Implications of Scaling on the Energy-Latency Trade-off 0.2
0.2
0 2
0
Like the case for CMOS, the scaling down of MEMS 0.8
Ga 6 0
1
pr 2 1.5
at 0.6 -7
parameters will lead to achieving greater energy savings. io
(g
d/
4
/w)]
x 10
1/w 3
[f(L/w 4
)]
1
(m)
x 10
-7

g0 0.4 2 [f(L
) 1/w x 1 -7 0.5 gap
A 1-DOF optimization based on a variable scaling factors (a) 0 (b)
-14

7 x 10
methodology has been proposed in previous work [13]. How- x 10

7
x 10
4
-13 15
Mechanical delay time (sec)

x 10
ever, single DOF analysis can lead to inaccurate outcomes. 4 3.5
Switching energy (J)

3
As a result, 3D FEA coupled with the sweeping of scaled 3
2.5
1.5
10

parameters has been performed in the COMSOL tool. In our 2 2 1

1.5 5
experiment, it is postulated that area (A), gate thickness (h), 1
1
0.5

and actuation gap (g0 ), can be scaled by factors of 0.1×, 0 0

0
0.8 2.5 0.5
0.5×, and 0.2× respectively. Other parameters such as gd , Ga
p r 0.6
1.5
2

7 -7
1
3
-8
at x 10 x 10 1 1.5 2 x 10
io
spring width (W), and spring (L) are kept variable by sweeping (g 0.4
d/
g0 0.5
1
1/w
[f(L
/w)] /w [f(L/w 2
)] 2.5 1 gap
(m)
)
(c)
(L/W). Ultimately, some parameters will approach a lower (d)

limit and it may not be be possible to scale them down as
readily as other parameters. For instance, g0 is limited by
nano-gap formation technology, while gate thickness (h) will
be set by process technology constraints.
Figure 4: Illustrates that: (a) switching energy based FEA at g0 =200nm and A=450um2
as a function of gd and resonant frequency (w); (b) Tmech. as a function of gap ratio and
resonant frequency obtained from 3D FEA at A=450um2 ; (c) Tmech. of the scaled relay
at g0 =40nm and A=45um2 as a function of gd and resonant frequency; (d) switching
energy of the scaled relay.

160
enabling latches to capture the input data through EN1 and
to raise the output request signal req_1. Consequently, the
previous stage waits for an acknowledgement signal from the
next stage, which is asserted once the data is computed and
ready to be stored into the latches. While the latched data in
the previous stage is being processed by the combinational
circuits, the request signal req_1 is also passing through a
matched delay element. The delay of the DL block is estimated
to be not less than the worst case delay of the combinational
circuits. This is to guarantee that correct data values are
captured by the latches.
V. P OWER GATING IN ASYNCHRONOUS MICROPIPELINE
In this section we briefly discuss the power gating tech-
niques in asynchronous miropipelines using sleep transistors.
Furthermore, using the optimized relay design (Section III)
a N/MEMS-based power gating controller is proposed. In the
following sections we briefly describe our approach, highlight-
ing the amount of
A. Conventional power gating in asynchronous micropipeline
The req_1 signal, as shown in Fig. 6 (b), is used as a
sleep control signal to turn off the CC block during its idle
state, or to turn it on during its active period. This will lead to
the use of so called ”just-in-time” computation. Consequently,
leakage current can be reduced during the inactive period, as
illustrated by Tof f in the timing diagram shown in Fig. 6 (a).
When the data is asserted, the request signal req_1 is raised
to high and passed simultaneously to both sleep transistors
and the DL block as a turn-on signal. This leads to powering
the CC block, and thereby the incoming data is accepted from
the data bus during Ton . The time required for the CC block
to compute the incoming data and give stable output values is
denoted as Teval . As the req_1 is passed through the DL
block, the handshaking controller 2 (H/S2 Ctr2) generates
the enable signal EN2 for the latches and Ack_1, which
is transmitted back to the handshaking controller 1 (H/S1
Ctrl). Consequently, handshaking controller 1 (H/S1 Ctrl) de-
asserts the req_1 signal once the Ack_1 signal is received,
and thereby turns off the CC block. It is reported that a
reduction of about 70% in the leakage energy dissipation
can be achieved by utilizing this approach compared to one
without a power gating technique [6]. It should be noted that
this study only evaluated leakage energy reduction without
taking into account the expense in energy overhead caused by
the effect of the power gating circuitry on the total energy
D_in
Combination
Latches
circuits
Latches
EN1 EN2
req_in
H/S req_1 Delay line H/S
Ctrl Ctrl
ack_1
ack_out
Figure 5: Asynchronous 4 phase bundle data micropipeline [6].
Req_1 D_in D_out
Ton Toff Comb.
Latches Latches
circuit
CC
EN1 EN2
Teval req_in GND req_2
H/S1 req_1 Delay line H/S2
Ctrl Ctrl
Ack_1 En2 = 1 ack_out ack_1 ack_2
(a) (b)
Figure 6: (a) timing diagram; (b) power-gated asyn. micropipeline [6].
dissipation. As a result, this approach can only be energy-
efficient when the energy saved is much greater than the energy
consumed in switching the power switch network (PSN) on-
and-off. Moreover, further energy savings of between 5% and
12% can be obtained by including the DL blocks in the power
gating domains [16], as shown in Fig. 7 (a). However, sleep
transistors have fundamental limitations in their effectiveness.
Therefore, the present research investigates using N/MEMS
for effective idle energy minimization.
B. N/MEMS power gating in asynchronous micropipeline
Further improvements to the previous paradigm can be
achieved by employing N/MEMS to power gate both the DL
as well as CC blocks, as can be seen in Fig. 7 (b). In this study,
An on chip charge pump for MEMS implementations has been
optimised to meet the requirement of the pull-in voltage of
any types of chosen MEMS. For example, It is found that
adopting a charge pump increases the delay overhead by 0.5
μs of the MEMS in Fig. 2, while it has a slight impact on
the energy overhead 0.5 pJ. The following two benefits can
be observed by adopting N/MEMS in the PSN of Fig. 7(b).
Firstly, unlike sleep transistors, N/MEMS switches exhibit
zero leakage current. To avoid any performance degradation,
especially in ultra low power applications, the width of sleep
transistors has to be made larger, which in turn leads to
significantly greater leakage current. Finally, fewer N/MEMS
than CMOS counterparts are required in both the DL block as
well as the PSN, due to its lower Ron than the sleep transistor
counterpart. When req_1 is de-asserted, the DL block will
be floating due to the disconnectivity period caused by the
long Tmech delay to turn-on the other N/MEMS in the buffer
circuit. Therefore, employing the AND gate, as can be seen
in Fig. 7 (b), is essential to ensure that the output of the DL
block is always driven by either logic low or logic high and
that it is never floating.
VI. E VALUATION SETUP
D_out
To validate the proposed approach as well as to find the con-
ditions at which power gating in asynchronous micropipelines
using N/MEM power switches becomes beneficial, 8- and 32-
tap FIR filters were designed. These FIR filters are imple-
req_2
mented using 90nm CMOS technology node, as shown in
Fig. 8. They consist of two combinational blocks including
ack_2
an accumulator and multiplier. Each combinational block is
powered by its own power domain, so that the multiplier is
161
 Vdd
Vdd
Power switch transistors MEMS power switch
Vdd PD Vdd PD

D_in D_out D_in D_out

Comb. Comb.
Latches Latches Latches Latches
circuits circuits

MEMS
EN1 EN2 EN1 Delay line
EN2

req_in
Delay line req_2 req_in Charge req_2
H/S H/S pump H/S
H/S req_1 req_1
Ctrl Ctrl Ctrl
Ctrl ack_1 ack_1 ack_2
ack_2 ack_out
ack_out (b)
(a)

Figure 7: Schematic illustration of power gating approach in asynchronous micropipeline using: (a) sleep transistors; (b) proposed N/MEMS.

Vdd Vdd
N/MEMS power switches N/MEMS power switches
Vdd PD1 (S1) (S2)
Vdd PD2

32 64 32 32 32 32
Multiplier A
Accumulator D Flip-flop
D Flip-flop
Data_in D Flip-flop Data_out

N/MEMS-based N/MEMS-based
EN0 EN1 EN2
Delay line Delay line
req_in req_0 req_1 req_out
Pipeline CP H/S CP H/S
Controller Ctr1 Ctr2
ack_out ack_0 ack_1 ack_in

Figure 8: Asynchronous 32-tap FIR filter implemented based on the proposed approach.

powered by power domain1 (Vdd PD1) while the accumulator Synopsys simulator the area, dynamic and static energy has
is powered by power domain2 (Vdd PD2). These two power been optimized. Finally, the two technology N/MEMS-CMOS
domains are powered by the main power supply voltage (Vdd ) are simulated using Cadence simulation tool.
through an array of PSN including S1 and S2 , as indicated VII. R ESULTS
in Fig. 8. The delay line (DL) blocks in each stage of the Our approach was evaluated and compared with various set-
micropipeline are connected now with the power domain ups in previous work [6] [17]. All these set-ups are powered
of the corresponding combinational circuit (CC) block. The by supply voltage with Vdd =0.6V. The number of PMOS sleep
acknowledgement signal ack_out is only generated when the transistors used in the PSN are S1 =20 with width=4um, and
controller receives a request signal req_in and performs N S2 =15 with width=4um. The total energy dissipation was eval-
handshake cycles with the micropipeline. Consequently, when uated and energy per computation was recorded. Furthermore,
the req_0 signal is placed high the switch array S1 will the total leakage energy (i.e. caused by DL, and CC) of each
turn on, thereby connecting the supply voltage Vdd to power set-up was recorded. Moreover, the overall energy overhead
domain1 (Vdd PD1). This leads to powering up the multiplier of the proposed approach caused by adding N/MEMS and the
and its corresponding delay line (DL) block. One branch of charge pump were evaluated. It should be noted that this filter
the req_0 signal bypasses the delay line (DL) block and will only works for a range of data rates which must not exceed the
be ANDed with its delayed signal, resulting in generating the natural throughput of the filter at Vdd =0.6V. Table IV shows
signal to be passed into handshaking controller1 (H/S Ctrl). the simulation results of 8-tap FIR filter at various setups.
The (Vdd PD1) can be powered down when the req_0 signal
It can be deduced from these results that decreasing the
is de-asserted, and this leads to placing one input of the AND
data rate from 1MHz to 1KHz will result in an increase in
gate in the floating state. However, the output logic of the
AND gate will be set at logic low by req_0. COMSOL
Device multiphysics
The flowchart of our evaluation process is presented in Fig. o dimensions
3D FEA
o geometry
9. Firstly, N/MEMS switch has been modelled and designed o material
simulator
o etc. VHDL code
using 3D FEA performed by COMSOL multiphysics tool. Pre- -Parametric sweep o FIR filter
Contact -Transient analysis o AES key generator
defined characteristics including dimension, geometric shape, modelling -Frequency analysis
o
material, and actuation type are used as an input to the o
Stiffness (k)
Damping (b) Synopsis-
simulator
COMSOL. As a result, the evaluation of the mechanical Extract device
o
o
Mass(m)
Pull-in Voltage (Vpi) synthesis
and electrical lumped parameters can be then obtained by parameters o Mechanical time
o Switching energy
performing frequency, transient, and parametric sweep anal- Optimize
Verilog-AMS o Dynamic and
ysis. These lumped parameters are written in Verilog-AMS (Electrical and static power
mechanical lumped o Area
and co-simulated in Cadence simulator, as illustrated in [15] model)
Results
[16]. From the other side, VHDL code is written for 32-tap o Total energy Cadence
o Timing
FIR filter which consists of two combinational blocks 32-bit o etc.
simulator

adder and 32-bit multiplier, as can be seen in Fig. 8. Using

Figure 9: Mixed electronics N/MEMS-CMOS evaluation process.

162
 Table IV: Total energy/computation for various asynchronous PG configurations. Table V: Energy consumption for 32-tap FIR filter at various asynchronous PG setups.

No PG With PG in [6] No PG With PG in [17] Proposed PG (MEMS)

Data- Leakage Total energy Total energy Saving Data- Energy Total energy Saving Total energy Saving
rate (KHz) (pJ) (pJ) (pJ) (%) rate(KHz) (nJ) (nJ) (%) (nJ) (%)
1 1351 2812 1940 31.0 1 6.778 4.10 39.5 2.10 69.0
10 134.3 283 217 24.9 10 0.80 0.49 38.0 0.30 62.5
100 12.90 41.0 33.0 18.14 100 0.60 0.41 31.0 0.31 48.3
400 3.277 19.8 20.6 -2.95 400 0.45 0.38 15.0 0.315 30.0
800 1.678 17.0 17.7 -7.56 800 0.389 0.35 10.2 0.32 17.7
1000 1.301 16.0 17.35 -8.40 1000 0.34 0.345 -1.4 0.32 5.80
10000 0.3 0.38 -26.0 0.45 -50.0
Table IV (continued): Total energy/computation for various asynchronous PG setups.

8
With PG in [17] Proposed PG (MEMS) 10
Without
PG
Data- Total energy Saving Energy (pJ) Total energy With
PG [16]
rate (KHz) (pJ) (%) (overhead) (pJ) MEMS
PG

Energy/computation ( J)
NEMS
PG
1 1601.9 43.0 3171 4640
10 172.6 39.0 336 464.9
100 30.9 24.0 52.5 81.70
9
10
400 18.6 7.0 28.8 45.90
800 16.8 -2.43 24.9 40.60
1000 16.5 -3.12 24.1 39.60

10
10
the dissipated energy/computation of the four set-ups. This 10
0 1
10 10
2
10
3
10
4

Data rate (KHz)

is attributed to the fact that leakage energy in the circuit
increases as the time required to complete a single computation
increases, leading to a longer circuit idle time. Although
MEMS relays exhibit zero leakage current, decreasing the
data rate (i.e, with longer computation time) will lead to a
significant increase in the energy, as shown in Table IV.
Table V and Fig.10 show the total energy consumption of
the 32-tap FIR filter implemented at various power gating set-
ups and data rate. All these set-ups are powered by supply
voltage with Vdd =1V. The number of PMOS sleep transistors
used in the PSN are S1 =30 with width=8um, and S2 =20 with
width=8um. The total energy consumption caused by the DL,
and CC of each set-up as well as the overall energy overhead
of the proposed approach caused by adding MEMS relays and
the charge pump were evaluated. These results indicate that at
low data rate our approach can achieve greater energy savings
about 69% compared with the one without-PG and 29.5%
with-PG [17]. This is attributed to the significant increase of
the leakage energy in the DL, and CC blocks. It is evaluated
that the leakage energy dissipation of DL blocks equal to
0.68nJ at data rate about 1KHz. However, increasing the data
rate will lead to increase Es of the MEMS-based power gating
which outweigh its leakage power savings. Due to its lower Es ,
NEMS at 45μm2 can achieve greater energy savings compared
to the existed MEMS, as shown in Fig. 10.
VIII. C ONCLUSION
This paper presents an investigation into power gating
techniques implemented on asynchronous micropipeline. This
study demonstrated the threshold at which these techniques
can achieve greater energy savings in relation to the design
architecture and data rate of the input. Future work, develop a
tool to automatically cluster the micropipeline stages with the
best power gating techniques by determining the static power
requirements and maximum allowable wake-up time.
Figure 10: Shows the total energy consumption for 32-tap FIR filter at various date rate
and different power gating configurations.
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