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Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 VLSI Basics

Extraction &
DFM Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other Index
Introduction
Corner) Modeling Layer Variation Topic Chapter 1: Digital Background
Chapter 2: Semiconductor background

Saturday, July 19, 2008 Chapter 3: CMOS Processing

Chapter 4: CMOS Basics

Antenna Effects Chapter 5: CMOS Layout Design

Antenna Effects: Featured Post

Modern wafer processing uses ‘Plasma etch’ (or ‘dry etch’). Plasma is an ionized/reactive gas used to etch. It allows super control of pattern Implant P+ Impurities: CMOS Processing (Part
(shaper edges / less undercut) and also allows several chemical reactions that are not possible in traditional (wet) etch. Apart from this, several 5)
unwanted things happen just because of several plasma processing steps. One of them is the charging damage.
Plasma charging damage refers to the unintended high-field stressing of the gate-oxide in MOSFET during plasma processing. The stress Implant P+ Impurities: CMOS Processing (Part 5) Index
voltage that develops across the gate and substrate of a MOSFET during plasma processing basically comes from three sources. Chapter1 Chapter2 Chapter3 Chapter4 ...

Non uniform distribution of plasma potential across the wafer.

Charging filtering (shading) due to microscopic topography on the wafer.
AC effects due to the nature of RF discharge that sustain the plasma.
The stress voltages due to AC effects are quite small in most cases and cannot cause damage by themselves. They do, however, add to the
magnitude of stress voltages developed by either non-uniform plasma potential or topographic filtering of charge or the sum of both.

The available charges are the net charges collected from the plasma by the exposed conductor with connection to the gate or substrate. Both
electrons and positive ions from the plasma are impinging on the exposed conductor during processing. Depending on the charge balance Vlsi expert
condition, the electron flux might not equal the ion flux, a net positive or negative charge collection rate exists. The collected net charges are Like Page 5.4K likes
channeled to the gate as shown in fig. 1 where it is neutralized by the current tunneling across the gate-oxide.

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Clearly, the size of the conductor exposed to the plasma plays a role in determining the magnitude of the net charge collection rate and therefore
the tunneling current. This is the so called “antenna effect”. The area ratio of the conductor to the oxide under the gate is the antenna ratio. The Follow
antenna ratio, in a rough sense, is a current multiplier that amplifies the tunneling current density across the gate-oxide. For a given antenna
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ratio, a larger tunneling current is supported when the plasma density is higher. Higher tunneling current means higher damage.
This antenna effect can be understood in a different way also. It occurs during the manufacturing process and renders a die useless. During
metallization (when metal wires are laid across devices), some wires connected to the polysilicon gates of transistors can be left floating
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(unconnected) until the upper metal layers are deposited. A long floating interconnect (without proper shielding layer of oxide) can act as a
temporary capacitor, collecting charges during fabrication steps, such as plasma etching. If the energy built up on the floating node is suddenly
discharged, the logic gate might suffer permanent damage due to transistor gate oxide breakdown.
6,223,108
In other word the 'antenna' is an inter-connect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon, i.e., not
'grounded', during the processing steps of the wafer. The connection to silicon would normally provide an electrical path to bleed-off any
accumulated charges. If the connection to silicon does not exist, charges and may build up on the inter-connect to the point at which rapid
discharge does take place and permanent physical damage results, e.g., to MOSFET gate oxides. This destructive phenomenon is known as the
'antenna effect'.
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"Timing Paths" : Static

Timing Analysis (STA)
basic (Part 1)

Basic of Timing
Analysis in Physical
Simplification: Design
Charge builds up (DC) on the metal wires (antenna) during the application of the plasma etch
Because the gate of a MOSFET is like a capacitor "Setup and Hold Time"

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The gate is damaged irreparably ► 2018 (4)
"Examples Of Setup ► 2017 (14)
The 'antenna ratio' of an inter-connect is used to predict if the antenna effect will occur. 'Antenna ratio' is defined as the ratio between the physical and Hold time" : Static
area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected. A higher ratio implies a Timing Analysis (STA) ► 2016 (11)
greater propensity to fail due to the antenna effect. This can result either from a relatively larger area to collect charge or a reduced gate oxide basic (Part 3c)
► 2015 (15)
area on which the charge is concentrated.
"Setup and Hold Time ► 2014 (15)
Violation" : Static
Timing Analysis (STA) ► 2013 (12)
basic (Part 3b) ► 2012 (15)

Delay - "Wire Load ► 2011 (17)

Model" : Static Timing ► 2010 (5)
Analysis (STA) basic
(Part 4c) ▼ 2008 (1)
▼ July (1)
Delay - "Interconnect
Delay Models" : Static Antenna Effects

Charge Build up is affected by: Timing Analysis (STA)

basic (Part 4b)
Diffusion path
There is an NP diode to substrate at the drain/source of any output pin
"Time Borrowing" :
During plasma-etch this diode is reverse biased and at high temp Static Timing Analysis
This causes the diode to behave like a resistor (STA) basic (Part 2)
Gate Area
Larger gate_area == larger gate ‘capacitor’ 10 Ways to fix SETUP
At fixed ‘charge’, voltage potential reduces as cap size increases and HOLD violation:
Static Timing Analysis
Reducing the voltage prevents ‘punch through’
(STA) Basic (Part-8)
Diffusion Area
Bigger diffusion == Smaller resistor 5 Steps to Crack VLSI
Smaller R allows more current to pass Interview

Wire length
Longer wires act as antennas to ‘pick up’ more charge
EDN Feed
The conditions that lead to antenna formation depend on the technology used to fabricate the chip and must be determined empirically for each
process. Once they have been identified, they can be used to define a set of antenna rules, similar to conventional DRC rules, that can be coded. Expect glitches… Is
your design
Factors these rules need to consider is whether the antenna should be based on the "top" area of the metal or on its "sidewall" area.
validated? -
In an aluminum-based process, charge accumulation occurs during the ETCH step. The top of the metal is protected by a resist
How to sculpt a
during this step, so the antenna rules for this process should be based on the metal sidewall area. 16-core 2 GHz
In copper-base technologies, charge accumulation occurs during CMP (Chemical-Mechanical Polishing). In this process, the sides of processor -
the metal are protected, so the antenna rules need to be based on the metal's top surface area. Parasitic extraction
must solve advanced
A number of techniques can be utilized to minimize the antenna effect. For example, the occurrences of antennas can be predicted and their node issues -
ratios calculated using design verification and layout software known as 'design rule check' ('DRC') programs. Then by adjusting the physical Analog IC co-design
layout of the inter-connects, the antenna ratios can be reduced to an acceptable level. In addition, processing steps utilizing plasma can be for latch-up
optimized to reduce the build-up of charges on any antennas that do exist on devices. compliance -
To avoid antenna problems, you must design all net topologies so that no gate is vulnerable to a large amount of floating charge. Antenna rules Is 5 nm testing the
are commonly expressed as a ratio of wire area over gate area (Aw/Ag) for each metal and cut (via) layer. This ratio indirectly states how much same or different? -
floating charge a transistor gate can handle by specifying how much wire can be connected to the input of the logic gate before antenna problems
occur. Recent Visitors

Design Solution to reduce Antenna Effects:

Router options Video Lectures
Break signal wires and route to upper metal layers by jumper insertion
All metal being etched is not connected to a gate until the last metal layer is etched.
Dummy transistors
Addition of extra gates will reduce the capacitance ratio.
PFETs more susceptible than NFETs
Problem of reverse Antenna Effects. Followers
Embedded Protection Diode
Connect reverse biased diodes to the gate of transistor (during normal circuit operation, the diode does not affect Followers (508) Next
functionality).
Diode insertion after placement and route
Connect diodes only to those layers with antenna violations.
One diode can be used to protect all input ports that are connected to the same output ports.

Follow

Most important methods are jumper insertion and diode insertion to remove antenna violation. We are discussing these two methods here in
detail.
Jumper techniques are the most effective method of avoiding antenna-effect problems. Diode insertion can repair the remaining antenna
problems. However, it is costly in terms of cell area size and it complicates the netlist verification process.
Jumper Insertion:
A jumper is a forced layer change from one metal layer to another, and then back to the same layer. Jumper insertion breaks up a long wire so
that the wire connected to the gate input is shorter and less capable of collecting charge, as shown in Figure. The advantage of jumper insertion
is that it is fully controlled by the routing tool. The disadvantage is that it can potentially contribute to routing congestion problems in upper metal
layers. There are also situations for which there are no valid jumper solutions.
Figure : Jumper Insertion Breaks Up a Long Wire

In most of the tools, jumper insertion is performed automatically during the routing. After detailed routing, you can fix antenna violations manually
by inserting jumpers by using commands corresponding to the tool you are using. When you execute those commands, tool detects and fixes
antenna violations using jumpers and a tailored ripup and reroute strategy.
The Importance of Jumper Location in Repairing Antenna Violations
Figure shows two nets with the same separation between the input and output pins, but slightly different jumper locations. The first one has an

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The difference is that the first net has a long metal1 connection to the input pin. The wire area as detected by the input pin of the first net is
significant, and, therefore, the antenna ratio is exceeded.
This example shows that antenna violations can be avoided through the use of jumpers (also known as “bridges”). A jumper directs the net to a
higher metal layer before descending again. In the process of metallization, the pin is connected to a small amount of wire area, except on the
highest layer, avoiding any antenna problem below that layer.
Unfortunately, the use of jumpers might only defer the antenna problem to the highest metal layer of the jumper, where antenna violations might
still occur because all geometries of the net are physically connected to each other. For this reason, it is important that the output pin have some
ability to solve antenna violations.
Diode Insertion
Figure : Diode Inserted Near a Logic Gate Input Pin

As shown in Figure, diode insertion near a logic gate input pin on a net provides a discharge path to the substrate so that built-up charges cannot
damage the transistor gate.
Unfortunately, diode insertion increases cell area and slows timing due to the increase of logic gate input load. Moreover, diode insertion is not
feasible in regions with very high placement utilization.
In most of the tools, diode insertion is performed automatically when you use the routing command. You can manually insert diodes using the
corresponding tool’s commands. There are two points in the design flow where you can insert diodes to fix antenna violations.
Inserting Diodes Before Detailed Placement
Normally, the diode is added only to the pins that need it. The antenna checker is called for each pin in question to decide first, if the pin has
antenna violations and second, if a jumper has failed in the area of the pin because the area is blocked and a large enough hole does not exist.
Inserting Diodes After Detailed Placement
After detailed routing, the antenna violations can still exist for various reasons. For example, there can be too much congestion to insert a jumper
or the diffusion strengths of the output pins are too weak. In these cases, diode insertion is a viable choice.
The semiconductor manufacturer generally provides the gate area or size, and the antenna checker calculates the appropriate wire area using
the wire (charge) accumulation method specified by the manufacturer.
Design Rules for Some Current Technologies –TSMC 0.18um
Metal antenna ratio is not cumulative.
Maximum drawn ratio of field poly perimeter area to the active poly gate area connected directly to it 200.
When the protection diode is not used, the maximum ratio of each metal (for M1 to M5) perimeter area to the active Poly gate area
400.
Antenna Ratio = 2[(L+W1)*t]/W2*l
L: floating metal length connected to gate
W1: floating metal width connected to gate
t: metal thickness
W2: connected transistor channel width
l: connected transistor channel length
Design Rules for Some Current Technologies –IBM 0.13um
Antenna ratio is non-cumulative.
Poly antennae larger than 100 are NOT ALLOWED
Floating gate devices with metal antennae larger than 150 are NOT ALLOWED
Every N-well is required to be tied down by a N+ diode
Antenna Rules:
In most cases, antenna rules are in the form of:
(antenna-area) / (gate-area) < (max-antenna-ratio)
Gate-area
Boolean AND of the ‘poly’ and the ‘diffusion’ layers
Recognized as gate area of the transistors by essentially all foundries
Antenna-area
Amount of metal area attached to the input pin
Calculation method varies for different processes
Max-antenna-ratio
Represents max allowed ratio of antenna area to gate area
Calculation method varies for different processes
There are 2 ways to calculate antenna area:
Side-Wall Area = (W + L) * 2 * Thickness
Polygon Area = W * L
Calibre antenna rules
M6_DIO = NET AREA SD >= 0.16
A.R.4_A.R.6.M6
{ @ (M6 area / gate area + ACCUMULATE ) > (600 in OD2, 5500 not in OD2) (without effective diode)
@ (M6 area / gate area)+ ACCUMULATE > Ratio (with effective diode)
NET AREA RATIO M6 M6_DIO HV_GATE GATE > 0 ACCUMULATE ACC_M5
[
!!AREA(M6) * !!AREA(GATE) *
(!AREA(M6_DIO)*(!!AREA(HV_GATE)*(AREA(M6)/AREA(GATE)-600) +
!AREA(HV_GATE)*(AREA(M6)/AREA(GATE)-5500)) +
!!AREA(M6_DIO)*(AREA(M6)/AREA(GATE)-AREA(M6_DIO)*456-43000))
- (!AREA(M6)+!AREA(GATE)) * LargeNumber
]
}
ACC_M6 = NET AREA RATIO M6 GATE >= 0 ACCUMULATE ACC_M5
Magma antenna rules:
rule antenna ratio metal_rule $l -area_type area -accumulation_type path \
-ratios {{{{0 600 0} {0.16e-12 43072.96 456e12}} {METAL6}}

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-diode_mode \
-metal_ratio \
-cut_ratio
define_antenna_layer_rule -mode \
-layer \
-ratio \
-diode_ratio <{v0 v1 v2 v3 [v4]}>
Summary:
During the IC manufacturing process, the metal layer is exposed to conditions that lead to the build-up of an electrostatic charge. The amount of
charge that builds up depends on a number of factors; the most important from an antenna standpoint is how much metal is exposed. As more
metal is exposed, the maximum charge that accumulates on the net that the metal is part of also increases. The substrate remains at ground
since it is connected to the fabrication device. As a result a voltage gradient develops across the gate oxide. When this gradient becomes large
enough, it is relieved via an explosive discharge (i.e. "lightning"). The problem is more significant at smaller technologies because the damage
resulting from the discharge is more likely to extend across the entire length of the gate.
Antenna rule checking is different for every process technology because the method for expressing antenna ratio is not standardized.
Antenna repair is accomplished by inserting a reverse-bias diode on the violating net as close to the gates being protected as practical. During
normal chip operation, the reverse bias prevents electrons from flowing from the net through the diode and into the chip's substrate. During
fabrication, however, the charge on the net can build to the point where the voltage drop across the diode exceeds its break-down voltage. This
voltage is greater than the normal operating voltage, but less than the voltage at which an electrostatic discharge at the gate can be expected.
When this happens, the diode allows electrons to flow from the net to the substrate and thus limits how much charge can accumulate on the net.
The process is non-destructive, and it's possible that the net could discharge through the diode several times during the fabrication process.
The other way to repair is to "break up" the antenna by shifting briefly to a different metal. When this metal layer is fabricated, the long piece on
one side is no longer electrically connected to the gate and does not contribute to any antenna effects. When it is eventually connected through
the higher-level metal "bridge," it is no longer exposed to the charge accumulation and again does not contribute to an antenna violation.
Causes of antenna defects:
Electrostatic charge collection on wires while the metallization is being deposited. (This is usually referred as ‘charge-collecting
antenna problem’ or simply antenna problem)
Most important ways to repair the antenna violation:
Using jumpers to break up long wires connected to gates (Jumpers are a short metal segment inserted onto a long route of another
metal layer).
Using diodes to provide a discharge path to the substrate by contact to a diffusion area.

Posted by VLSI EXPERT at 1:10 PM

Reactions:

70 comments:
Anonymous February 5, 2011 at 11:14 PM

I seldom leave comments on blog, but I have been to this post which was recommended by my friend, lots of valuable details, thanks again.

Reply

your VLSI February 10, 2011 at 4:13 PM

Hi,
Nice to here that you like this Post. Please keep visiting my blog and let me know if you need anyother specific detail.

Reply

Replies

ankit goyal April 1, 2013 at 3:36 PM

If you can write something on verilog than it will be great

Reply

Anonymous March 17, 2011 at 2:33 PM

seems you have worked in all eda companies.. gr8

Reply

qa May 16, 2011 at 10:57 PM

great work , cheeeers , certainly good for the freshers

Reply

your VLSI May 20, 2011 at 11:24 AM

thanks qa

Reply

iam August 1, 2011 at 6:55 PM

Amazing knowledge...well written to...

Reply

Sujata September 26, 2011 at 8:33 AM

Thanks a lot for sharing . I couldn't have understood the concept better from any other source.

Reply

Anonymous October 4, 2011 at 4:35 PM

thanks for the detailed explanation...:-)

Reply

Anonymous November 23, 2011 at 4:38 PM

Really, Very good and detailed explanation.

Good no. of ways has been mentioned to overcome the ANTENNA effect.

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Reply

$@$! December 29, 2011 at 1:04 PM

Excellent analysis and great presentation.

Reply

Anonymous January 3, 2012 at 12:39 AM

Kudos to you for giving such detailed and graphical explanation of this topic. I understood many concepts related to Antenna problem because of this.

Reply

Anonymous January 5, 2012 at 12:24 PM

thanks

Reply

Anonymous January 25, 2012 at 12:22 AM

thank you so much,i would like to know what will happen for hanged metal1 it will not find any discharging path na after metal2 fabrication it may aid the
charge on metal1(hanged)and metal2 and hence may damage the gate oxide na??can you pls clarify more on it..Thanx in advance.

Reply

Replies

your VLSI January 26, 2012 at 7:46 AM

You are right. So if the metal1 has too much charge that it can damage the gate oxide, it will do that but if that's not the case then it will wait
for metal2 and then metal3 and so on.
So the point is the moment accumulated charge is sufficient to destroy thr gate oxide, it will do.

Reply

Unknown February 10, 2012 at 11:10 AM

can u giv me a lnk for documentation,ppt and abstract for this topic..i would lik to giv a tech seminar on this...wil it be good ?

Reply

Replies

your VLSI February 10, 2012 at 11:30 AM

hi Unknow,

Its very difficult for me to give you any ppt right now. Because I don't have anything handy currently. Apart of my blog, may be wikkipedia
website can help you.

http://en.wikipedia.org/wiki/Antenna_effect

Sorry man - That I am unable to help you regarding this right now.

Reply

Unknown February 10, 2012 at 11:11 AM

can u giv me a lnk for documentation,ppt and abstract for this topic..i would lik to giv a tech seminar on this...wil it be good ?

Reply

VLSI fan February 21, 2012 at 11:43 AM

its very usefull for me thank you ........ can u plz explain me wht propotion use in anteena effect.........

Reply

Anonymous March 7, 2012 at 2:54 PM

its very usefull to understand anteena concept Good work, any other blogs.

Reply

AD April 10, 2012 at 10:37 PM

Hi
This article is really very nice and it helps me to understand very clearly.
I have a QUESTION : In some articles i have red, when a tool puts a jog on metal then it takes a higher or one above metal. But not lower or one below
metal. why? Would you please explain me.

Thanks
AD

Reply

Replies

holla June 4, 2014 at 6:21 PM

no u can not go to lower level metal c because whn the gate s connected by M2 and ur getting antenna error.
if u go for jumper of m1 near the gate, M1 s fabricated first and then M2 so v r getting error from M2 , M1 and M2 are connected and that
may harm our gate.
If u go for jumper of m3 near the gate, M2 s fabricated first as a two piece near the gate and after the jumper.
den we fabricate m3 so charges in m2 s removed before m3 fabrication, so it will not harm the gate.

Anonymous March 23, 2017 at 3:04 PM

Nycc Explanation... thanks alott...

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sangeeta April 25, 2012 at 3:58 PM

Hi,
Thanks a lot.
good explanation.

Reply

Neethu A July 8, 2012 at 4:48 PM

Hi, if we are connecting the antenna metal to higher metal,the top metal still contributes to antenna effect right?

Reply

Replies

your VLSI July 10, 2012 at 2:30 PM

Yes. You are right

Anonymous August 23, 2012 at 8:46 AM

See,there will be a small chance that top metal will not contribute to the antenna.This is because top metal length used as jumper is
small.Unless top metal, which is used in the same net(of lower metal ,suffering antenna) and used in different location ,add up to cross
antenna ratio for that metal layer(top metal),it will not not happen.

Reply

kishan November 4, 2012 at 7:06 PM

Hello Expert

I have one more doubt regarding antenna effect

if one of the metal is connected to drain and other end connected to
gate (ex inverter connected to another inverter ) is there a need for
antenna protection ?? because one end is connected to diffusion which
by default has a parasitic reverse bias diode (bw diffusion and
substrate) so i feel it is protected by default am i right ?

Reply

Replies

your VLSI November 8, 2012 at 12:46 PM

Kishan,
You have to go for Antenna protection in this case also. See in layman language - why there is a problem. Whenever (even for a instant) if
there exist enough charge on the gate (which comes from the wire) which can damage it - we should go for the Antenna protection. Now the
other end can be connected to anywhere - It doesn't matter. It all matter how long the wire is -- if wire is too long and after that its connected
to ground - even in that case there may be a problem of Antenna.

Actually these problems comes during the fabrication- so these have no major relationship with the logical connection and whatever you are
talking .. is the logical connection.

I hope you got my point. Still if these is any doubt - feel free to post here.

kishan November 9, 2012 at 10:29 PM

kishan November 9, 2012 at 10:43 PM

Thanks a lot expert but first step in fab is substrate, diffusion, poly and metal so a reverse bias diode is already formed there which can
breakdown at high reverse voltage and form a low impedance path to substrate so dont the charges leak away during the process?

Thanks and regards

holla June 4, 2014 at 6:12 PM

yes.. we dont need diode or jumper in dis case. It will go through the diffusion. we need diode only when the gate s connected by M1(lower
layer) and drain s connected by M2(higher layer) and antenna error s from M1(lower layer) in dis case only v need diode or jumper.

Sagar Patel July 23, 2014 at 3:02 PM

Hi Kishan,

Suppose the net is routed through M1-M5 layers and it's having antenna violation on M3.
So while M3 is manufactured there's excess charge on it. But M4 and M5 aren't manufactured yet. So the piece of net on M3 which is
having excess charge, isn't connected to the driver's output pin (diffusion) yet. Hence there's no path for the charge to go into the diffusion.

By the time M4 and M5 are manufactured, the charge on M3 is already grounded (I don't know exactly how though), and there's no antenna
violation anymore.

Correct me if I am wrong somewhere.

Thanks,
Sagar

Reply

Anonymous November 26, 2012 at 1:13 PM

hi,

may i know in a design with seven layers is there any chance of getting antenna violations at seventh layer..
say if exists then how to overcome with that violations
as there is no room to insert diode.. what could be the other chance of removing it.. please let me know..

Reply

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your VLSI November 27, 2012 at 12:30 PM

there are chances -- any where and any layer -- that's the reason you can see that the foundry have rules for all the layers...
Now for such violations always prefer jumpers.

"Using jumpers to break up long wires connected to gates".

Its a mostly recommended methodology - that for M1 or Max M2 - Use Diode and for upper layer use Jumpers.

Reply

Anonymous January 29, 2013 at 11:24 PM

Hello,

I have a question about the antenna rules....i hav observed that the topmost layer will have the antenna ratio very less [0.1]...can you pls tell me why is
that ? All other layers will have antenna ratios as 200,300 etc...But why only Top most layer has less ratio ??

Reply

Anonymous May 7, 2013 at 11:29 AM

Really helpful thank you for sharing it !!!

Reply

Anonymous May 13, 2013 at 7:48 PM

very much helpful, well explained, cleared most of my doubts on antenna effect

Reply

mayank gupta September 30, 2013 at 2:16 PM

Reply

Anonymous October 3, 2013 at 8:57 AM

Superb xlanation...thank u

Reply

Anonymous February 24, 2014 at 5:09 PM

Hi experts could u plz explain detaildly regording antenna dide working. .

Thanks in advance.
Regards,
Siddharth.

Reply

Anonymous March 19, 2014 at 12:16 AM

Really good explanation to understand the Antenna Issue, I have one question, I have antenna Violation on Top Metal Layer and my design is very
congested so I can not put the Antenna Diode. Usually for Jumper you move to higher metal layer and then come down to lower metal Layer. In this
scenario can Jump to Lower metal Layer and then again going back to Top metal layer will fix the Antenna Violation or we need to try something else.

Reply

Replies

holla June 4, 2014 at 6:03 PM

no u can not go to lower level metal and then to top level.. c because whn gate s connected to m3 that s done first after the m4(consider top
layer) is done. so both are connected and error is coming from m4(top layer). so u hav to connect a diode or try to reduce the length of top
layer.

Reply

PREETHESH K May 8, 2014 at 12:15 AM

Nice explanation. No need refer anything else for understanding Antenna effect. Nice work !!!!

Reply

Anonymous May 27, 2014 at 11:43 PM

I think you guys did an excellent job explaining the antenna effect. I will be looking forward to more information
as a layout technician. This will continue to help me emensely. Great Work!! and Thank You

Reply

Krishna Soorannavar June 16, 2014 at 12:24 PM

Reply

Anonymous June 16, 2014 at 12:26 PM

Great explanation......:)
This data much better than Art of Analog Layout - Alan Hestings

Reply

srinivas June 28, 2014 at 7:39 PM

Thanks alot...:)

Reply

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Anonymous September 10, 2014 at 6:14 AM

Could you expalin how to choose diode specifications or layout area for Antenna effect?

Reply

Anonymous October 10, 2014 at 10:36 AM

Can you please explain the detailed operation of antenna diode ???

Reply

Replies

Anonymous October 10, 2014 at 10:40 AM

Yes, i too need some explanations regarding the operation of antenna diode.

Reply

Anonymous December 1, 2014 at 5:16 PM

can you please tell me why higher metal layers doesnot accumulate charge ?

Reply

Anonymous August 27, 2015 at 1:30 AM

I just get artictle about tunnel diode, if you need to get more information about this electronic device check this.

Reply

Anonymous December 2, 2015 at 5:41 PM

Hi

A great article to understand antenna effect. Thanks for the detailed explanantion.
I have one query regarding use of antenna diode. What type of diodes are prefarable(p+/n+ diode)? and How are we connecting it?

Thanks

Reply

Replies

Sanam December 30, 2015 at 11:58 AM

Hi,

We prefer NMOS devices as the diodes. Source and Drain connected to antenna affected signal, Gtae and substarte are connected to
GND.

Reply

Sanam December 30, 2015 at 11:56 AM

Please explain the antenna diode functioning in detail?

Reply

Anonymous February 8, 2016 at 1:59 AM

cheers.. keep-up the good work!!!!

Reply

Unknown February 12, 2016 at 2:45 PM

I have one doubt on diode insertion in reverse bias for antenna effect. why we have to connect diode in reverse bias only. pls explain

Reply

Unknown March 2, 2016 at 8:43 AM

Nice gd explanation

Reply

Abubacker Siddique March 4, 2016 at 6:12 PM

Can you please explain the three sources of the stress voltage mentioned ?

Reply

Madhu Swamy March 9, 2016 at 5:29 PM

Hii,

while calculating the maximum antenna ratio in the formula, i have seen a parameter called "Diode Protection" (DP) value, when diodes are used for
preventing antenna violations. it would be very helpful if you could explain that. i have read somewhere, it is a ratio that can range from 0 to 1e6. can
you please tell me whats that ratio is and how the value is determined for preventing violations.

Thank you very much for this post.. very useful

Reply

Unknown May 20, 2016 at 3:51 PM

Hi, nice explanation for Antenna effect given. But i coundt get the Operation of the Antenna Diode, in this scenario. Is is a shottkey diode/tunnel diode ?
or a normal diode, which will be damaged if it conducts in reverse bias.

Reply

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Hi,
nice to read this, got idea what is antenna effect, causes and remedies but i didn't get the functionality of inserting diode i mean how it is operate. can u
please explain in detail operation of inserting diode

Reply

Akhil November 4, 2016 at 12:51 PM

Super information

Reply

RAJKUMAR MANDAL September 13, 2017 at 10:33 AM

Nice post. got enough information about antenna.

Reply

priyanka priya September 26, 2017 at 6:41 PM

Provide reason for disabling antenna violations upto postroute stage by adding diodes

Reply

priyanka priya September 26, 2017 at 6:42 PM

Provide reason for disabling antenna violations upto postroute stage by adding diodes

Reply

Anonymous November 12, 2017 at 12:46 PM

Hi,
Thanks a lot for such a nice explaination.
I have a doubt. If there is an antenna violation in metal 1 means metal 1 has charge accumulated in it and to remove it, it is connected to M2 then again
M1.But Charge can still flow as all are metals connected to each other through via. So how this jumper is used as a remedy for antenna effect. Please
reply.

Reply

Anonymous March 16, 2018 at 6:49 PM

Appreciate this post. Will try it out.

Reply

Anonymous May 11, 2018 at 3:38 AM

Howdy! Would you mind if I share your blog with my twitter group?
There's a lot of people that I think would really enjoy your content.
Please let me know. Than you

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