28nm Synopsys PDF

IC Compiler 32/28nm Webinar Series
28nm Silicon And Design Enablement
The Foundry And EDA Vendor

Perspective
JC Lin
Vice President R&D
IC Compiler
©Synopsys 2010 1 IC Compiler 32/28nm Webinar Series

Today
Done 32/28nm Design Challenges
Addressing 32/28nm Design

Done
Challenges
Fastest Time to Tapeout
Done
with IC Validator
Realizing Today’s 32nm
Done
and Beyond Large Designs
Manufacturing-Aware
Done
Routing
Extraction For
Done
32/28nm
28nm Silicon And Design Enablement
Today’s Topic
A Foundry And EDA Vendor Perspective

Welcome!
JC Lin
Vice President, R&D
IC Compiler
Synopsys

32/28nm Design Enablement
• Overview of Synopsys Solutions At 32/28nm
• Featured Technologies
– In-Design STA: Final-stage Leakage Recovery
– In-design physical verification: Automatic Litho-repair

Using Pattern Matching Technology

Synopsys Solutions At 32/28nm
Variability Low Power

Galaxy
• High accuracy • Comprehensive flow
• MCMM throughout the • Major advances in
flow 2010.03 and 2010.12
PrimeTime/StarRC
Design
Compiler
Enhanced Manufacturing
IC Validator Design Complexity
Compliance
• Routing, Physical • Runtime speedup

IC • 40M+ design handling
Verification & Test
Compiler
Production proven across 32/28nm process nodes

Leading The Way In Tapeouts At 32/28nm
100 @ 32/28nm
90
80
70
60
50
40
30
20
10
0
Q4'05
Q1'06
Q2'06
Q3'06
Q4'06
Q1'07
Q2'07
Q3'07
Q4'07
Q1'08
Q2'08
Q3'08
Q4'08
Q1'09
Q2'09
Q3'09
Q4'09
Q1'10
Q2'10
First to 45nm, First to 32nm

High Accuracy Flow Reduces Margins
Critical For Convergence At 32/28nm
Device & Delay RC models & Net

Advanced OCV
Models Topology
Composite Current Source Models (CCS) Driver Reduced Order Receiver
Model Network Model Model
U
2
A
Y U3
Output current waveform in library
U1
slew Current vectors
0.7
0.5 U4
0.2 output
0.1 • NLDM • Elmore • NLDM Depth 1 2 3 4 5 6
cap
.023 .047 .065 .078 .091 • CCS • Arnoldi • CCS Derate 1.2 1.2 1.15 1.15 1.08 1.08

Concurrent Multicorner Multimode
Reduces Uncertainty At 32/28nm
New: MCMM
Multicore Support RTL to Layout
CTS/CTO
Full Flow MCMM with SI Design
6
1-core 4-core Compiler
5 Design FCLK
Planning
Multi-Voltage
4 TCLK
MCMM
3
Placement
2
CTS
1
Routing
0
2009.06 2010.03 2010.12
Comprehensive MCMM support - faster TAT, best QoR and easy to use

Enhanced Reliability At 32/28nm
Preventative EM & Integrated IR Flow
Electromigration In-Design PrimeRail

Aware CTS IC Compiler Integration
Y
User provided
X X
X-Y padding Manufacturing
Y Error Browser
identified missing via
Before EM-Aware CTS After EM-Aware CTS
Clock cell
Based on guidance
IC Compiler adds in the
missing via
Logic cell Logic cell Clock cell
Comprehensive flow addresses EM & IR issues

Comprehensive Low Power Flow
Multi-Voltage And UPF Support
Improved Multi-voltage
MV Support
Productivity - UPF Aware Opt.
RTL Top
• Auto-insertion of LS/ISO UPF

Bot
Mid
cells Design Compiler

• Disjoint VA and Always-
Gate
Logic View
On Synthesis UPF’
SD PD
AO (VA’)
• MV-aware power IC Compiler
network synthesis AO (VA”)
Gate
• MTCMOS power gating Gate (PG) UPF”
Physical View
Production proven automated flow produces best QoR

Low Power CTS
Complete Support At 32/28nm
New In 2010.12 XOR Clock Gating Datapath For CTS
 Smart selection of buffers vs. data[0:7]

0 0
inverters
 Power driven sizing
 Intelligent clock net layer 7 7 dly[0:7]

selection clock I
C
G
 Target transition relaxation Datapath ICG

= 10% reduced power OOTB Extra 10% reduced power placement & routing
~30% less power
Significant clock tree power savings for high-performance designs

Best Leakage QoR
MCMM Aware, Handles More VTs
MCMM
Physical Flow In-Design STA
Throughout
180 20%
ICC Only MCMM
160 18%
140
DCG+ICC
MCMM
16% Place Opt
%Improvement 14%
120
Power (mW)
12%
100
80
10%
Clock Opt
8%
60
6%
40 4%
Route Opt Final-stage
20
0
2%
0%
Leakage Recovery
Customer Designs
Optimizing leakage and other Delivers Maximum

On average 7% better leakage costs through the flow Leakage Savings
Better leakage and timing - faster convergence at 32/28nm

Faster Design Exploration
20M Instances In One Day
Exploration Faster
Virtual IPO
Placement Global Route
fanout
43 32
VIPO
43 32
plangroup plangroup 2
1
47
budgeted
Coarser placement no legalization Global routing results output delay
25M instances in 1 hour see top-level congestion early Provides early look at timing QoR
2X Faster initial floorplan creation

Feasibility Flow
Faster & Easy To Debug
Feasibility Categorized
Check & Report
Optimization Reports
Timing Histogram
(baseline, feasibility)
Infeasible
paths
Optimization on
feasible paths
masked
• User customizable • 2X faster place_opt & • HTML links to reports and/or GUI for
• “What Next” recommendations 1.5X clock_opt to assess dirty SDC debug
Increased designer productivity in the early stages of the design

Faster Hierarchical Design Planning
On Demand Loading Technology
On-Demand Top-level
Loading Designers View
Original On-demand
netlist netlist
1.8M Cells 50K Cells
Removes internal logic within partitions to place Top level design has the top level and
& optimize interface logic interface cells to route & time (GUI)
2.8X runtime and 2X memory improvement

32/28nm Rule Formulation & Support
Placement Rules Routing Rules Soft Rules
Soft rule for

wire spacing
2x  H S
1x 
Yield
Standard Cell Example: 3-neighbor, end-
Yield vs.
of-line via-enclosure rule
Filler Cell spacing plot H S Spacing
Supported by leading foundries and major IDMs

Zroute – Manufacturing-Aware Router
Tapeout Proven At 32/28nm
Manufacturing Multicore Delivers

Core Technology
Compliant 3X Speed-up
Realistic Dynamic Maze
Connectivity Grid
Multi-threaded
Dynamic
Grid
Virtual
Wire
Redundant Vias Wire widening &
spacing
Advanced Design
Rules Polygon Manager
0.6S X Y
S Z
S
0.6S W
S
# of Cores
Litho friendly routing
3X Speed-up, higher QoR, better manufacturability

In-Design Physical Verification
Improved Productivity For The Physical Designer
In-Design DRC In-Design Metal Fill In-Design LCC
Auto-Repair Timing-Aware
Signoff Quality 10x Faster

Automatic
litho-repair using
Incremental Highest Density pattern matching

– In-design physical verification: Automatic Litho-repair

Using Pattern Matching Technology

Leakage Trends At Advanced Nodes
ITRS Leakage Power Projections MOSFET Leakage Current Components
• Sub-threshold leakage current dominates total leakage power

• Advanced nodes require new techniques
– Leakage QoR with leakage variants (eg. Channel-length variation, multi-Vt)
– Managing increasing leakage variability
Need to approach leakage optimization from a device modeling perspective

Leakage QoR With Leakage Variants
Channel-Length Variation, Multi-Vt Libraries
• Increasing channel length is also referred to as CD biasing

• Besides Vt variants, leakage reduction is possible by increasing gate length
• Potential foot-print equivalent leakage variants in standard cell libraries
Example: 3 different leakage variants of a NAND3 with CD biasing
OUT OUT OUT

A1 A1 A1
A2 A2 A2
A3 A3 A3
Significantly reduced impact on No impact on most timing with For most effective
top-pin-to-out timing with some leakage reduction leakage reduction
considerable leakage reduction

In-Design STA -- Final-Stage Leakage
Recovery
• Architected for 15+ channel- Final-Stage Leakage Recovery
length based leakage variants
400
and Vt libraries
Before After
Leakage Power (uW)

• Used on “final” netlist for leakage 300
62%
recovery Less
• Reduces leakage while preserving 200
48%
signoff timing/DRC Less
• Minimal physical perturbation 100
• Driven by PrimeTime® STA 0

40nm 32nm
• Augments leakage savings 864K cells 2M cells
4 Vth 7 Vth
delivered by standard leakage BC/WC 4 scenarios
flow in IC Compiler
% Leakage recovery depends on how much power
optimization was done earlier in flow

– In-Design Physical Verification: Lithography Hotspot

Prevention Using Pattern Matching

Manufacturing Challenges at 32/28nm
Sub-Wavelength More & More Complex Feature

Gap Rules Dependencies
Feature Size Wavelength
2000 ?
10
1500 DRC-clean
3.0
2.0 Number of Rules
1
Size (um)
0.436 0.6 1000

0.35 0.193
0.365
0.1 0.18 500
65nm Litho
32nm
0.01 Hotspot
0
350 250 180 150 130 90 65 45 32
Poor process printability Difficult to write and maintain Beyond nearest feature
Address Lithography Limiting Patterns During Design

In-Design PV – Litho Hotspot Prevention
Built on Patented Pattern-Matching Technology
Prevent Match Repair
IC Compiler (ICC) IC Validator (ICV) ICC+ICV

• Manufacturing aware • Pattern-matching • Automatic repair and
routing avoids litho based detection of revalidation of
hotspots lithography limiting matched layout
layout patterns patterns
Fastest Path to Litho-Clean Design Closure

In-Design PV – Pattern-Matching Match
Patented Technology Enables Fast Litho Detection
Automated Intelligent Database-Driven

Pattern Capture Layout Filtering Pattern Matching
30
Runtime (min)
25
20
15
10
5
0
100K
10K
1K
100
10
1
Num Patterns
Directly from OPC, Fast Identification of Zero Runtime Penalty

LRC or Simulation Match Candidates per Pattern
Qualified by GlobalFoundries for 28nm Process

In-Design PV – Auto Litho Repair Repair
Smart Integration Eliminates Corner-Case Patterns
Highly Localized Router-Driven Incremental Validation
Full Property Visibility
Timing Aware
Proven Algorithms
Negligible Physical Impact Highest Quality Final Layout 4-5x Faster Analysis
Eliminates Need for Manual Layout Fixes

Results: Automatic Litho Repair
Customer Designs, 45/40nm
High Repair Rate Fast Runtime

Before After Repair Rate Detection Repair Patterns in DB
1400 100% 30 1000

1214
# Litho Hotspots
1200 25
Runtime (min)
95%
Repair Rate
# Patterns
1000
20 100
800
90% 15
600 457
10 10
400 85%
187
200 5
7 13 54
0 80% 0 1
617k 966k 2.4M 617K 966K 2.4M
Design Instances Design Instances
Hotspot Free in Minutes

Synopsys Solutions At 32/28nm
Summary
Variability Low Power

Galaxy • Comprehensive flow
• High accuracy • Low Power CTS
• MCMM throughout the • In-Design STA : Final-
flow stage Leakage
PrimeTime/StarRC
Design Recovery
Compiler
Manufacturing Compliance
IC Validator Design Complexity
• Routing, Physical
Verification & Test • Runtime speedup
• In-Design PV: Litho IC • 40M+ design handling
Hotspot Prevention using Compiler
Pattern Matching
Production proven across 32/28nm process nodes

Thank You!
Done 32/28nm Design Challenges
Addressing 32/28nm Design

Done
Challenges
Fastest Time to Tapeout
Done
with IC Validator
Realizing Today’s 32nm
Done
and Beyond Large Designs
Manufacturing-Aware
Done
Routing
Extraction For
Done
32/28nm
28nm Silicon And Design
Done
Enablement

Predictable Success
To view other webinars in the 32/28nm webinar series:

http://www.synopsys.com/32-28nm-WebinarSeries

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IC Compiler 32/28nm Webinar Series

28nm Silicon And Design Enablement

The Foundry And EDA Vendor

©Synopsys 2010 1 IC Compiler 32/28nm Webinar Series

Done 32/28nm Design Challenges

Addressing 32/28nm Design

©Synopsys 2010 2 IC Compiler 32/28nm Webinar Series

©Synopsys 2010 3 IC Compiler 32/28nm Webinar Series

• Overview of Synopsys Solutions At 32/28nm

– In-Design STA: Final-stage Leakage Recovery

– In-design physical verification: Automatic Litho-repair

©Synopsys 2010 4 IC Compiler 32/28nm Webinar Series

Variability Low Power

• Routing, Physical • Runtime speedup

Production proven across 32/28nm process nodes

©Synopsys 2010 5 IC Compiler 32/28nm Webinar Series

©Synopsys 2010 6 IC Compiler 32/28nm Webinar Series

Device & Delay RC models & Net

©Synopsys 2010 7 IC Compiler 32/28nm Webinar Series

©Synopsys 2010 8 IC Compiler 32/28nm Webinar Series

Electromigration In-Design PrimeRail

Logic cell Logic cell Clock cell

Comprehensive flow addresses EM & IR issues

©Synopsys 2010 9 IC Compiler 32/28nm Webinar Series

• Auto-insertion of LS/ISO UPF

cells Design Compiler

Production proven automated flow produces best QoR

©Synopsys 2010 10 IC Compiler 32/28nm Webinar Series

New In 2010.12 XOR Clock Gating Datapath For CTS

 Smart selection of buffers vs. data[0:7]

 Power driven sizing

 Intelligent clock net layer 7 7 dly[0:7]

 Target transition relaxation Datapath ICG

Significant clock tree power savings for high-performance designs

©Synopsys 2010 11 IC Compiler 32/28nm Webinar Series

Optimizing leakage and other Delivers Maximum

Better leakage and timing - faster convergence at 32/28nm

©Synopsys 2010 12 IC Compiler 32/28nm Webinar Series

2X Faster initial floorplan creation

©Synopsys 2010 13 IC Compiler 32/28nm Webinar Series

Increased designer productivity in the early stages of the design

©Synopsys 2010 14 IC Compiler 32/28nm Webinar Series

2.8X runtime and 2X memory improvement

©Synopsys 2010 15 IC Compiler 32/28nm Webinar Series

Placement Rules Routing Rules Soft Rules

Soft rule for

Supported by leading foundries and major IDMs

©Synopsys 2010 16 IC Compiler 32/28nm Webinar Series

Manufacturing Multicore Delivers

3X Speed-up, higher QoR, better manufacturability

©Synopsys 2010 17 IC Compiler 32/28nm Webinar Series

In-Design DRC In-Design Metal Fill In-Design LCC

Signoff Quality 10x Faster

©Synopsys 2010 18 IC Compiler 32/28nm Webinar Series

• Overview of Synopsys Solutions At 32/28nm

– In-Design STA: Final-stage Leakage Recovery

– In-design physical verification: Automatic Litho-repair

©Synopsys 2010 19 IC Compiler 32/28nm Webinar Series

• Sub-threshold leakage current dominates total leakage power

Need to approach leakage optimization from a device modeling perspective

©Synopsys 2010 20 IC Compiler 32/28nm Webinar Series

• Increasing channel length is also referred to as CD biasing

Example: 3 different leakage variants of a NAND3 with CD biasing