Implementation of Zero Current Switch Turn-ON based Buck-

Boost-Buck Type Converter for Low Power Applications

Abstract– In this paper, a single stage single switch ac/dc integrated converter is proposed as
a tight DC voltage regulator with unity input power factor. Proposed converter is formed by
the integration of buck-boost converter with a buck converter operated by a single switch.
The buck-boost section of the proposed converter is operated in discontinuous current
conduction mode (DCM) so that unity power factor can be achieved at the input and the buck
section is operated up to boundary current conduction mode (BCM). The features acquired by
the converter operating in complete discontinuous conduction mode (DCM) are, unity input
power factor, zero-current switch turn-ON, fast and well regulated DC output voltage with
extensive conversion range, and low voltage stress on the switch. Additionally, the
intermediate capacitor voltage stress is independent of converter load variations so as the
switch. A comprehensive study is carried out to obtain the necessary design equations. A
design model is implemented using simulation and hardware. The results confirm the
performance of the proposed converter.
Key words: ac-dc converter, single stage single switch, buck-boost-buck, zero-current
turn-ON, power factor correction (PFC).

I. INTRODUCTION

The DC supply is generally used for various applications, such as battery charging for
electric vehicles, lighting system, telecommunication systems, solar energy applications,
LED drivers, battery energy storage systems (BESSs), and inverter etc. [1]–[3]. For many of
these applications ac/dc converters requires power factor correction (PFC) system to improve
the input power factor with less harmonic distortion in the supply current. With the modern
international power quality requirements (EN/IEC 61000-3-2), PFC methods have become
more significant in the ac/dc converters, and lots of research has been done on the PFC
converters [2]–[10].

In two-stage ac/dc converters, first stage (PFC system) improves the input power
factor and the second stage (DC-DC regulator) tightly regulates dc output voltage with low
ripple [4]–[7]. But, the input power processing can be done through two stages (PFC and
regulator), with this the converter efficiency is restricted to the product of individual
efficiencies. However, these converters are costly, need complex control scheme, which
increases the complexity of the converter [8]–[9]. Hence single-stage single-switch ac/dc
converters have been developed [9]-[10] by integrating PFC converter with DC-DC regulator
using a common active switch. This approach reduces the size, cost and simplifies the control
of the converter.

However, single-stage converters experience high switching voltage stress compared

to the two-stage converters. This is due to the unregulated intermediate storage capacitor
voltage, which is depends on the input and load characteristics [11]–[13]. For universal input
voltage range, the intermediate storage capacitor voltage rises further than 450 V. Therefore,
a bulky capacitor and high voltage rating active switch is needed for the single-stage ac/dc
converter. As a result, efficiency will get reduced, size and cost will increase. This problem
restricts the single-stage converters to a limited number of applications. Researchers have
been proposed number of methods in [14]–[23] to limit the voltage of the intermediate
storage capacitor. But the majority of these methods employed boost converter as a PFC
system. This design is found to be inappropriate for low output-voltage applications such as
PCs, SMPS loads etc.

Standard single-switch converters (Buck–Boost, Cuk, and SEPIC etc.,) [24] can
produce low output-voltage along with PFC. Because of high switching stresses they are not
suitable for universal input voltage range and the switch usage is poor for lower duty ratios
resulting lower efficiencies [25]. Single-stage single-switch configurations (integrated
configurations) are capable of overcoming the problems facing by conventional buck-boost
topologies [26]. With the integration of two converters, conversion range can be boosted a
lot, as the conversion ratio 𝑀(𝐷) becomes quadratic function of duty ratio (𝐷) [27].

In this paper, a single stage single switch integrated buck-boost-buck (IB3) ac/dc
integrated converter is proposed. Buck–boost converter is chosen as PFC system at the input

side. In general, applications like LED drivers etc., need 5W – 25W power level. Buck–boost

has outstanding PFC capabilities for this power range and also has potential for bucking the
voltage [28]. The buck converter is selected at the output because of its step-down ability.
The buck-boost section is operated in discontinuous current conduction mode (DCM) so that
unity power factor can be achieved at the input and the buck section is operated in boundary
current conduction mode (BCM). The buck section can be operated either continuous
conduction mode (CCM) or Discontinuous conduction mode (DCM). Moreover operating the
buck converter in DCM, the converter draws higher peak currents. By using a high current
density active switch, peak currents problem can be minimized. The features gained by the
converter operating in complete discontinuous conduction mode (DCM) are:

1. Fast and well regulated dc output voltage with extensive conversion range.
2. Unity input power factor.
3. Zero-current switch turn-ON.
4. Low voltage stresses on both the switch ‘S’ and storage capacitor 𝐶𝑟 .
5. Reverse recovery issue of the diodes has minimized.
6. High efficiencies.
7. Switch voltage 𝑉𝑆𝑊 and capacitor voltage 𝑉𝐶𝑟 stresses are independent of load variations.

Section-II represents circuit configuration and operation of the proposed configuration

and the important equations. In section-III the theoretical analysis is illustrated with
necessary equations. The modeling and design considerations are presented for the proposed
converter in section-IV. Discussion on simulation and experimental results are presented in
section-V to validate the performance of the proposed model. Conclusions based on the
performance analysis are given in section-VI.

II. Proposed Buck-Boost-Buck Type Converter

A. Circuit configuration
Fig. 1 shows the circuit configuration of proposed single stage single switch
converter. This converter is the integration of buck-boost converter with a buck converter
controlled by a single switch. The buck-boost section includes diode 𝐷1 , input inductor 𝐿𝑟 ,
intermediate storage capacitor 𝐶𝑟 and the buck section includes diode 𝐷1 , output inductor 𝐿0 ,
free-wheeling diode 𝐷𝐹 , output capacitor 𝐶0 . The switch ‘S’ is common for the both sections.
The input inductor 𝐿𝑟 is selected to operate in discontinuous conduction mode (DCM). The
through input inductor 𝑖𝐿𝑟 is discontinuous hence the line average current is proportional to
input supply voltage, this makes the input power factor as unity. Thus, the front section
becomes much appropriate for universal input voltage range. The output inductor 𝐿0 value is
chosen to operate in discontinuous conduction mode (DCM). The intermediate storage
capacitor voltage 𝑉𝐶𝑟 depends on input supply voltage 𝑉𝑠 . Switch voltage 𝑉𝑆𝑊 is depends on
the capacitor voltage 𝑉𝐶𝑟 . So a centre-tapped step-down transformer based full wave rectifier
is used, to reduce the voltage stress on the intermediate storage capacitor 𝐶𝑟 and also to
isolate the load from the input terminals.
iD1 D1 L0

- iL0
Cr vCr -
CENTER TAPPED Lr +
is TRANSFORMER
DFW1 + iLr
iSW
+ DF
v0 RL
AC Input

MOSFET C0
Vs Vin vSW
iDF
- i0
G

DFW2 D2 + v0
-
iD2
G
+ PI Controller Ʃ
-
Vref

Fig. 1 Proposed single stage single switch Integrated Buck-Boost-Buck (IB3) configuration

B. Steady-state operation
The steady-state operation of the IB3 converter over a switching period (Ts = 1/fs) is
shown in Fig. 2.

D1 L0

- iL0
Cr vCr -
Lr +
+ iLr
iSW
+ DF
v0 RL
S C0
vSW
Vin
- i0
G

- D2 +

iD2

(a) Mode I
 iD1 D1 L0

-
Cr vCr -
+ iL0

+ iLr Lr

+ DF
iDF v0 RL
S C0
VSW
Vin
- i0

- D2 +

(b) Mode II

L0

- -
i L0

DF v0 RL
i DF v0 RL C0
C0

i0
i0

+
+

(c) Mode III (d) Mode IV

Fig. 2 Operating modes of IB3 configuration.

Mode-I [t0, t1]: Prior to this mode, input and output inductor currents 𝑖𝐿𝑟 , 𝑖𝐿0 are zero, and
the filter capacitor 𝐶0 feeds the load. Fig. 2(a) represents Mode-I operation. At t = t0 the
switch 𝑆 is turned on, so the inductor currents 𝑖𝐿𝑟 , 𝑖𝐿0 increases linearly from zero. In this
mode both inductor currents 𝑖𝐿𝑟 , 𝑖𝐿0 flow through the switch 𝑆. The storage capacitor 𝐶𝑟
discharges its energy through switch 𝑆. Conversely the diodes D1 and DF are reverse biased
but diode D2 is forward biased. This mode will proceed up to switch 𝑆 is turned on.
Mode-II [t1, t2]: At t1 switch 𝑆 is turned off, the currents 𝑖𝐿𝑟 , 𝑖𝐿0 linearly discharges through
the diodes D1 and DF respectively as shown in Fig. 2(b). So the intermediate storage
capacitor 𝐶𝑟 charges using inductor current 𝑖𝐿𝑟 . In this interval the diode D2 becomes reversed
biased. This mode will end at the current 𝑖𝐿𝑟 reaches the zero.
Mode-III [t2, t3]: In this interval the current 𝑖𝐿𝑟 stays at zero but current 𝑖𝐿0 decreases linearly
through the freewheeling diode DF. This mode will end when the output inductor current 𝑖𝐿0
becomes zero. This mode of operation is shown in Fig. 2(c).
Mode-IV [t3, Ts]: Mode-IV is a small interval created because of discontinuous conduction
mode (DCM) operation of output inductor 𝐿0 . Benefit of DCM operation is that the switch
(𝑉𝑆𝑊 ) and storage capacitor voltage (𝑉𝐶𝑟 ) stresses are low and independent to the load
variations. In boundary conduction mode (BCM) the switch is turned-on at t = t3, this
eliminates Mode-IV. Advantage of operating under boundary conduction mode (BCM) is
superior converter efficiency. The ideal steady-state waveforms of the proposed converter for
a switching cycle are shown in Fig. 3.

III. THEORETICAL ANALYSIS

A. Output voltage 𝑽𝟎 and conversion ratio 𝑴(𝑫):
Considering the 𝑣𝑠 = 𝑉𝑆 𝑠𝑖𝑛𝜔𝐿 𝑡 as input sinusoidal voltage (𝑣𝑠 ), and the input current
is 𝑖𝑠 . During the time interval 𝑑1 𝑇𝑠 , the input inductor current 𝑖𝐿𝑟 is same as the input
current 𝑖𝑠 , where 𝑑1 is the duty ratio of the switch over a switching cycle 𝑇𝑠 . The rectified
line voltage modulates the input current, as presented in Fig. 4 (For half-line cycle). In a
switching period 𝑇𝑠 , the input voltage 𝑣𝑠 is assumed to be constant since the switching
frequency 𝑓𝑠 (=1/𝑇𝑠 ) is higher than the supply frequency ( 𝑓𝑠 ≫ 𝑓). This phenomenon is also
shown with respect to input current 𝑖𝑠 in Fig. 3. Thus the average input current of each pulse
can be represented as the instantaneous input current at the end of each pulse. Therefore, the
average input unfiltered current at line frequency is derived as [1]:
𝑖𝑠𝑝 𝑑1 2 𝑉𝑠
〈𝑖𝑠 〉 = 𝑑1 𝑇𝑠 = (𝑠𝑖𝑛𝜔𝐿 𝑡) (1)
2𝑇𝑠 2𝐿𝑟 𝑓𝑠
where 〈𝑖𝑠 〉 is input current at time t, 𝑖𝑠𝑝 is the peak value of each current pulse, 𝑉𝑠 is the peak
value of input supply voltage. From equation (1) it can be observed that the unfiltered
average input current is sinusoidal and in-phase with supply voltage (𝑣𝑠 ). Thus with input
inductor 𝐿𝑟 discontinuous current conduction mode (DCM) the input unity power factor can
be achieved. So the input power Ps is
1 𝑑1 2 𝑉𝑠 2
𝑃𝑠 = 𝑉𝑠 〈𝑖𝑠𝑝 〉 = (2)
2 4𝐿𝑟 𝑓𝑠
 G
Mode

I II III IV I
t
is, vs iLrp vs

Is

t
iLr iLrp
DCM

t
iL0
iL0p
DCM

t
iCr iLrp

Discharging

t
Charging

-iL0p

iSW iLrp + iL0p

Zero Current
Turn-ON
t
d1Ts d2Ts d3Ts
iD1
iLrp

t
t0 t1 t2 t3 Ts

Fig 3 Ideal Steady-state waveforms of proposed converter

 is
Not Scaled

t
Ts d1Ts
Line half period TL/2

Fig. 4 Modulated unfiltered input current

𝑉02
Using power equilibrium between input and output (𝑃0 = ), the average output voltage 𝑉0
𝑅

can be obtained as

𝑑1 𝑉𝑠 𝑅
𝑉0 = √ (3)
2 𝐿𝑟 𝑓𝑠

Where R is load resistance.

𝑉0
From equation (3), the voltage conversion ratio 𝑀(𝐷) (= ⁄𝑉 ) for lossless converter in
𝑠

DCM region is obtained as

𝑑1
𝑀(𝐷) = (4)
√2𝑘
The factor 𝑘 is given by
2𝐿𝑟 𝑓𝑠
𝑘= (5)
𝑅
Equation (4) is valid only for 𝐿𝑟 operating in DCM region. Fig. 5 represents the plot between
voltage conversion ratio 𝑀(𝐷) and duty ratio 𝑑1 for different values of 𝑘. In the CCM region
only Mode-I and Mode-II operating modes exist, so equation (4) doesn’t valid. The voltage
conversion ratio 𝑀(𝐷) in CCM region is given by
2𝑑12
𝑀(𝐷) = (6)
[𝜋(1 − 𝑑1 )]
 Fig. 5 Voltage conversion ratio 𝑀(𝐷) verses duty ratio 𝑑1 for different values of 𝑘

B. Intermediate capacitor voltage 𝑽𝑪𝒓 :

The intermediate capacitor voltage 𝑉𝐶𝑟 is an essential design element. Because the
switch 𝑆 voltage stress and voltage stress across the diodes 𝐷1 , 𝐷2 are dependent on 𝑉𝐶𝑟 .
From Fig. 3 the average capacitor current 〈𝑖𝐶𝑟 (𝑡)〉 𝑇𝑠 for a switching cycle 𝑇𝑠 is given as
1
〈𝑖𝐶𝑟 (𝑡)〉 𝑇𝑠 = [𝑑2 𝑖𝐿𝑟𝑝 − 𝑑1 𝑖𝐿0𝑝 ] (7)
2
Under steady-state equation (7) must be zero.
From Fig. 3 the inductor currents 𝑖𝐿𝑟𝑝 , 𝑖𝐿0𝑝 can be given as
𝑉𝑠
𝑖𝐿𝑟𝑝 = 𝑡
𝐿𝑟 1
𝑉𝐶𝑟 − 𝑉0
𝑖𝐿0𝑝 = 𝑡1 (8)
𝐿0
𝑇𝐿
The average capacitor current 〈𝑖𝐶𝑟 (𝑡)〉𝑇𝐿 over a half-line cycle is
2
2

𝑇𝐿
2
2
〈𝑖𝐶𝑟 (𝑡)〉𝑇𝐿 = ∫ 〈𝑖𝐶𝑟 (𝑡)〉 𝑇𝑠 𝑑𝑡 (9)
2 𝑇𝐿
0

Using equations (7), (8) and (9), the intermediate capacitor voltage 𝑉𝐶𝑟 can be derived as
 𝑉0 2𝐿0 𝑉𝑠 2
𝑉𝐶𝑟 = (1 + √ ( ) + 1) (10)
2 𝐿𝑟 𝑉0

𝑉0
From equation (10) it can be noted that, for a specified value of 𝑀 (= ⁄𝑉 ) ,
𝑠

intermediate capacitor voltage 𝑉𝐶𝑟 is independent of load current variation, but it depends on
𝐿0
input voltage 𝑉𝑠 , output voltage 𝑉0 and inductance ratio ⁄𝐿 . So with a centre-tapped step-
𝑟

down transformer the input voltage can be low, which helps to reduce the intermediate
storage capacitor 𝐶𝑟 voltage stress, thereby switching voltage stress (𝑉𝑆𝑊 ) and the diodes 𝐷1 ,
𝐷2 voltage stress.

C. Conditions for DCM and BCM:

Applying volt-sec principle to input inductor 𝐿𝑟 , from Fig. 3 it can be written as
𝑣𝑠 𝑉𝐶𝑟
𝑑1 𝑇𝑠 − 𝑑 𝑇 =0
𝐿𝑟 𝐿𝑟 2 𝑠
𝑉𝐶𝑟
𝑑1 = 𝑑2 (11)
𝑣𝑠
Similarly for 𝐿0
𝑉𝐶𝑟 − 𝑉0 𝑉0
( ) 𝑑1 𝑇𝑠 − (𝑑2 + 𝑑3 )𝑇𝑠 = 0
𝐿0 𝐿0
𝑉𝐶𝑟 − 𝑉0
𝑑2 + 𝑑3 = 𝑑1 ( ) (12)
𝑉0
To operate inductor 𝐿𝑟 in DCM, the below condition must be satisfied:
𝑑1 + 𝑑2 ≤ 1 (13)
Similarly to operate inductor 𝐿0 in DCM, the below condition must be satisfied:
𝑑1 + 𝑑2 + 𝑑3 ≤ 1 (14)
Simplifying equations (13) and (14) using (11) and (12):
𝑣𝑠 1 − 𝑑1
≤ (15)
𝑉0 𝑑12
𝑉0
𝑑1 ≤ (16)
𝑉𝐶𝑟
From equation (14), 𝑑1 + 𝑑2 + 𝑑3 = 1 then inductor 𝐿0 operates in BCM. This condition
reduces the current stress on the active switch and improves overall converter efficiency.
Using equations (5) and (15) 𝑘 value can be written in terms of duty ratio 𝑑1 is given by
 (1 − 𝑑1 )2
𝑘≤ (17)
2𝑑12
From equation (17) the critical value can be obtained to operate the 𝐿𝑟 in DCM is:
(1 − 𝑑1 )2
𝑘𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 = (18)
2𝑑12
From (18) it can be observed that the proposed configuration has wide DCM range for
voltage conversion ratio 𝑀(𝐷) than that of standard buck–boost converter. So 𝐿𝑟 will
operate in DCM for 𝑘 ≤ 𝑘𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 , if not, converter will operate in CCM region. This is
illustrated in Fig. 6.

Fig. 6 Inductor 𝐿𝑟 DCM/CCM regions for proposed and standard buck–boost converter

IV. DESIGN OF REACTIVE COMPONENTS

Design analysis of converter reactive components 𝐿𝑟 , 𝐶𝑟 and 𝐿0 are discussed in this
section. The selection of output filter capacitor 𝐶0 is made large enough for output voltage
ripple minimization. So the average output voltage 𝑉0 will be fairly constant and hence C0
will not affect the circuit dynamics. From equation (2), for a given output power the input
inductance 𝐿𝑟 for a lossless converter is obtained as
𝑑1 2 𝑉𝑠 2 𝑑1 2 𝑉𝑠 2
𝐿𝑟 = = (19)
4𝑃𝑆 𝑓𝑠 4𝑃0 𝑓𝑠
For the values 𝑑1 = 0.25, 𝑉𝑠 = 84𝑉𝑝 , 𝑃0 = 5𝑊 and 𝑓𝑠 = 10𝐾𝐻𝑧 the input inductance 𝐿𝑟
value calculated as 𝐿𝑟 = 2.205𝑚𝐻. For simulation purpose 𝐿𝑟 = 2.25𝑚𝐻 is considered.
To calculate storage capacitor 𝐶𝑟 , low-frequency peak-to-peak capacitor voltage ripple
(∆𝑉𝐶𝑟 ) can be obtained as
 2〈𝑖𝐷1 〉𝑎𝑐 𝑝
∆𝑉𝐶𝑟 = 2〈𝑖𝐷1 〉𝑎𝑐 𝑝 𝑋𝐶𝑟 = (20)
2𝜋. 2. 𝑓𝐿 𝐶𝑟
where 〈𝑖𝐷1 〉𝑎𝑐 𝑝 is the peak value of the low-frequency diode average modulated ac current
and 𝑓𝐿 is the line frequency. Similar to the equation (1) using Fig. 3, the diode average
modulated current 〈𝑖𝐷1 〉 for double the line frequency is given by
𝑖𝐷1𝑝 𝑑1 𝑑2 𝑉𝑠
〈𝑖𝐷1 〉 = 𝑑2 𝑇𝑠 = (𝑠𝑖𝑛𝜔𝐿 𝑡) (21)
2𝑇𝑠 2𝐿𝑟 𝑓𝑠
Using equation (11) in (21) current 〈𝑖𝐷1 〉 is obtained by
𝑑1 2 𝑉𝑠 2 2
𝑑1 2 𝑉𝑠 2 1 − 𝑐𝑜𝑠2𝜔𝐿 𝑡
〈𝑖𝐷1 〉 = (𝑠𝑖𝑛 𝜔𝐿 𝑡) = ( ) (22)
2𝐿𝑟 𝑓𝑠 𝑉𝐶𝑟 2𝐿𝑟 𝑓𝑠 𝑉𝐶𝑟 2
From equation (22) the low-frequency ac current circulating through storage capacitor 𝐶𝑟 and
diode 𝐷1 is
𝑑1 2 𝑉𝑠 2 𝑐𝑜𝑠2𝜔𝐿 𝑡
〈𝑖𝐷1 〉𝑎𝑐 𝑐𝑜𝑛𝑡𝑒𝑛𝑡 = = 〈𝑖𝐷1 〉𝑎𝑐 𝑝 . 𝑐𝑜𝑠2𝜔𝐿 𝑡 (23)
4𝐿𝑟 𝑓𝑠 𝑉𝐶𝑟
Using equation (23), from (20) capacitor voltage ripple (∆𝑉𝐶𝑟 ) is obtained as
𝑑1 2 𝑉𝑠 2 1
∆𝑉𝐶𝑟 = (24)
8𝜋𝐿𝑟 𝑓𝑠 𝑓𝐿 𝑉𝐶𝑟 𝐶𝑟
So the intermediate storage capacitance 𝐶𝑟 , for a considerable voltage ripple (∆𝑉𝐶𝑟 ) is given
by
𝑑1 2 𝑉𝑠 2
𝐶𝑟 = (25)
8𝜋𝐿𝑟 𝑓𝑠 𝑓𝐿 𝑉𝐶𝑟 ∆𝑉𝐶𝑟
For 𝑑1 = 0.25, 𝑉𝑠 = 84𝑉𝑝 , 𝑃0 = 5𝑊, 𝑓𝐿 = 50𝐻𝑧, ∆𝑉𝐶𝑟 = 35𝑉, 𝐿𝑟 = 2.25𝑚𝐻, 𝑉𝐶𝑟 = 89𝑉 and
𝑓𝑠 = 10𝐾𝐻𝑧 the intermediate storage capacitance 𝐶𝑟 value calculated as 𝐶𝑟 = 5.006𝑢𝐹. For
simulation purpose 𝐶𝑟 = 5𝑢𝐹 is considered.
Similarly the output inductance 𝐿0 for a permissible ripple ∆𝑖𝐿0 is given by
(𝑉𝐶𝑟 − 𝑉0 )𝑑1
𝐿0 = (26)
𝑓𝑠 ∆𝑖𝐿0
For 𝑑1 = 0.25, 𝑉0 = 35𝑉, ∆𝑖𝐿0 = 0.44𝐴, 𝑉𝐶𝑟 = 89𝑉 and 𝑓𝑠 = 10𝐾𝐻𝑧 the output inductance
𝐿0 value calculated as 𝐿0 = 3.06𝑚𝐻. For simulation purpose 𝐿0 = 3𝑚𝐻 is considered.

V. RESULTS AND DISCUSSION

A design example of proposed converter as given in Fig. 1 is simulated with
MATLAB/SIMULINK software. The designed circuit parameters are specified in Table-I.
Based on the analysis made in earlier sections the circuit components are designed. Converter
input voltage 𝑉𝑠 is assumed to be an ideal rectified sine wave. Both the inductors 𝐿𝑟 and 𝐿0
are operated in the DCM and assumed that the current 𝑖𝐿𝑟 reaches zero level earlier than the
current in 𝑖𝐿0 .

TABLE-I
CIRCUIT PARAMETERS OF THE PROPOSED CONVERTER
Parameter Simulation Experimental
Converter Input Voltage (𝑉𝑠 ) 84 Vp 84 Vp
Supply Line Frequency ( 𝑓𝐿 ) 50 Hz 50 Hz
Switching Frequency ( 𝑓𝑠 ) 10 kHz 10 kHz
𝐿𝑟 2.25mH 2.3mH
𝐶𝑟 5uF 5.5uF
𝐿0 3mH 3mH
𝐶0 1000uF 1000uF
Centre tapped T/F Rating 230/60-0-60 V 230/60-0-60 V
R 250Ω 250Ω

Fig. 7 Simulation waveforms of supply voltage and input line current without input filter

Fig. 7 shows simulated waveforms of supply voltage and input line current at 𝑃0 =
5𝑊. It can be noticed that the unity input fundamental power factor is achieved even though
the input current is with sinusoidally varying pulses. Fig. 8 represents the experimental
waveform of input line current (sinusoidally varying pulses) with gate signal of 15V.
 20 V/div

Gate Pulse
0.2 A/div

100 μs/div Input Line Current

(Sinusoidally Varying Magnitude)

Fig. 8 The experimental waveform of input line current (pulses) along with gate signal (15V).

Fig. 9 The Simulation waveforms of input inductor current ( 𝑖𝐿𝑟 ), output inductor current
( 𝑖𝐿0 ) and switch current ( 𝑖𝑆𝑊 )

Inductors 𝐿𝑟 and 𝐿0 are operating in DCM so the currents are discontinuous which is
represented in Fig. 9. Fig. 9 shows the simulated waveforms of input inductor current ( 𝑖𝐿𝑟 ),
output inductor current ( 𝑖𝐿0 ) and switch current ( 𝑖𝑆𝑊 ). Experimental waveforms of inductor
currents ( 𝑖𝐿𝑟 , 𝑖𝐿0) and switch current ( 𝑖𝑆𝑊 ) are shown in Fig. 10. According to assumption
the current 𝑖𝐿𝑟 reaches zero level earlier than the current in 𝑖𝐿0 . Because of DCM operation of
output inductor current ( 𝑖𝐿0 ), the current in the switching device will start from zero. This
provides Zero Current Turn-ON (ZCT) condition at switch ‘S’. With ZCT condition, the
switch (𝑉𝑆𝑊 ) and storage capacitor voltage (𝑉𝐶𝑟 ) stresses are low and also independent to the
load variations.
 1 A/div

Input Inductor Current

100 μs/div

(a)

0.4 A/div
Output Inductor Current

100 μs/div

(b)

Switch ‘S’ Current

50 μs/div Zero Current Switch

Turn-ON

0.2 A/div

(c)
Fig. 10 Experimental waveforms (a) input inductor current ( 𝑖𝐿𝑟 ), (b) output inductor current
( 𝑖𝐿0 ) (c) switch current ( 𝑖𝑆𝑊 )
 Fig. 11 shows the simulated waveforms of output voltage (𝑉0) with storage capacitor
voltage (𝑉𝐶𝑟 ) at 25% duty ratio (𝑑1 ). In Fig. 12 the experimental waveforms of capacitor
voltage and output voltage (Non-Inverted) are shown for the same duty ratio ( 𝑑1 ). As
discussed in section-IV the capacitor voltage ripple (∆𝑉𝐶𝑟 ) is 35V which can be proved from
Fig. 11 and 12 for 25% duty ratio.

Fig. 11 Simulation waveforms of output voltage (𝑉0) and storage capacitor voltage (𝑉𝐶𝑟 )

100 V/div 20 V/div

Storage Capacitor
Voltage VCr
Output DC Voltage
V0 (Non-Inverted)
20 μs/div
10 μs/div

Fig. 12 the experimental waveforms of capacitor voltage and output voltage (Non-Inverted)

Fig. 13 shows the plots for % efficiency, % input power factor, % output voltage
ripple and % THD of input line current at 𝑃0 = 5𝑊 for universal operating voltage range. As
can be seen, the % efficiency is above 89% throughout the range and the power factor (input
filter) is also above 0.98 (almost unity). Furthermore the % THD is well under the limits,
with well regulated output dc voltage (very less % regulation).
 Fig. 13 Plots for universal operating voltage range at 𝑃0 = 5𝑊. (a) % Efficiency, (b)
% Input power factor, (c) % Output voltage ripple and (d) % THD of input line current

Fig. 14 demonstrates the different essential plots for two different output voltages
(35V, 60V) with ±20% load variations. From Fig. 14 it can be acknowledged that the
converter showed the better performance for load variations (250Ω ± 20%) with higher
efficiency and almost unity input power factor. Moreover the storage capacitor voltage (𝑉𝐶𝑟 )
is independent of these load variations so as the switch voltage (𝑉𝑆𝑊 ).

Fig. 14 Plots with ±20% load variations for two operating voltages. (a) % Efficiency,
(b) % Input power factor, (c) % THD of input line current (d) Storage capacitor voltage (𝑉𝐶𝑟 )
 Fig. 15 shows the plots for with and without input filters for various duty ratios. It can
be observed that the output voltage and % regulation are very similar for with and without
input filters. In addition, for very low duty ratios without filter gives unity input power factor
with very less output ripple. The measured %THD of input current is less than 4% as shown
in Fig. 15. This shows the operating range capability of the proposed converter at low duty
ratios. Fig. 16 shows the input and output power curves with power loss for range of duty
ratios.

Fig. 15 Plots for with and without input filters (a) % Input power factor (b) % THD of input
line current (c) Output voltage (𝑉0 ) and (d) % Regulation of 𝑉0

Fig. 16 Plot of Input and Output power curves with power loss for various duty ratios.
 Fig. 17 shows the Simulated and Experimental efficiency curves with and without
ZCT (Zero Current Turn-ON) respectively. It can be shown that operating the switch with
ZCT condition gives more efficiency. Fig. 18 shows the efficiency curves with respect to the
output power 𝑃0 . It can be seen that simulation efficiency for 5W – 25W is 90% – 95%,
where as the experimental efficiency is 85.6% – 91.2%.

Fig. 17 Simulated and Experimental efficiency curves with and without ZCT

Fig. 18 Simulation and Experimental efficiency curves with respect to output power 𝑃0
 VI. CONCLUSION
In this paper, a single stage single switch ac/dc integrated converter is proposed for
DC voltage regulation along with unity input power factor. This converter is integration of
buck-boost converter with a buck converter operated by a single switch. The detailed
operation and design of proposed converter in discontinuous current conduction mode
(DCM) is presented with necessary equations. The features acquired by DCM are, unity input
power factor, zero-current switch turn-ON, tight regulated DC output voltage with extensive
conversion range, and low voltage stresses. The intermediate capacitor and switch voltage
stresses are independent of load variations. A design example is simulated using
MATLAB/SIMULINK, for the same a laboratory set-up is also made in-order to verify the
feasibility of the proposed configuration. The proposed configuration is also tested for
universal input voltage ranges (90–265 Vrms) and ±20% load variations. From the results the
proposed configuration has achieved good performances such as, input power factor unity
(without filter), more than 98% with filter, %THD less than 6% (for variable load), less than
4% (for constant load). Higher efficiencies (85.6% – 91.2%) achieved for the output power
range 5W – 25W. Converter voltage stresses are low and are independent to the load
variations.

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