PULL nano !

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News from the European 32/22nm CMOS Research pool at month 21 April 2008

EDITORIAL VITeam

Clearly the semiconductor

industry is going through
32/22nm metrology
challenging times, yet
again, as we see the 32nm
European SMEs come
technology node creating
a rupture in the semiconductor land- on board
scape. The escalation of development
costs and of manufacturing fab invest- In the drive towards nanostructures,
ments is forcing more players to greater
cost sharing in the form of large trans- advanced metrology is of crucial impor-
continental alliances. With its strong tance to staying ahead of the technology
academic and industrial partnership,
e l e c t r o n i c s

Pullnano has certainly led the 32nm
CMOS battle for Europe. Our competi-
tive 32nm SRAM cell demonstrator, pre-
sented at IEDM 2007, is the world’s first
with a Fully Depleted Silicon On Insula-
tor (FDSOI)/High K dielectric/Metal Gate
architecture. At 32nm design rules this
memory cell translates into a density of
33 million transistors per mm2!
The withdrawal of NXP and Freescale
from the Crolles2 Alliance (as of Decem-
ber 07) with implications on the
Pullnano consortium partnership left
former Crolles 2 Alliance members in
N a n o C M O S
progress in order to stabilize the process
window at smaller nodes. In order to face
this challenge, the Pullnano Consortium
asked three SMEs to come to the rescue.
An overview with Martin Schellenberger,
coordinator of the equipment subproject
for Pullnano at the Fraunhofer IISB.
Small is beautiful ... but tiny semiconduc-
Martin Schellenberger, coordinator
tors pushing back the limits of miniaturi-
for the SP7, Fraunhofer IISB : « Pull-

search of a new world size alliance.
Elsewhere large alliances are forming as
well. Nevertheless work towards the
32 nm node continues and will accele-
rate, since no single CMOS technology
can “do it all” given the variety of appli-
cations and markets accessible to large
chip manufacturers. Know-how, soft-
ware tools methodologies, models, cha-
racterization techniques and equipment
improvements developed through
Pullnano will be transferred to/used in
additional technologies known as More
o f
zation are not only a challenge for the
fabrication process with smaller struc-
tures, new materials and new device ar-
chitectures. They are also a challenge for
the analysis and characterization equip-
ment, a prerequisite to be able to develop
and produce the nanostructures down to
the 32/22nm nodes. As Pullnano results
are developed towards the industrial ex-
ploitation phase, the equipment forum,
active in subproject 7 (SP7) and coordina-
nano tells the process directions and
contributes to the process specifica-
tions for SEA-NET. In this case, the
specification is the know-how co-
ming from Pullnano, and we will get
the results feedback from SEA-NET. »
developing the necessary process and
metrology equipment, with a special
focus on 32/22nm capabilities related to

Than Moore technologies (RF, analog, ted by the Fraunhofer Institute of Integra- the Pullnano needs », points out Martin
embedded memories…), optoelectro-
nics or NEMS (NanoElectroMechanical ted Systems and Device Schellenberger
l i m i t s

Systems). This will allow a smoother Technology (IISB) in Erlan-
transition to 32nm manufacturing in gen, Germany, scored a
Europe. few important achieve-
During the final year of the Pullnano ments. « It is the overall ob-
project the consortium’s attention is jective of the SP7
focusing more and more towards 22nm
equipment forum to opti-
devices; preliminary work shows that
with creative and bold device architec- mize and smooth the pro-
t h e
from the Fraunhofer
Institute. In Pull-
nano, the equip-
ment activities are
especially suppor-
The NovaScan platform is a metrology
ted by new part-
solution for critical dimensions and
shape profiling applications down to ners, Cameca and

ture the 22 nm node can offer the cedure of designing and 32nm (doc. Nova) Imagine Optic from
performances expected in the ITRS
(International Technology Roadmap for
Semiconductors). Certainly one of the Table of contents
options studied within Pullnano will
P u l l i n g

emerge in the final industrial 22nm tech- MASTAR : A European Enrico Sangiorgi :
nology. Good news: at 22nm the
technical aspect seems to work; if the compact model enters “Electronic industry is in
economics also works, we should then the international stage p.3 the midst of revolutionizing
see the 16nm node happen …
the traditional CMOS device” p.4
Dr Gilles Thomas (STMicroelectronics) High-K material
Pullnano coordinator Will Gadolinium succeed Dissemination p.6
to Hafnium ? p.6
1
 VITeam

M a r t i n S c h e l l e n b e r g e r W P 7 E q u i p m e n t s

Spectrometry) instrument of its fers for materials and da-

own, the french company Cameca mage characterization. A
is developing the metrology sys- sensitivity analysis for the
tem needed for the depth profiles layer stacks and materials
via ultra low impact energy capa- and the preparation of the
bilities (100 to 150 eV). The SIMS spectral libraries with the
technique allows molecular and material parameters is cur-
elemental characterization of rently under way. The team
layers as well as the investigation is also working on the defi- The e-Xplorer installed a
of bulk composition and distribu- nition of the measurement Fraunhofer Institute (do
tion of trace elements, with a very tool as well as preparing the wafer process
high resolution (lateral as well as flow and the characterization of the wa-
The IMS SCU on stage at IMEC (doc. Cameca) depth). fers. The outcome should be a reliable pre-
The Cameca activities in Pullnano diction for measurement capabilities.
France and Nova from Israel ; these SMEs are manifold : simulation and calcula-
from the equipment community joined the tion of the beam optics for improved
Pullnano consortium in 2007. transmission; calculation of the chro-
During fabrication, there is a need to matic aberrations for 150 eV impact
control the structures built at each process energy; new design of the Cesium
step, in order to define and stabilize the source for ultra low impact energy ap-
process window precisely and to achieve plication and associated electronics;
the highest possible performance and optimization of the oxygen source to
yield. In the case of Pullnano, the metro- enable working mode with ultra low
logy equipment has, for example, to tackle impact energy; implementation and
measurements on 2D and 3D aspects, as validation of performances. Up to
well as to establish dopant profiles of bu- now, the team has achieved an in-
ried structures. The technology oriented crease of the sputter rate by a factor Flatness metrology for CMP : the measurement
project Pullnano has grown on top of the 3, up to 0.1nm/min. Validation of the contains global and local wafer geometry.
previous Nanocmos project where new system with the new Cesium source is
equipment had already been identified. In planned for June 2008.
order to go further than the initial contrac- In the Metrology for Scatterometry-Based CMP metrology in situ
tual phase, the original 35 member consor- Imagine Optic is active in the me-
tium exceptionnally decided to trology for chemical-mechanical
use the reserve of 300 k€ to polishing (CMP), where the aim is
value new partners, european Samuel Bucourt,CEO of Imagine Optic : to develop a setup for wafer flat-
leaders in their respective « We brought our expertise in wavefront ness and edge control, which
field, and get them to contri- measurement and optical engineering to should both be usable on CMP for
bute with their expertise in the Pullnano consortium in 2007 and we raw silicon wafers as well as pat-
specific metrology equipment. terned wafers, in situ and in real-
developed a wafer flatness measurement ins-
« The team followed strict cri- time during the front-end process
teria to focus its activities on
trument which will also permit the measure-
(non-destructive procedure).
already existing equipment ment of mirrors in synchrotron and spatial « Flatness of the wafers is increa-
prototypes from suppliers applications. We hope to launch a series of singly crucial with optical lithogra-
which could be adapted to the standard products based on this instrument phy, due to the requirements
nanotechnology needs. For which could well represent 10 to 15% of our arising from the depth of focus to
the suppliers, the appeal was get precise structures », empha-
sales in the future. »
to become a member of the sizes Martin Schellenberger. A
Pullnano consortium and to compact industrial system (e-Xplo-
get into contact with an industry harbou- Low-K Control, the purpose is to demons- rer) based on Shack-Hartmann wavefront
ring a potential new business for them », trate a method to characterize damage to sensors from Imagine Optic as well as a
explains Martin Schellenberger. the sidewalls of low-k material structures pattern recognition wavefront sensor (Ma-
In the metrology for ultra-shallow junctions on patterned wafers caused during plasma kyoh) adapted for research, are already in
(10nm, i.e. ultra-thin structures), the ob- etching. The challenge is in the very small place at the Fraunhofer IISB. First results
jective is to provide accurate dopant pro- change in refraction index of the damaged for flatness metrology have been obtained,
files with a high degree of inherent layer. Working with IMEC, Nova Measuring with methods of calculation like cross sec-
quantification at interfaces. Starting with a Instruments completed a feasibility study tion analysis, double Gaussian filtering and
standard SIMS (Secondary Ion Mass last November, on how to measure the wa- height deviation analysis. They show an

2
 achieved resolution and ac-
curacy of 1.1mm for lateral
resolution and 50nm in verti-
cal resolution.
Finally, a Fraunhofer IISB
team is also working toge-
ther with STMicroelectro-
nics on developing an
automated fault detection
and classification solution
for low-k (2.5 or less) pore
led at the sealing processes. The
(doc. Cameca) control solution is based on
residual gas analysis (RGA),
and can be used in R&D as well as
in production.
« In parallel to the Pullnano initiative, the are funded via SEA-NET »
equipment forum worked to establish tight
contacts to the independent european In general, the metrology tool development sary to maximize productivity while main-
project for the assessment of semicon- requires the availability of state-of-the-art taining acceptable cost of ownership ■
ductor equipment for nanoelectronic
technologies (SEA-NET), where the
activities focus more on equipment
testing on a large scale, versus Pull-
nano where the focus lies on the
materials and process technolo-
gies », explains Martin Schellenber-
ger. « Currently, two projects,
related to advanced overlay
capabilities to be made availa-
ble for fabrication of necessary
Georges Antier, Vice President and standards and establishment of
Business Unit Manager of Cameca : metrology methodologies in ad-
« Ultra Low Impact Energy is a key vance of production. This re-
factor to get access to the ultimate quires a greater attention to
depth resolution in SIMS. This is a strong re- expanding close ties between
metrology development and
quest from all Cameca customers and from
process development. The co-
semiconductor analytical teams in general. operation between the metro-
The work done in Pullnano was very fruitful logy community and
for Cameca as we were able to demonstrate semiconductor fabrication is
extremely good data with both Cesium and mandatory to keep equipment
Oxygen primary ion beam. » development in Europe. But,
when the metrology is well mat-
ched to the process tools and
control and X-ray metrology and origina- processes, ramping times for pilot lines
ting from ideas in the Pullnano domain, and factories are reduced. Later on, an ap-
propriate combination of well-engineered
tools and appropriate metrology is neces-
David Scheiner, CTO of Nova Measuring Instruments :
« After gaining access to cooperation with IMEC, we will have a
unique application to offer our customers and gain a certain advan-
tage in relation to our competitors from the USA if the project is
successful, and we hope to continue cooperation with IMEC and possibly
install a metrology system to continue the development of this capability. »

VIProduct

MASTAR : A European compact

model enters the international stage
The Model for Assessment of CMOS Technology And Roadmaps
(MASTAR) was initially created by Thomas Skotnicki from STMi-
croelectronics. The main idea behind MASTAR is to predict the per-
formance trend of several type of CMOS device structures (Bulk,
Ultra Thin Films, multigates …) , while keeping a simple but phy-
sics-based approach of the transistor behavior in terms of short-
channel effects, mobility enhancement, access resistance,
innovative gate stacks etc. The tool was originally aimed at helping
device engineers who wanted to anticipate technological choices.
Illustration of the new MASTAR interface aimed at system level and
At the European level, back in 2002, the early version of MASTAR
currently under development in the Pullnano project
was used to define the performance targets of the IST-ARTEMIS
project aimed at 65nm node. From 2004, the various collaborations been developed [1]. In addition, the inclusion of a stand-alone System
with European universities and SMEs occurring through the IST-NA- Level model allows for the calculation of small circuits (ring oscillators,
NOCMOS project, allowed for the enhancement of MASTAR models SRAMs). It also takes into account the variability issues occurring in mo-
with new functionalities, such as ballistic transport, quantum calcula- dern technologies. This allows the Pullnano project to be at the leading-
tions, strained-silicon fundamentals etc. Thanks to this user-friendly ap- edge of CMOS roadmap discussions at the international forums [2] ■
proach, MASTAR was used for the definition of the 2005 and 2007
editions of the ITRS roadmap. It has thus become the established tool MASTAR is a freeware supported by STMicroelectronics.
used by the international CMOS Community. It can be download from the ITRS website: www.itrs.net
This collaborative approach continues within Pullnano, where the cou- 1] M. Sellier et al., ISQED 2008
pling between MASTAR and full circuit simulators (such as SPICE) has [2] F.Boeuf et al., Trans. Electron Devices June 2008

3
 VIP
Enrico Sangiorgi :
“Electronic industry is in the midst
of revolutionizing the traditional
CMOS device”
The continued scaling of CMOS technology is reaching a point where, due to
physical limits, new materials and device structures increasingly need to be introdu-
ced, requiring an extension of devices and circuits models in order to provide
solutions in time for forthcoming technology generations. The Device Physics cluster
in Pullnano is in charge of this task. Explanations by Enrico Sangiorgi.
Why does electrical modeling become
more important in the 32nm and below pro-
cesses?
As pointed out in the ITRS roadmap, device
characterization, modeling and simulation will
face several challenges for the 32 and 22nm
CMOS device development. In fact, the tech-
nological innovations introduced by the 32nm,
and even more by the 22nm process, may
very well revolutionize the traditional CMOS
device scenario. Today, the number of tech-
nological options is astonishingly large and in-
cludes both new materials and new device
structures, like high-k insulators in various
fashion with metal gate, ultra-thin Schottky
contact Source and Drain, uniaxial or biaxial
strained silicon channel, Single or Double-
Gate SOI devices, FINFET, Omega-Gate, and
Multi-Gate FET in general. The introduction of
some of these highly innovative structures at
the 32 and 22nm nodes will be a key element
to master the development of a competitive
new CMOS process by boosting performance
and cost reduction at the same time.
However, in the attempt to reach this goal,
A grain boundary parallel to the source/drain
junction creates a potential barrier that in-
creases the threshold voltage right across the
width of the device. (doc. University of Glasgow)
technologists face a double threat : the num-
ber of available technological choices is too
wide to allow a “try and repeat” approach and
the physical mechanisms behind the possible
advantages of new materials and new struc-
tures are largely unknown. Here is where phy-
sically based electrical modeling can play an
important role by developing and testing ad-
vanced physical models addressing the future
needs. In particular all the issues related to the
usage of strained silicon, the adoption of dif-
ferent crystal orientations for the MOSFET
channel, the use of high-k gate dielectrics, the
fluctuations of dopants, the dielectric and sili-
con layer thickness, and the effects of line-
edge roughness, as well as their impact on the
electrical parameters of the devices must be
investigated.
What is the contribution of Pullnano to this
activity ?
The Pullnano project has devoted an unpre-
cedented effort toward the development of
advanced physical models, with many acade-
mic teams grouped together to form a “De-
vice Physics” Cluster with ambitious yet clear
goals. Once implemented in device simula-
tors, the developed models will allow evalua-
ting and comparing different device
architectures and technological options, as
well as permit the calibration of the new com-
pact models needed for engineer-oriented
tools like MASTAR.
At approximately two thirds of the way along
the 30-months duration of the project, we
have carried out a thorough fundamental work
to understand effects like the electron mobility
in presence of a high-k interface and different
strained silicon channels, the degree of bal-
listic transport, which is an important source
of performance boost, as a function of the
channel material and device structure, the im-
pact of detrimental effects like off-currents of
various origins, gate current, band-to-band
tunneling, etc., as a function of the different
technological options, and, last but not least,
the modeling of the holes in the channel of the
p-MOSFETs, taking into account the quantum
mechanical effects induced by quantization in
the channel well.
Another area where the Pullnano modeling
Pioneering the modeling of
nanoscale chips…
Enrico Sangiorgi has been invol-
ved in several European projects
of the 5th, 6th, and now 7th FP
with management responsibilities.
He is currently a member of the
Executive-Scientific Committee of
the Nanosil Network of Excel-
lence, managing the modeling
activities, and a member of the
strategic board of the Integrated
Project Pullnano. Since 2006 he is
also the Vice Chairman of the
Scientific Community Council
(SCC) of the Eniac Technology
Platform and since 2007 a mem-
ber of the Steering Board of the
Eniac-related Aeneas Association.
He is currently in charge of the
nano-microelectronics group of
the University of Bologna –
Campus of Cesena. He is also the
Director of the Italian Universities
Nanoelectronic Team (IU.NET),
which is a legal consortium grou-
ping eight university groups active
in the field of nanoelectronics. His
research interests include the
physics, characterization, mode-
ling, and fabrication of silicon
solid-state devices and integrated
circuits. In order to tackle and
eventually overcome the hurdles
of device scaling, down to the ulti-
mate physical and technological
limits, he has devised and develo-
ped several original concepts and
methods in the characterization
and modeling of nanoscale silicon
devices.
Enrico Sangiorgi coauthored 33
IEDM papers and published more
than 150 papers in international
journals and conference procee-
dings. He is a Fellow of the IEEE,
a Distinguished Lecturer of the
Electron Device Society and
Chairman of the Electron Device
Society TCAD Technical Com-
mittee. He has been Editor of
IEEE ELECTRON DEVICE
LETTERS since 1994.
4
 E n r i c o S a n g i o r g i
team has made impor-
tant progress, is the
study of the effects of
statistical device variabi-
lity due to intrinsic
sources, e.g. discrete
dopant distribution, line
edge roughness, etc.
This issue is becoming crucial because at na-
A 3-D analysis shows the impact of surface potential pinning and doping nonuniformity in
noscale dimensions the matter itself become
the gate and the dependance on grain boundary orientation (Poly-Si gate variability) :
discrete! The team at the University of Glas- (a) pinning in the middle of the band gap ; (b) increased doping concentration around the
gow, a world authority in this field and part of grain boundaries ; (c) combination of (a) and (b). (doc. University of Glasgow)
the Pullnano Device Physics Cluster, has des-
cribed for the first time in two recent publica- the best technological options (materials and Could you give details about the impact of
tions originated by Pullnano, the effect of the device architecture) available for the 32 and IUNET* on Pullnano ?
Poly-Si gate related variability in decanano- 22nm nodes. Last but not least, the results of The IUNET scientists are strongly contributing
metre MOSFETs with conventional architec- the device simulation will be “lumped” in up- to most aspects of the modeling effort in the
ture and the quantitative evaluation of graded compact models, starting with MA- Pullnano project and share the same spirit of
statistical variability sources in a 45nm tech- STAR which is a handy tool for engineers who cooperation which has been the key aspect
nology. want to compare the influence of different sustaining the success of IUNET with all the
At the same time, we are working on the stan- technological choices on device performance. other members.
dardization of the so-called “template de-
vices”, i.e. “ideal” structures, used by all
Unstrained silicon Strained silicon
partners to implement and test the models
and at the same time fabricated by the main
technological Pullnano partners to provide the
necessary experimental feedback to the theo-
retical modeling effort.

What is the agenda for the Device Physics

cluster through the end of this project?
We are now entering the last and crucial part
of the project. Most of the models ingredients
have been developed and implemented in the
simulation codes developed by the different
groups. These simulation codes reflect the dif-
ferent degree of complexity required to tackle
the fundamental physical phenomena (quan-
tum effects for example!) and attain a global
view of the device performance versus the dif-
ferent technological options. In the next 8
months of the project, the Device Physics
cluster will be busy comparing the results of
the newly developed models and the imple-
mentations in the different simulation codes
featuring different degrees of complexity. This
will be done with the experimental data star-
ting to become available from the technologi-
cal partners. A rigorous comparison will allow
to measure the degree of confidence in the
new models and get some first ideas about
When considering the silicon hole band structure (at a fixed energy) for the "regular" (unstrai-
ned) and strained silicon, it is visible that holes in strained silicon behave in a completely diffe-
rent way, as if it were "another" material and not just an "enhanced" material (doc. IUNET)
As per specific examples, at last December
*IUNET : the Italian Universities IEDM, IUNET has presented the “first time”
Nanoelectronic Team examination of the experimental extraction
IUNET is a consortium of leading Italian procedure for the so called “ballistic-ratio”
universities which are active in the field which is a measure of the degree of ballistic
of nanoelectronics. The IUNET mem-
bers contributing to the Pullnano pro- transport achieved in nanoMOSFETs . The
ject, namely the universities of “surprise” is that the ballistic-ratio extracted
Bologna, Milano, Pisa, and Udine, have applying this so far well established procedure,
a long standing tradition in the field of severely underestimates the actual degree of
semiconductor device physics and mo- ballisticity achieved by modern technologies.
deling. At the last IEDM conference in
Washington D.C. , IUNET was repre- One further example is the development of the
sented with 10 papers, a number simi- first “multi-subband” Monte Carlo simulator for
lar to the top industrial companies and the drain current of nanoscale p-MOSFET
research institutions (e.g. Stanford, which has been presented by IUNET at the re-
IBM, Toshiba, Samsung, etc.). cent ULIS Conference in Udine ■

“Pullnano and the earlier projects like Nanocmos, have played a

crucial role in creating a large scientific and industrial community of world-
top researchers who learnt to work together. This is an extremely important
heritage, of which the European Community should be proud of, and
which we must carefully
nurture and further develop. ”
5
 VIMaterial refore, a more pressing problem may be crea-
ting a stable amorphous or monocrystalline

High-K material dielectric material without trap assisted or

grain boundaries generated leakage mecha-
Will Gadolinium succeed to Hafnium ? nisms. On top of that finding an amorphous
dielectric materials able to withstand the 900-
Over the last decades, transistor scaling has been relatively easy, 1000°C without crystallization is a challenge of
with SiO2 the gate oxide of choice. Today, the R&D is still in full 64 importance.
swing for the 22nm node, with the dedicated Pullnano academic It has already been demonstrated that rare-
cluster looking at the High-K material of the future. earth-oxides can be stabilized in the amor-
phous phase by converting them into silicates.
For generations, SiO2 with tage. In an overview of At the same time this conversion consumes
its dielectric constant at 3.9 A possible dielectrics for the the native SiO2 interface layer. The High-k-
was the perfect gate oxide. 22nm bulk LSTP (low Group is presently focusing its efforts on ma-
The leakage current increase standby power) techno- king stable gadolinium silicates starting from
due to continued thinning logy (1), the Pullnano High- the already favourable gadolinium oxide
has required the switch to k-Group compared the Gd2O3, The results are encouraging, with a
gate materials with a higher B leakage current between total equivalent oxide thickness reduced after
dielectric constant (“k different dielectrics. For annealing while the k-value of this part of the
value”). After hafnium-based example, it included an stack slightly increased from 14.4 to 15.5.
dielectrics at the 45nm and estimate of band offset vs Composition analysis shows that the final ga-
(a) TiN/Gd2O3/SiO2 stack as deposited
32nm nodes, there could dielectric constant as re- dolinium rich layer contained about 10% sili-
(b) TiN/GdSiO/SiO2 stack after 900C/1s an-
well be another switch at neal. Notice the change in SiO2 thickness. quired by the 22nm node. con. Electrical characterization is on going. The
22nm by stepping to another The ideal dielectric has to academic cluster is optimistic; atomic number
area of the periodic chart to gadolinium-based fullfill a combination of properties better trans- 64 Gadolinium will give a good fight to atomic
dielectrics, for example.Ideally, the gate oxide lated by a highest possible product between number 72 Hafnium ! ■
should function as isolation (with a band gap > offset value and k-value; thus, increasing one For more information: Olof Engström
5 eV), show a thermodynamic stability with si- of these quantities allows for decreasing the e.mail : olof.engstrom@mc2.chalmers.se
licon, form a good electrical interface with sili- other. For so called “fully depleted double gate (1) The ITRS roadmap specifies transistors for high perfor-
con, have the least possible number of SOI transistors”, the conditionsare such that mance (HP) logic, low standby power (LSTP) logic and low
operating power (LOP) logic, in different types like FD DG
defects, be compatible with today's fabrica- the requirements compared with standard (fully depleted double gate) SOI or planar bulk SOI, etc. The
tion techniques (stability at process tempera- “bulk” transistors can be considerably relaxed. LSTP type is generally dedicated for mobile consumer ap-
tures of about 1000°C). That's why scientists From figure 1, one can see that a number of plications, and therefore one of the main target in european
research.s
are currently working on many different solu- materials, matching the requirements, are avai-
tions using materials with a dielectric constant lable. The limiting curves are calculated by as-
Dissemination
between 8 and 24, together with a gate elec- suming that the current is determined by direct
trode stack from grainy polycrystalline silicon tunnelling. As a number of possible oxides are
to pure metal, and various poly+metal combi- on the right side of this limit, one may conclude Training Events 2008
nations in between. that the most important problem for future gate ULIS 2008: 12 March 2008, Udine, Italy
“Device aspects from a circuit point of view”
dielectrics will be to keep under control lea- (Pullnano lecturers)
Already a low leakage candidate in its oxide kage mechanisms other than tunnelling. The- AEC/APC 2008: 9th European Advanced
Control/Advanced Process Control on 31 March
phase 2008, Tel Aviv, Israel
However, in the quest of “General Introduction to APC”.
ESSDERC/ESSCIRC 2008: on 15 September
gate dielectrics for the 2008, Edinburgh, UK
22nm node, rare-earth “Characterization and Metrology for advanced
Si technologies”.
oxides are of primary inte- Dedicated schools
rest in spite of their typi- MIGAS 2008: on 28 June - 4 July 2008, Autrans,
France
cally low dielectric “Nanoscale CMOS and Si-based Beyond-CMOS
constants in the range of Nanodevices“.
SINANO Summer School: on 1-5 September
12 to 15 for the k value. 2008, Bertinoro, Italy
The reason is that lower k “Device-Modeling”.
Other events
values are connected with Workshop (ESSDERC/ESSCIRC 2008)
high energy barriers “CMOS variability research in Europe : from atomic
scale to circuits and systems”
(“band offset values”) for Courses at IMEC
electrons to penetrate “Plasma Etching for CMOS Technology and
ULSI Applications”:
from the silicon crystal, 3-day course on 13/5-15/5
which in turn contributes “Silicon-on-Insulator” :
2-day course on 15/5-16/5
to keep tunnelling currents Fig.1
“Silicon Processing for sub-90nm circuit fabrica-
low, i.e. a decisive advan- Borders for the 22nm LSTP node : bulk node (blue curve), FD DG SOI (red curve) tion” : 3-day course on 11/6-13/6
Symposium “Advanced Physical and electrical
characterization”, end of 2008
Director of Publication : Gilles Thomas (ST) PULLnano is a project supportyed by the Euro- Date and location still to be confirmed
Managing Editor : Chantal Cochini email : nano32@lops.fr pean Commission from the IST Programme
Contributing Editor : Elizabeth Feder within the European Union 's Sixth RTD Fore more information : Herman MAES,
For more information on Pullnano: WWW.pullnano.eu Framework programme. e.mail : maesh@imec.be