IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO.

10, OCTOBER 2004 1953

Parasitic-Aware RF Circuit Design and Optimization

Jinho Park, Kiyong Choi, and David J. Allstot, Fellow, IEEE

Abstract—RF circuit synthesis techniques based on particle

swarm optimization and adaptive simulated annealing with
tunneling are described, and comparisons of parasitic-aware
designs of an RF distributed amplifier and a nonlinear power
amplifier are presented. Synthesized in 0.35- m digital CMOS
using a single 3.3-V power supply, the designs provide an 8-dB
gain and 8-GHz bandwidth for a four-stage distributed amplifier,
and 1.2-W output power with 55% drain efficiency at 900 MHz
for a three-stage power amplifier. A standard circuit simulator,
HSPICE or SPECTRE, embedded in an optimization loop is used
to evaluate cost functions. The proposed design and optimization
methodology is computationally efficient and robust in searching
complex multidimensional design spaces.
Index Terms—RF integrated circuits, RF circuit synthesis, sim-
ulated annealing, particle swarm optimization (PSO).

I. INTRODUCTION

T HE burgeoning demand for system-on-chip (SOC) solu-

tions has stimulated intense worldwide research on CMOS
RF integrated circuits. However, the issue of parasitics associ-
ated with CMOS active components that are inferior to their
GaAs and SiGe counterparts, and on-chip passive components
on lossy silicon substrates, has impeded development. Without
the use of parasitic-aware design and optimization tools, many
RF circuits are difficult to synthesize in fine-line CMOS tech-
nology owing to detuning effects associated with omnipresent
nonlinear parasitic components.
Several synthesis approaches that optimize the performance
of CMOS RF and analog integrated circuits using the simulated
annealing algorithm have been developed [1]–[3]. In contrast
to conventional gradient-descent optimization methods, simu-
lated annealing avoids being trapped in local minima in the
design space using a hill climbing heuristic that is analogous
to the physical process of annealing a solid [4], [5]. In that
process, molten metal is poured into a mold at a high tempera-
ture and then cooled so that the constituent atoms organize into a
minimum energy state. Ideally, simulated annealing circuit syn-
thesis begins at a high temperature and cools at an optimum rate
to find the lowest cost solution in the design space. In com-
plex problems, however, it often gets trapped in local minima
Manuscript received January 9, 2003; revised April 12, 2004. This work was
supported in part by the U.S. Defense Advanced Research Project Agencies
NeoCAD Program under Grant N66001-01-1-8919, by the National Science
Foundation under Grant CCR-0086032 and Grant CCR-0120255, by the Semi-
conductor Research Corporation under Grant 2000-HJ-771 and Grant 2001-HJ-
926, and by the National Semiconductor, Corp., and Texas Instruments, Inc.
This paper was recommended by Associate Editor A. Hajimiri.
J. Park and K. Choi were with the Department of Electrical Engineering, Uni-
versity of Washington, Seattle, WA 98195-2500 USA. They are now with Mar-
vell Semiconductors, Sunnyvale, CA 94089 USA.
D. J. Allstot is with the Department of Electrical Engineering, University
of Washington, Seattle, WA 98195-2500 USA (e-mail: allstot@ee.wash-
ington.edu).
Digital Object Identifier 10.1109/TCSI.2004.835691
1057-7122/04$20.00 © 2004 IEEE
Fig. 1. Parasitic-aware design and optimization flow. The circuit simulator
is HSPICE or SPECTRE. A compact model generator provides the parasitic
modeling function. The optimizer uses ASAT or PSO.
when the temperature cools too quickly so that hill climbing is
disabled prematurely. Moreover, it is inherently slow because
it approaches the global minimum only after conditionally ac-
cepting a costlier solution. In this paper, parasitic-aware RF cir-
cuit design and optimization techniques using particle swarm
optimization (PSO) and adaptive simulated annealing with tun-
neling (ASAT) are presented.
PSO draws inspiration from the observations of social sci-
entists of group behavior; e.g., birds flying in search of food
compete as individuals but cooperate as a flock to adjust their
flight trajectories [6]. PSO initially positions solution candidates
(i.e., particles) randomly in a multidimensional design space. At
each iterative step, the particles exchange information to update
their movements toward the global minimum. Since PSO oper-
ates concurrently on a population of particles rather than a single
solution candidate, it is potentially faster and more robust than
simulated annealing [7].
It is difficult to predict the requisite coefficient values for
conventional simulated annealing; e.g., the temperature coeffi-
cient Temp used in the cooling schedule is notoriously problem
dependent. The ASAT heuristic avoids this classical problem
by adaptively controlling Temp to eliminate unnecessary hill
climbing iterations. A local search algorithm also increases the
computational efficiency of the ASAT algorithm.
The general parasitic-aware synthesis flow for RF integrated
circuits includes three major functional blocks (Fig. 1). The
optimization core comprises ASAT or PSO, the circuit simu-
lator is HSPICE or SPECTRE, and the parasitic modeling block
1954 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004

Fig. 2. Final four-stage CMOS RF distributed amplifier after parasitic-aware synthesis [8], [9].

is a compact model generator (e.g., [19]). In Section II, sim-

ulated annealing is briefly reviewed and the PSO and ASAT
approaches are motivated. Parasitic-aware RF circuit synthesis
using ASAT and PSO optimization cores is described in Sec-
tions III and IV, respectively. Comparisons between simulated
annealing and ASAT for a simple cost function are also made
in Section III. Section IV details the PSO paradigm and of-
fers insights into the selection of its parameter values. A com-
pact model generation method as applied to on-chip spiral and
bond wire inductors is reviewed in Section V. In Section VI,
PSO and ASAT are compared to simulated annealing in the par-
asitic-aware synthesis of two CMOS RF circuits: a four-stage
distributed amplifier and a three-stage power amplifier. The cri-
teria for comparison are computational efficiency, robustness,
and balance between global and local search capabilities. Con-
clusions are given in Section VII.

II. SIMULATED ANNEALING SYNTHESIS

A four-stage distributed amplifier in 0.6- m CMOS with
6.5-dB gain over a 0.5–5.5-GHz bandwidth demonstrates
the essential need for parasitic-aware RF circuit synthesis
[8]; Fig. 2 details the final design obtained using simulated
annealing optimization. The simulated frequency responses
of Fig. 3 show good agreement between the analytic design
without parasitics and the final parasitic-aware design, which
actually achieves superior pass-band characteristics. Without
parasitic-aware optimization, parasitics de-tune the design
as shown. Measurements on CMOS prototypes show close
agreement with simulations [8].
The parasitic-aware synthesis flow comprises three major
functional blocks (Fig. 1). The circuit simulator evaluates can-
didate solutions using HSPICE or SPECTRE using complex
active and passive device models; it is the most expensive
computational function. For example, the CMOS four-stage
distributed amplifier of Fig. 2 [8] was optimized using a sim-
ulated annealing optimization core. Although there were only
Fig. 3. Simulated gain and phase responses of a four-stage CMOS
distributed amplifier [8], [9]. There is good agreement between the analytic
design excluding parasitics and the final design including parasitics after
parasitic-aware optimization. The analytic design with parasitics before
optimization exhibits unacceptable errors.
nine design variables, each optimization run required about
5000 iterations and one day of CPU time on a Hewlett-Packard
712/100 Unix workstation. For more complex RF circuit
designs, the number of design variables is expected to grow
exponentially [9]. Hence, more efficient optimization methods
are needed to reduce cost by reducing the requisite number of
iterations and circuit simulations.
This paper presents an ASAT heuristic and a PSO technique
that are more efficient and robust than simulated annealing. Syn-
thesis results for a power amplifier and a distributed amplifier
are also described.
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION
Fig. 4. (a) Hill climbing in conventional simulated annealing. (b) Tunneling in ASAT for a cost function versus design variable
Fig. 5. Flowchart for the tunneling heuristic used in the ASAT algorithm.
III. ASAT
The ASAT heuristic includes a tunneling technique, a local
optimization method, and an adaptive temperature coefficient
(Temp) algorithm.
A. Tunneling Technique
A well-known advantage of simulated annealing is its hill
climbing capability determined by the temperature coefficient,
Temp, in the cooling schedule and the slope of the cost function.
Showing a simple cost function that depends on a single design
variable , Fig. 4(a) depicts conventional hill climbing wherein
there is a nonzero probability of escaping local minima in search
of the global minimum. However, when Temp is low and the
hill is steep, many iterations are wasted traversing from A to B
though there are only higher cost candidate solutions between
them. Using the technique of Fig. 4(b), the optimizer senses a
hill climb at A and invokes tunneling through it.
1955
X.
The tunneling process is controlled by two empirical coeffi-
cients: Tunneling threshold and tunneling radius. The tunneling
threshold determines the beginning of a climb where tunneling
is invoked. Tunneling radius denotes the maximum distance that
a simulation point tunnels in the design space. The tunneling
radius is more critical. If it is too small, the probability of tun-
neling is low, but if it is too large, the simulation point tunnels
so far that the optimum is not found. Fig. 5 charts the tunneling
heuristic. When tunneling occurs, a fraction of tunneling radius
is added to the previous design variable values to determine the
new values. To illustrate its performance, a cost function is de-
fined as
COST (1)
Fig. 6 validates the tunneling technique. In contrast to simulated
annealing [Fig. 6(a)], the tunneling algorithm in Fig. 6(b) wastes
little time crawling over cost-function hilltops, explores all pos-
sible minima, and frequently finds the optimum solution.
1956 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004
Fig. 6. Results from 30 simulation runs. (a) Simulated annealing wastes
iterations crawling over cost function hilltops and fails to find the optimum. (b)
The ASAT algorithm effectively explores all minima and frequently finds the
global minimum.
B. Local Optimization Method
As simulated annealing optimization progresses, Temp is de-
creased in compliance with the cooling schedule to emphasize
local, rather than global, search capabilities. However, even
when Temp is small, it determines the values of the design vari-
ables randomly at the next simulation point. Consequently, it is
notoriously inefficient as it approaches an acceptable solution.
An improved local search strategy uses a history vector
defined between the previous and present simulation points
(Fig. 7). In simulated annealing, a fraction of random vector
is added to the present design vector to determine the next
state; herein, a weighted sum of vectors and defines the next
point. A temperature-dependent weighting factor determines
the balance between local and global search capabilities: if
Temp is large, the random component dominates, which em-
phasizes the global search capability and vice-versa. The next
optimization point is
stepsize
where is proportional to Temp.
C. Adaptive Temperature Coefficient Heuristic
Temp is critical in simulated annealing in minimizing the
number of iterations. Fig. 8 relates Temp and the cost func-
tion slope. If Temp is too large, global search dominates and
Fig. 7. Improved local search strategy. The history vector ~
y is defined between
the previous (Z ) and present (Z ) design points. The next simulation
point (Z ) is a weighted sum of the history vector ~
y and the random vector
~x. If Temp is small, the history component dominates and vice-versa.
Fig. 8. When the slope of the cost function hill is steep, Temp, should be large
and vice-versa.
iterations are wasted, and if Temp is too small, local search
dominates and the optimizer gets stuck in a local minimum.
The optimum value of Temp depends on RF circuit topology;
i.e., high Temp is required for circuits with steep cost functions
and vice-versa [10], [17]. Greater computational efficiency is
achieved adapting Temp using an estimate of the cost function
slope [18]. Moreover, the adaptive method eliminates the need
to guess an initial value of Temp. An implicit relationship
between Temp and the cost function slope is given in (3a).
Temp is adapted by replacing the random number with a fixed
parameter , solving for Temp, and averaging as in (3b)
cost cost old
(3a)
cost cost old
(3b)
accepted
Fig. 9 charts a flow for adaptively determining Temp. For a given
topology, experience shows that an estimate of Temp obtained
(2) from iterations within the first optimization loop
is sufficiently accurate for further optimization cycles. All pos-
itive cost-function differences between iteration points within
the first loop are weighted and averaged to estimate Temp. (Of
course, Temp can be estimated using additional loops.)
Whereas the adaptive Temp algorithm eliminates the need for
an initial value of Temp, an empirical parameter, , is
introduced. It represents the initial probability of hill climbing
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION
Fig. 9. Flowchart of the adaptive temperature coefficient heuristic used in the ASAT algorithm.
and ranges from 0.70–0.90; i.e., it determines the balance be-
tween global and local search capabilities. An advantage of this
approach is that is not topology dependent as is Temp.
IV. PSO
PSO works with a large population of potential solution
candidates called particles. Hence, the inherently parallel
approach of PSO is potentially faster than simulated annealing.
PSO also gains advantages over alternative population-based
optimization algorithms owing to its unique swarming capabil-
ities. Moreover, its describing equations are simple and easily
implemented in the core optimization block.
A. PSO Theory
Social scientists have observed that swarming in search of
food differs from other animal behaviors in that individuals
benefit from the discoveries and experiences of all other group
members [6]. Swarming behavior is observed in flocks of birds,
schools of fish, swarms of bees, etc. PSO mimics the swarming
behavior [7]. An obvious advantage is its simplicity; it is
easily implemented in the core optimizer using the describing
equations in Fig. 10.
The motion of an object in PSO is represented as the vector
sum of present position and velocity vectors (Fig. 10). The
second equation that details the algorithm for updating the par-
ticle velocity comprises three vectors: inertia, competition, and
cooperation. The cooperation vector links the current position
of a particle to the position of the particle that enjoys the
best global position ; it is weighted using a uniformly
1957
Fig. 10. Describing equations for PSO. The position of a particle at the next
iteration step is given by the sum of its current position and velocity vectors.
The next velocity vector is a sum of weighted inertia, and randomly weighted
competition and cooperation vectors.
distributed random function. Each member of the group gains
knowledge of the globally best position by cooperating and
communicating with all other particles. The competition vector
links the current position of a particle to its personal best
position ; it is weighted using a second uniformly
distributed random function. The competition factor describes
the tendency of a particle to explore the vicinity of its own
personal best position. Finally, the inertia vector represents the
tendency of a particle to maintain its current velocity ; it
is weighted by a constant . PSO cleverly combines inertia,
competition, and cooperation in an optimum fashion so that the
particles swarm to the best solution.
Whereas it is clear that cooperation among particles is essen-
tial for finding the global optimum solution, the need for the
inertia and competition is not obvious; the main reason for in-
cluding them is to avoid trapping in local minima. To appreciate
this point, consider a four-particle example (Fig. 11) in which
cooperation (Fig. 10) is activated but inertia and competition are
1958 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004
Fig. 11. Four-particle PSO example with the cooperation factor enabled and the inertia and competition factors disabled. Performance depends on the initial
particle positions. For the initial positions shown, the particles miss the global optimum and converge on a local minimum.
disabled. The probability of finding the global optimum without
being trapped in a local minimum depends on the initial posi-
tions from which the particles fly straight toward the known best
position. In the example, the particles converge on a local min-
imum without ever experiencing the global optimum. This be-
havior is reminiscent of gradient-descent algorithms.
Trapping in local minima is avoided using the complete PSO
formulation (Fig. 10). In Fig. 12(a), four particles are positioned
with the rightmost particle initially occupying the best position.
The particles move according to a randomly weighted sum of
inertia, competition, and cooperation vectors. Notice that PSO
encourages the particles to travel in different directions to ex-
plore different regions of the design space. After the first iter-
ation, the leftmost particle experiences the lowest cost, and the
positions after a second iteration are shown in Fig. 12(b); PSO
allowed the rightmost particle to escape the local minimum. All
particles quickly swarm toward the optimum solution.
The weighting of the inertia, competition, and cooperation
factors is important in determining the efficiency and robust-
ness of PSO. Because it is intuitively appealing to assign the
same weight to each vector, the factors, , and
are chosen to have average values of one; hence,
. In some cases, is adjusted to be less than 1 for
faster convergence. This issue is revisited later.
B. PSO Procedure
PSO begins with the population of particles assigned random
initial positions in the design space. Each particle is also given
an initial random velocity (Fig. 13). As PSO progresses, each
particle keeps track of its best solution, Pbest, while the whole
group keeps track of the overall best solution experienced by any
particle, Gbest. Particle swarming continues until a sufficiently
low-cost solution is found, or a maximum number of iterations
are executed. PSO for parasitic-aware synthesis is charted in
Fig. 14.
C. PSO Parameters
The inertia weighting factor is important in determining the
balance between global and local search capabilities. If it is too
large, PSO emphasizes global searching and is slow, and if it is
too small, it emphasizes local searching and gets trapped in local
minima. Another important optimization parameter not shown
in Fig. 10 is , which limits the maximum particle velocity
and effectively limits its range of movement between iterations.
The size of the population in PSO is less critical than in other
population-based algorithms: two to three times the number of
design variables is generally effective [6].
Nonlinear power amplifier (22 particles) and RF distributed
amplifier (55 particles) designs are used to investigate the im-
pact of the parameters on PSO optimization. Twelve synthesis
runs were performed for each circuit for nine combinations of
and . The failure rate, the percentage of runs that did not
find an acceptable solution within the maximum number of it-
erations (5000 for the distributed amplifier and 20 000 for the
power amplifier), is plotted in Fig. 15. In this comparison, an
iteration in PSO is an update of only one particle. Statistics of
the number of iterations versus parameter values are shown in
Fig. 16; in these examples, and are op-
timum. Additional details are presented in Section VI.
V. COMPACT MODELS FOR PASSIVE COMPONENTS
On-chip inductors, transformers, micro-strip transmission
lines, and coplanar wave-guides are ubiquitous in impedance
matching networks, resonant circuits, etc. The parasitic-aware
synthesis paradigm ensures that parasitic components do not
limit circuit performance. Hence, parasitic modeling is a key
component as indicated in Fig. 1.
The use of on-chip spiral inductors provides increased
integration. However, their performance is inferior to their
off-chip counterparts owing to parasitic elements. Fig. 17
shows cross-sectional and top views of a square spiral inductor
[10]–[12]. Process and design parameter information is needed
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION 1959

Fig. 12. PSO example. (a) At the initial positions the rightmost particle has the lowest cost. For the first iteration, the particles move based on the weighted inertia,
cooperation, and competition factors. The leftmost particle now occupies the best position. (b) Particle positions after the second iteration. PSO encourages the
rightmost particle to escape the local minimum. Note particle swarming toward the optimum.

Fig. 13. Initial conditions for PSO. In this example, the four particles are assigned random initial positions and velocities.

to develop accurate compact circuit models. Process informa- the substrate, metal thickness, substrate resistivity, etc. Design
tion includes oxide thickness between the metal layers and parameters are metal width , number of turns , center
1960 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004

Fig. 14. Flowchart of PSO as used in the core optimization block of a parasitic-aware RF circuit synthesis tool.

Fig. 15. Performance results for 12 parasitic-aware PSO runs versus v and w . (a) Four-stage distributed amplifier. (b) Three-stage power amplifier. The failure
rate is the percentage of synthesis runs for which an acceptable solution is not found within the maximum number of iterations. v = 0:1 and w = 0:80 work
well for both examples.

spacing , and metal line spacing . The relationships between inductor in 0.35 m CMOS. Design parameters for the metal-3
the parasitic component values and the design and process pa- spiral are: turns, m, m, and
rameters are complex and difficult to model accurately. Fig. 18 m. The spiral provides 9 nH of inductance with a
displays the measured impedance versus frequency for a spiral peak of 4 at 3.2 GHz.
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION 1961

Fig. 17. Cross-sectional (left) and top (right) views of a parasitic-laden 2 turn
monolithic square spiral inductor. A compact  -model circuit is also shown.

Fig. 18. Measured impedance of a square spiral inductor in 0.35 m CMOS.

Design parameters for the metal-3 spiral are: N = 6:25 turns, W = 15 m,
S = 101:4 m, and D = 1:2 m.

Fig. 19. Parasitic component values for the compact  -model of Fig. 15
versus square spiral inductance in 0.35 m CMOS. Design parameters for the
metal-3 spirals are: W = 15 m, S = 101:4 m, and D = 1:2 m. x denotes
measured or MOMENTUM simulation value; ‘—’ indicates the describing
equation obtain using the polyfit function of MATLAB. Representative
polynomials are shown.

desired range of values. Fig. 19 shows , and

versus inductance from 1 to 18 nH using the same design
parameters as above. Several steps are used to generate Fig. 19.
1) Fabricate and measure small, medium, and large inductors
Fig. 16. Statistics for v and w . (a) Average number of iterations. (b) that span the desired range of inductances.
Standard deviation of the number of iterations for the four-stage distributed 2) Calibrate MOMEMTUM so that its results match the
amplifier and the nonlinear power amplifier. three sets of measured results.
3) Use MOMENTUM (calibrated) to determine parasitic
Parasitic-aware optimization requires parasitic component component values for several inductances interpolating
values expressed as functions of the design variables over a the range.
1962 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004

Fig. 21. Four-stage CMOS distributed amplifier with artificial LC gate and
drain delay lines.

Fig. 20. Bond wire inductor connected between two on-chip bonding pads.
Key parasitics that need to be modeled include the N -well and substrate
resistances and capacitances.

4) Finally, use the polyfit command in MATLAB, or a sim-

ilar curve-fitting tool, to fit equations to the measured and
simulated points (Fig. 19).
The fitting equations are compatible with HSPICE or SPECTRE
netlist descriptions that enable on-the-fly compact model gener-
ation for use in the optimization loop.
A bond wire inductor has several advantages. It is often made of
gold, rather than aluminum, and its radius is large (about 30 m)
compared to the dimensions of the spiral. Consequently, its se-
ries loss resistance is much smaller and its quality factor is much Fig. 22. (a) Three-stage (class-AB, class-E, class-E) power amplifier showing
larger. Fig. 20 depicts a bond wire and its important parasitics. The the desired gain and drain efficiency () distributions. (b) CMOS circuit
implementation details.
bondingpadscontributeconstant and valueswithrespect
to the length of the wire. Repeatability of bondwire inductors has
been a concern. However, it has been shown that machine-bonded A. Four-Stage Distributed Amplifier
wires exhibit less than % inductance variations and less than The four-stage distributed amplifier (Fig. 21) used two artifi-
% variations in manufacturing [13]. cial LC delay lines. One, the gate line applies delayed versions of
the input RF signal to the four gate terminals. The other, the drain
VI. PARASITIC-AWARE OPTIMIZATION RESULTS line adds the drain signal currents constructively in the load re-
For a given circuit topology, the optimization core updates the sistor. Cascode transistors reduce the Miller effect by imposing a
design variable values and the associated parasitic components low impedance at the drains of the amplifying devices. Cascoding
at every iteration, and provides an updated netlist. The simula- also reduces capacitive coupling between the artificial transmis-
tion output is then used to compute the cost. Iterations around sion lines and increases gain flatness, reverse isolation, stability,
the optimization loop continue until a predetermined cost func- and input and output impedance matching accuracy. Finally, the
tion objective is met. For the examples of this section, the cost high output impedance of the cascode configuration reduces gain
function is loss associated with loading on the drain line.
An LC transmission line exhibits an intrinsic mismatch at each
COST (4) termination point due to image impedance variations with fre-
quency. Hence, -derived half sections are inserted to improve
the impedance matches to the delay lines [14].
where is a weighting coefficient, is a performance ob-
In order to increase gain flatness and decrease gain peaking
jective to be optimized, and and are the optimization
near the cutoff frequency, a staggering technique is frequently
target and the worst case specification, respectively. Thus, the
used in distributed amplifiers [15]. Staggering means adopting
cost function translates a multidimensional design space into a
slightly different cutoff frequencies for each delay line in order
single expression that is easily evaluated. The optimizer then
to increase the linearity of the phase response. Designing the
updates the design variables according to the cost. This process
gate line to have a higher cutoff frequency improves gain flat-
repeats until the optimum is found or a maximum number of it-
ness.
erations are executed.
Assuming matched impedances at the input and output
In this section, applications of parasitic-aware synthesis using
ports, the cutoff frequency, characteristic impedance, and low
the ASAT and PSO algorithms to the synthesis of a distributed
frequency gain are
amplifier and a power amplifier are described, and compared to
simulated annealing. A 0.35- m digital CMOS process is used
(5)
for both amplifiers.
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION
Fig. 23. Averages (AVG) and standard deviations (STD) of the number of iterations for PSO, ASAT, and SA for (a) four-stage distributed amplifier, and (b)
three-stage power amplifier.
(6)
(7)
where is the small-signal transconductance of the active de-
vices [16]. The term in (7) indicates the unique property of
gain addition in a distributed amplifier.
Key amplifier specifications are a constant gain greater than 8
dB over a bandwidth greater than 8 GHz with linear phase over
the full bandwidth. The input and output ports are matched to
50 , and the distributed amplifier operates from a single 3.3-V
power supply. Eleven design variables are used in optimizing
the design including all on-chip inductor and capacitor values.
B. Three-Stage Class-E Power Amplifier
A class-E power amplifier uses a transistor as a switch and
capacitors and inductors to minimize the overlap between the
1963
current and voltage waveforms to achieve high efficiency. It is a
nonlinear power amplifier suited to digital modulation schemes
such as GMSK, MSK, etc.
Fig. 22 shows a three-stage power amplifier with gain and
drain efficiency distributions. Fig. 22(a) achieves a 30-dB
gain with 50% drain efficiency; drain efficiency of the third stage
is most important because of its large output power. Hence, the
last two stages are class-E for high drain efficiency and the first
stage is class-AB for high gain. The first two stages use spiral in-
ductors and all choke inductors use bondwires. To obtain a 1-W
output power, the resistance presented by the matching network
needs to be about 5 . Hence, a bondwire inductor is used in the
third stage. Cascodes are used to reduce the voltage stresses on
the FETs. The cost function components are output power and
drain efficiency. To optimize the power amplifier, 22 design pa-
rameters are considered including all device sizes and bias con-
ditions; the goal is 55% drain efficiency with 1.2 W of output
power.
1964 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004
Fig. 24. Average costs versus iterations for (a) the distributed amplifier and
(b) the power amplifier.
C. Comparative Results
For comparison purposes, the best parameter settings are used
for all optimization runs. Since Temp is critical for both the sim-
ulated annealing and ASAT algorithms, the adaptive Temp coef-
ficient algorithm is used in both. For particle swarm,
and is chosen for both amplifiers as explained earlier.
Fig. 23 compares three different optimization approaches for
12 synthesis runs. The distributed amplifier is optimized using
11 design variables and the power amplifier has 22. For the dis-
tributed amplifier, all three optimization techniques find an ac-
ceptable set of design parameters to achieve a flat-gain response
within a reasonable number of iterations. Both PSO and ASAT
converge more than twice as fast as simulated annealing. The
standard deviations of the number of iterations indicate sim-
ilar robustness for all three approaches. For the power ampli-
fier, simulated annealing is poorer in both average and standard
deviation; the search space is larger for this example and it has
difficulty converging to the optimum.
Fig. 24 plots costs versus the number of iterations for the
various methods. For the power amplifier, PSO and ASAT ini-
Fig. 25. (a) Forward gain magnitude (S in decibels) results. (b) Forward
gain phase results.
tially perform poorer than simulated annealing. One reason is
that PSO in our examples generates the particles in a serial
fashion, even though PSO is an inherently parallel approach,
to provide a worst-case comparison to the other approaches. It
updates the velocity and position of each particle, and deter-
mines the cost after the whole group of particles is created. Thus,
PSO appears slow at the beginning of the optimization process.
In ASAT, the adaptive tunneling process emphasizes the global
search at the beginning, resulting in a slow pace. As optimiza-
tion progresses, both techniques achieve superiority over sim-
ulated annealing, which wastes iterations hill climbing as de-
scribed earlier. As the constraints become tighter and as itera-
tions increase, the discrepancy between PSO or ASAT and sim-
ulated annealing widens as detailed in Fig. 24. PSO is powerful
in reducing the computation cost due to cooperation among its
particles. ASAT is also more effective owing to its novel local
search algorithm. Both PSO and ASAT exhibit a very good bal-
ance between global and local search capabilities. Overall, PSO
and ASAT outperform simulated annealing by more than 2X.
PSO is 15% faster than ASAT in both examples.
PARK et al.: PARASITIC-AWARE RF CIRCUIT DESIGN AND OPTIMIZATION
Fig. 26. Simulation results with ideal inductors and parasitic-laden inductors,
before and after optimization.
D. RF Circuit Optimization Results
Figs. 25 and 26 illustrate key final results for synthesis of the
distributed amplifier and power amplifier, respectively. The opti-
mized distributed amplifier has a much better frequency response.
Note that the optimizer has cleverly regained phase linearity by
eliminating internal parasitic mismatch effects. Loss compensa-
tion and improved phase linearity also improve the gain flatness
(Fig. 25).Gainroughnessin thepassbandbeforeoptimizationwas
dB; after optimization it is dB.
The desirability of parasitic-aware synthesis is also illustrated
in Fig. 26. With ideal parasitic-free inductors on all three stages,
the output power is 30 dBm and the drain efficiency is 58%
for an input power level of 0 dBm. Using parasitic-laden spiral
and bond wire inductors, but before optimization, the output
power drops to 27 dBm and the drain efficiency decreases to
only 30% with 0 dBm of input power. Both output power and
the drain efficiency are restored to nearly ideal specifications
after optimization.
VII. CONCLUSION
Methods for parasitic-aware RF circuit synthesis using PSO
and ASAT are presented and compared to simulated annealing.
PSO and ASAT provide greater computational efficiency and
robustness in the presence of on-chip and package parasitics. A
parasitic-aware synthesis system has been described that com-
prises three parts: an optimization core, an embedded RF cir-
cuit simulator, and a compact model generator. A four-stage dis-
tributed amplifier with 8-dB forward gain and 1-dB gain flatness
over a 8-GHz bandwidth, and a three-stage 900 MHz nonlinear
power amplifier with 30-dBm output power and 55% drain effi-
ciency have been synthesized in 0.35- m digital CMOS.
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Jinho Park was born in Seoul, Korea, in 1972. He
received the B.S. degree from Seoul National Uni-
versity, Seoul, Korea in 1996, the M.S. degree from
Oregon Graduate Institute, Portland, in 1999, and
the Ph.D. degree in electrical engineering from the
University of Washington, Seattle, in 2003. During
his Ph.D. program, he studied CMOS ultra-wideband
LNAs and RF synthesis techniques using particle
swarm optimization.
In 2003, he joined Marvell Semiconductors, Sun-
nyvale, CA, where he is currently engaged in design
of RF synthesizers and dc–dc converters. He is the coauthor of a book and a
book chapter in electronics. From 1999 to 2003, he served as President of Ko-
rean Graduate School Association of Electrical Engineering at University of
Washington and Director of Korean–American Scientists & Engineers Associ-
ation, Pacific Northwest Chapter.
Dr. Park received awards for outstanding analog design from the National
Science Foundation Center for the Design of Analog/Digital Integrated Circuits
(CDADIC) in 2002 and Analog Devices, Inc. in 2003.
1966 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 10, OCTOBER 2004

Kiyong Choi was born in Seoul, Korea. He received David J. Allstot (S’72–M’72–SM’83–F’92) re-
the B.S.E.E. and M.S.E.E. degrees in electrical engi- ceived the B.S., degree from the University of
neering from Arizona State University, Tempe, AZ. Portland, Portland, OR, the M.S. degree from
in 1998 and 1999, respectively, and the Ph.D. degree Oregon State University, Corvallis, and the Ph.D.
from University of Washington, Seattle, in 2003. degree from the University of California, Berkeley,
His interests include high-speed and high-power respectively.
analog integrated circuit design and computer-aided He has held several industrial and academic po-
design optimization. He is currently with Marvell sitions and has been the Boeing-Egtvedt Chair Pro-
Semiconductors, Sunnyvale, CA. fessor of Engineering at the University of Washington
since 1999. He is currently the Acting Chair of Elec-
trical Engineering. He has advised approximately 75
M.S. and Ph.D. graduates and published about 225 papers.
Dr. Allstot is the recipient of several outstanding teaching and advising
awards Awards include the 1978 IEEE W.R.G. Baker Prize Paper Award,
the 1995 IEEE Circuits and Systems (CAS) Society Darlington Best Paper
Award, the 1998 IEEE International Solid-State Circuits (SSC) Conference
Beatrice Winner Award, 1999 IEEE CAS Society Golden Jubilee Medal, and
the 2004 Technical Achievement Award of the IEEE CAS Society.He was an
Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II:
ANALOG AND DIGITAL SIGNAL PROCESSING from 1990 to 1993, and its Editor
from 1993 to 1995. He has served on the Technical Program Committee, IEEE
Custom Integrated Circuits Conference, from 1990 to 1993, on the Education
Award Committee, IEEE CAS Society, from 1990 to 1993, on the Board of
Governors, IEEE CAS Society, from 1992 to 1995, on the Technical Program
Committee, IEEE International Symposium on Low-Power Electronics and
Design from 1994 to 1997, on the Mac Van Valkenberg Award Committee,
IEEE CAS Society, from 1994 to 1996, and since 1994 is serving on the
Technical Program Committee, IEEE International SSC Conference. He has
been the 1995 Special Sessions Chair, IEEE International Symposium on CAS,
the Executive Committee Member and Short Course Chair, IEEE International
SSC Conference, from 1996 to 2000, the Co-Chair, IEEE SSC and Technology
Committee, from 1996 to 1998, Distinguished Lecturer, IEEE CAS Society,
from 2000 to 2001, and the Co-General Chair, IEEE International Symposium
on CAS in 2002. He is a Member of Eta Kappa Nu and Sigma Xi.