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Nmos Inverter: Resistive Load
Nmos Inverter: Resistive Load
Kn’=100μA/V2 • A resistor load to “pull”
VTN=0.6V the output up toward
the power supply VDD.
• Switch between two
states:
– Triode region:
,
Design: Chose R and – Cutoff region:
W/L of MS
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
NMOS resistive load inverter
Kn’=100μA/V2 MS cutoff
VTN=0.6V •
• is set by power supply
voltage VDD.
• should be less than ,
typically
2
• 2.5 V, 0.2 V
.
⇒
, • Load resistor:
Current determined by 28.8 kΩ
permissible power dissipation
of the NMOS,
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Noise Margin Analysis
Procedure:
• Find relation between
and
• Calculate (VIL , VOH) and
(VIH , VOL) by
• Calculate noise margin by
2
⇒
• Setting 1, we get
•
•
2
1
⇒
2
• Setting 1, we get
You can write in terms of
• 0.816
and solve for 1, but
that’s tedious! • 2
1
NM 0.816
• Noise margins increase as
increases for typical values of
greater than 2.
• For the previous design
A long chain of such inverters can • 0.756 V, 2.42 V
tolerate noise and process variations • 1.46 V, 0.51 V
around 0.25 V in the low‐input state and • NM 0.96 V, NM 0.25 V
0.96 V in the high state.
• Consider a 28.8 k Ω load:
2.88 10 Ω 10 cm
0.001 Ω cm
2880
Geometry of a simple 1
rectangular resistor • If width is 1 μm, length has to be
2.88 mm!
t: typically 1 μm
• Load resistor takes too much area
ρ: 10‐3 Ω cm on a chip
• Alternatives ??
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham