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Ucc 28056
Ucc 28056
UCC28056
SLUSD37C – OCTOBER 2017 – REVISED FEBRUARY 2018
40
2 Applications 35
Simplified Application
LBST DBST
VOUT
ROS1 Bus
CIn
CC0 RC0
UCC28056
CC01
VOSNS COMP
RZC1
COut
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28056
SLUSD37C – OCTOBER 2017 – REVISED FEBRUARY 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 controller Functional Modes .................................... 23
2 Applications ........................................................... 1 8 Application and Implementation ........................ 25
3 Description ............................................................. 1 8.1 Application Information............................................ 25
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 25
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 42
6 Specifications......................................................... 4 10 Layout................................................................... 42
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 42
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 42
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 45
6.4 Thermal Information .................................................. 4 11.1 Custom Design With WEBENCH® Tools ............. 45
6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 45
6.6 Typical Characteristics .............................................. 9 11.3 Community Resources.......................................... 45
7 Detailed Description ............................................ 12 11.4 Trademarks ........................................................... 45
7.1 Overview ................................................................. 12 11.5 Electrostatic Discharge Caution ............................ 45
7.2 Functional Block Diagram ....................................... 13 11.6 Glossary ................................................................ 45
7.3 Feature Description................................................. 14 12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DBV Package
6-Pin SOT-23
Top View
VOSNS 1 6 COMP
ZCD/CS 2 5 DRV
VCC 3 4 GND
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Output of the internal transconductance error amplifier and power demand input. To achieve
compensation of the voltage loop, connect a suitable RC network from this pin to GND. The error
amplifier output is internally limited to VCOClmp. An internal resistor, RCODisch, discharges the external
COMP 6 I/O
compensation network when the controller is in its Stopb state or when the Ovp2 comparator is tripped.
Switching stops, and the controller enters a low-power state (BstOffb), when the voltage on the COMP
pin drops below VBSTFall. Switching resumes when the COMP pin voltage exceeds VBSTRise.
GATE connection to drive the main power MOSFET. This output is internally limited to VDRHigh. This is
done to reduce power dissipation in the internal driver and allow controller operation from high VCC
DRV 5 I/O voltages. An external resistor connected from DRV to GND adjusts the delay between the Drain
waveform falling below VIn and the DRV rising edge, allowing the turn on transition to be aligned to the
valley minimum accurately over a wide range of idle ring oscillating frequency.
Controller Ground reference pin. Connect to the power stage at the lower terminal of the current sense
GND 4 G
resistor, RCS, only.
Positive supply voltage. Switching operation can start once VCC exceeds VCCStart. Switching operation
VCC 3 P
ceases if VCC drops below VCCStop for longer than TUVLOBlk.
This pin is fed by a potential divider connected across the Drain & Source pins of the power MOSFET
switch. While the DRV pin is high this pin monitors the voltage across the current sense resistor, RCS.
This pin implement over-current protection functions. While the DRV pin in low this pin monitors the Drain
ZCD/CS 2 I voltage waveform. Input voltage applied to the power stage can be obtained by filtering the Drain
waveform. Input voltage provides Line voltage feed - forward and Line Brown - In features. Drain voltage
waveform is also used to provide ZCD detection, valley synchronization and second level output over -
voltage protection features.
Voltage error amplifier inverting input. The error amplifier non - inverting input connects to internal
reference voltage VOSReg. Error amplifier gain increases with error magnitude to improve transient
VOSNS 1 I response without compromising Line current distortion. Output over-voltage protection is implemented on
this pin. Switching operation halts if the voltage on this pin exceeds VOvp1Rise and resumes when it drops
below VOvp1Fall.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC -0.5 36
Input voltage ZCD/CS -0.5 7 V
VOSNS -0.5 7
COMP -0.5 7
Output voltage V
DRV -0.3 20
Junction
temperature TJ -40 150
range
Storage
temperature Tstg -65 150 °C
range, Tstg
Soldering, 10 second 300
Lead temperature
Reflow 260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
11 9.2
9.15
10.9
9.1
10.8 9.05
10.7 9
8.95
VCCStart (V)
VCCStop (V)
10.6
8.9
10.5 8.85
8.8
10.4
8.75
10.3 8.7
10.2 8.65
8.6
10.1
8.55
10 8.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) d000
Temperature (°C) d000
1.92 0.03
1.9 0.029
1.88
0.028
1.86
0.027
1.84
0.026
1.82
1.8 0.025
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C) d000
d000
0.115 0.128
0.11 0.124
0.12
0.105
ICC_BSTOFF (mA)
ICC_FAULT (mA)
0.116
0.1
0.112
0.095
0.108
0.09
0.104
0.085 0.1
VCC = 12V
0.08 VCC = 25V 0.096
VCC = 33V
0.075 0.092
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) d000
Temperature (°C) d000
Figure 5. VCC Fault Current vs Temperature Figure 6. VCC Burst Off Current vs Temperature
VOSNSReg (V)
ICC_RUN (mA)
2.51
1.76
2.5
1.74
2.49
1.72 2.48
49.8
gM (µS)
0.3
49.5
0.296
49.2
0.292
48.9
48.6 0.288
48.3 0.284
48 0.28
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C) d001
d000
VBSTFall (V)
1.13 0.502
1.125 0.5
1.12 0.498
1.115 0.496
1.11 0.494
1.105 0.492
1.1 0.49
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) d001
Temperature (°C) d001
Figure 11. VOVP2 Threshold vs Temperature Figure 12. Burst Mode Falling Threshold vs Temperature
TZCDTo (µs)
0.627
2.6
0.625
2.5
0.623
2.4
0.621
0.619 2.3
0.617 2.2
0.615 2.1
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) d001
Temperature (°C) d001
Figure 13. Burst Mode Rising Threshold vs Temperature Figure 14. ZCD Timeout vs Temperature
2.81 2.73
2.8 2.72
2.79 2.71
2.78 2.7
2.77 2.69
VOSOovp1Rise (V)
VOSOovp1Fall (V)
2.68
2.76
2.67
2.75
2.66
2.74
2.65
2.73 2.64
2.72 2.63
2.71 2.62
2.7 2.61
2.69 2.6
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) d001
Temperature (°C) d001
Figure 15. VOSNS OVP1 Rising Threshold vs Temperature Figure 16. VOSNS OVP1 Falling Threshold vs Temperature
13.2 55
TDCM(GFF0)
13.1 50
TDCM(GFF1)
13 45 TDCM(GFF2)
12.9 TDCM(GFF3)
40 TDCM(GFF4)
12.8 TDCM(GFF5)
35
TONMAX0 (µs)
TDCM (µS)
12.7 TDCM(GFF6)
30 TDCM(GFF7)
12.6
25
12.5
20
12.4
12.3 15
12.2 10
12.1 5
12 0
-40 -20 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Temperature (°C) d001
COMP (V) d001
Figure 17. TON Max vs Temperature Figure 18. TDCM vs COMP Voltage
7 Detailed Description
7.1 Overview
The UCC28056 controller partners with the UCC256301 device to control a complete PFC and LLC isolated off-
Line power supply system delivering more than 300 W. The combined power supply is designed to meet tough
efficiency and standby power requirements without the need for an Auxiliary Flyback converter and with no need
to switch off the PFC under light load conditions. It allows designers to meet modern green power standards with
a simpler and cheaper power supply.
The controller contains a number of features designed to maximize operating efficiency across the entire range
of Line and Load. A versatile CrM/DCM control algorithm allows UCC28056 to operate in transition mode at full
power and then transition seamlessly into DCM at reduced load without compromising Line current harmonics or
power factor. The controller operates at maximum frequency (Transition mode) when delivering full load and then
automatically reduce switching frequency, moving to DCM operation, when delivering reduced load for maximum
efficiency.
Light-load efficiency and standby power are further enhanced by transitioning automatically to a burst mode of
operation when delivering less than 10% load. During the burst OFF periods, the controller powers down most of
its internal circuits to minimize controller power consumption.
The UCC28056 controller includes a comprehensive list of fault protection features such as cycle-by-cycle
current limit, over-current protection, dual independent output over-voltage protection, Line Brown-In, Over-
temperature protection and supply undervoltage lockout (UVLO).
Quantised 7-level line voltage feed-forward ensures that the loop gain is almost independent of line voltage, to
ease design of the output voltage control loop. A non-linear error amplifier greatly improves the response to large
steps in load without compromising steady state Line current harmonics.
VOSReg +
VOSNS 1
Error
VCOClmp 6 COMP
Amplifier
X SSCnt/4
+ Ovp1Fltb + RCODisch
BstRunb
VOSOvp1Rise, VOSOvp1Fall VBstRise,VBstFall Ovp2Fltb
R
+ D Q
Ovp2Fltb TONb >CLK
VOvp2Th
Stopb
VCCStop, VCCStart +
UVLOFltb
TUVLOBlk
TONb
VCC 3 Voltage VOSReg 4 GND
Ocp2Fltb Ovp1Fltb Fault and RDGRdb
Reference
TsdFltb ThrCycFlt Burst Pauseb
TLongFlt Faultb Mode
Ovp2Fltb State Stopb
VDRHigh UVLOFltb
VREG BstRunb Machine SSCnt
BoFltb
ILPkS( )
IL( , t)
IL( , t) ILPkS( )
ILAvS( ) ILAvS( )
TPER( ) TPER( )
Figure 19. PFC Inductor Current Waveform for CrM and DCM Operation
Consider a single switching cycle that occurs at angle (θ) during the Line Cycle. Assuming ideal CrM operation
the average inductor current (ILAvS(θ)) that flows during the switching cycle is given by:
ILPkS T TON T VIn T
ILAvS T VIn D u
2 2 u LBST RInEq (1)
A fixed circuit has constant inductance (LBST), so if the switch ON duration (TON(θ)) holds constant (TON) , across
the Line Cycle, then the average input current remains proportional to the input voltage. In other words, when
controlled in this way, the Boost converter behaves as a resistive load (RInEq) connected across the Line.
2 u LBST
RInEq
TON (2)
the next step is to consider DCM operation. Equation 3 describes the average inductor current that flows during
the switching cycle.
ILPkS T T T TDCH T T T u GONDCH T VIn T
ILAvS T u ON VIn T u ON
2 TPER T 2 u LBST RInEq (3)
To ensure average input current proportional to input voltage it is necessary for the on-time product TON(θ) x
δONDCH(θ) is kept constant across the Line Cycle. Equation 4 shows the equivalent input resistance.
2 u LBST
RInEq
TON u GONDCH (4)
The minimum effective input resistance (RInEqMin) is needed to draw maximum power (PInMax) from minimum Line
voltage (VInMinPkL):
VInMinPkL
PInMax
2 u RInEqMin (5)
1.3
1.2
Normalized Gain
1.1
0.9
0.8
0.7
0.6
0.5
80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280
Line Voltage (RMS) D001
IL(t)
VDS(t)
VIn
First Valley Ipk Err
0
DRV
TON TON
TZCDR TZCDR
Figure 21. Drain Voltage and Inductor Current Transitioning from DCM to CrM
VOSNS 1 + COMP
6
VOSReg VCOClmp
CCO
RCODisch
CCO1
Ovp2Fltb GND
R RCO
D Q
TONb >CLK
Stopb GND
GND
To improve the transient response to large perturbations, the error amplifier gain increases by a factor of six
times (6×) when the error amplifier input deviates more than ±3% from the nominal regulation voltage, VOSReg.
This increase allows faster charging and discharging of the compensation components to recover from step
changes in load current.
IL(t)
RZC1
RZC2
VZC(t)
RCS x IL(t)
GND GND
VOvp2Th
IL(t)
DRV
TOvp2Blk TOvp2En
Ovp2Fltb
Zcdb
Faultbn
Stopb RDGRdb
Runb BstOffb
SoftONb
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Ensure that POutMax can be delivered from the lowest Line voltage for GFF1. Use Equation 17 to calculate the
required Boost inductor value .
2
K ZC u VFF0Fall TONMAX1
LBST1 u 266 PH
110% u 2 u POutMax 2 (17)
Choose the lower of the two values calculated in Equation 16 and Equation 17 (LBST0 and LBST1). Using a smaller
inductance value compromises light load efficiency. A larger inductance value cannot deliver the required
maximum load power (POutMax) across the required range of Line voltage.
Choose a Boost inductor value of 250 µH. In order to deliver maximum load power the inductor must be able to
operate with a peak current that is greater than both ILPk0 and ILPk1
LBST 250 PH (18)
VInRMSMin u 2 u TONMAX0
ILPk0 6.15 A
LBST (19)
K ZC u VFF0Fall u TONMAX1
ILPk1 5.83 A
LBST (20)
ILPk ILPk0 6.15 A (21)
Use Equation 22 to calculate a current sense resistance that ensures the required peak inductor current (ILPk)
does not cause early termination of the TON period.
VZCOcp1Min
RCS 0.073 :
ILPk (22)
Achieve this amount of resistance by connecting three resistors in parallel.
1
RCS 0.073 :
2 1
0.15 : 3 : (23)
Use Equation 24 to calculate an inductance value that allows a saturation current above the maximum Ocp1
current limit value.
VZCOcp1Max
ILSat 7.5 A
RCS (24)
Maximum current in the power components flows while delivering maximum load when supplied from minimum
Line voltage. In this condition, the UCC28056 controller always operates in transition mode (CrM). shows the
inductor current waveforms for ideal CrM operation.
ILPkS( )
ILRMS( )
ILAvS( )
0 Œ
ILPkS( )
IL(t, )
ILRMS( )
ILAvS( )
0 TON TDCH( ) t
Equation 25 describes the he Boost inductor RMS current over a single switching cycle, at angle θ through the
Line half-cycle.
ILPkS T 2 u ILAvS T 2 V
ILRMS T u InPkL u sin T
3 3 3 RInEqMin (25)
Equation 26 describes the Boost inductor RMS current over a complete Line cycle.
S
1 2 VInRMS
³
2
ILRMS u ILRMS T dT u
S 3 RInEq
0 (26)
Maximum Boost inductor RMS current occurs at minimum Line voltage and maximum input power.
2 110% u POutMax
ILRMSMax u 2.5 A
3 VInRMSMin (27)
Based upon the inductor requirements, a custom magnetic can be designed, or a suitable catalogue controller
selected.
GMos T VInPkL G T
IMosRMS T ILPkS T u 2u u sin T u Mos
3 RInEq 3 (28)
Equation 29 describes the duty cycle of switch conduction for ideal transition mode (CrM) operation.
TON
GMos T
TON TDCH (T) (29)
The switch ON time is constant across the Line cycle but the OFF time varies according to the position in the
Line cycle. Volt-second balance across the Boost inductor, within each switching cycle, requires that.
TDCH T VIn T
TON VOut VIn T (30)
Equation 31 calculates the duty cycle of switch conduction.
V
GMos T 1 2 u InRMS u sin T
VOut (31)
Equation 32 describes the RMS switch current across a complete Line half-cycle.
S
1 VInRMS 4 32 u 2 u VInRMS
³
2
IMosRMS u IMosRMS T dT u
S RInEq 3 9 u S u VOut
0 (32)
Maximum RMS current in the switch occurs at maximum load and minimum Line.
110% u POutMax 4 32 u 2 u VInRMSMin
IMosRMSMax u 2.1 A
VInRMSMin 3 9 u S u VOut (33)
Use the following guidelines for MOSFET selection for the Boost switch.
• The voltage rating must be greater than the maximum output voltage. Under transient or Line surge testing
the output voltage may exceed the normal regulation level. For this design example, the MOSFET voltage
rating is 650 V supports a regulated output voltage of 390 V.
• Based upon an acceptable level of conduction loss in the MOSFET, the required on-resistance (rDS(on)) value
can be calculated from the maximum RMS current. For this example design an STF24N60DM2 MOSFET,
from STMicrolelectronics was selected with an on-resistance of 0.37 Ω, when TJ = 125°C which allows
maximum conduction power loss (less than 1.7 W) in the MOSFET.
• For best efficiency, use a MOSFET that incorporates a fast body diode. Operation using discontinuous
inductor current (DCM) from a low input voltage incurs additional switching power loss if a MOSFET with slow
body diode is used.
Electrolytic capacitors typically have a ripple current rating at twice Line frequency (120 Hz) and a different ripple
current rating at switching frequency (100 kHz). These ratings reflect the fact that the capacitor ESR is higher at
twice Line frequency and hence ripple current at this frequency leads to higher power loss than the same
amplitude of switching frequency ripple. Consider the equivalent high-frequency ripple current flowing in the
capacitor in order to select the correct capacitor.
ICEquRMSHF ICOutRMSLF2 u KHLF2 ICOutRMSHF2 (47)
The parameter KHLF is the ratio of high frequency to low frequency RMS ripple current rating for the particular
capacitor series to be used.
100kHz _ ripple _ current _ rating
KHLF
120Hz _ ripple _ current _ rating (48)
In this example design, for reasons of size and rating, two 68-µF, 450 V capacitors are selected from Rubycon
BXW series (450BXW68MEFC12.5X45), connected in parallel. In this way, both the capacitance value
requirement and ripple current rating are met with some additional margin.
COut 2 u 68 PF 136 PF (49)
2
2 § 1.525 · 2
ICEquRMSHF 0.3 A u¨ ¸ 1.15 A 1.37 A
© 0.610 ¹ (50)
In theory, a simple resistor divider can be used to attenuate the Drain voltage waveform fed into the ZCD/CS pin.
In practice, the parasitic capacitance associated with the PCB traces and the ZCD/CS pin filter the attenuated
signal and introduce phase shift. The resulting distortion and phase shift negatively impact the ability of the part
to synchronize to the zero inductor current transitions. The problem is compounded by the need to limit power
dissipation in the resistive divider, which dictates the use of high resistance values, and increased filtering of the
attenuated signal.
Add a capacitor divider in parallel with the resistor divider in order to use of high value resistors without
introducing filtering and associated phase shift. In this case, ensure that the reactive divider ratio is equal to the
resistor divider ratio.
R ZC2 X ZC2
R ZC1 R ZC2 X ZC1 X ZC2 (55)
Hence:
R ZC1 CZC2
R ZC2 CZC1 (56)
There are number of internal voltage thresholds driven by the attenuated Drain voltage signal supplied to the
ZCD/CS pin. These include Brown-Out (VZCBoRise), Line feed-forward (VFFxRise, VFFxFall) and second output over-
voltage (VOvp2Th). The same external divider ratio (KZC) drives all of these thresholds. Scope to vary the
attenuation ratio specified is limited because it impacts all of these thresholds in unison.
R ZC1
K ZC 1 401
R ZC2 (57)
K ZC
VInRMSBoRise VZCBoRise u 85.1 V
2 (58)
The controller infers Line voltage from the switching cycle average voltage on the Drain node. Neglecting any
resistive voltage drop in the Boost inductor this must be equal to the voltage supplied from the input rectifier,
provided the Boost inductor current returns to zero at the end of each cycle (TM/CrM/DCM). Voltage drops in the
input rectifier bridge and EMI filter stage cause an error between predicted and measured threshold values. An
internal peak detector determines the peak input voltage across a Line half-cycle. Equation 58 above converts
this peak value to an RMS quantity, but assumes an ideal sinusoidal Line supply
Equation 59 calculates the output voltage required to trigger the second output overvoltage comparator (Ovp2).
VOutOvp2 VOvp2Th u K ZC 451 V (59)
This parameter is observed via the Drain waveform, voltage drops in the Boost Diode and series NTC resistor,
causes the Ovp2 comparator to trip at a lower output voltage level.
Power dissipation in the Drain sensing resistor divider chain reaches its highest value during the Burst OFF
condition. During the Burst OFF condition, the Drain voltage approximates a DC voltage equal to the Line voltage
peak. This approximation assumes the time constant CIN × (RZC1+ RZC2) is long compared with a Line half-
period. Under no-load conditions, the Burst OFF duty cycle is high therefore maximum power dissipation in the
Drain sensing resistor divider chain, occurs at high Line and no-load, as described in Equation 60.
VInRMSMax 2 u 2
PZCMax
R ZC1 R ZC2 (60)
Equation 61 calculates the maximum value of RZC1 c, allowing a budget of 1% error due to input bias current
(IZCBias), on the lowest voltage threshold (VZCBoRise).
Err% u K ZC u VZCBoRise 1% u 2 u 85V
RZC1 d 12.0 M:
IZCBias 100nA (61)
The upper resistor in the divider chain (RZC1) must withstand the peak output voltage under a surge test. For a
rugged solution, the resistor(s) in this location must have a voltage rating above the avalanche rating of the
Boost MOSFET. This design uses a series chain of three 1206, SMT, 3.24 MΩ resistors for this location, which
yields DC voltage withstand capability above 600 V.
R ZC1 3 u 3.24 M: 9.72 M: (62)
R ZC1
R ZC2 24.3 k:
K ZC 1 (63)
Use Equation 60 to calculate the power dissipation in the ZCD/CS pin divider resistors.
VInRMSMax 2 u 2
PZCMax 14 mW
R ZC1 RZC2 (64)
Once arranged on the PCB, the resistor divider circuit has some parasitic capacitance across both the upper
(RZC1) and lower (RZC2) resistors. Experience suggests a parasitic capacitance (CZC1) of approximately 0.1 pF
across resistor RZC1, when it is made up of three 1206 SMT components, assuming a compact PCB layout. In
theory this parasitic capacitance could be used to form the entire value of CZC1 and an appropriate value of CZC2
added to achieve the ratio required by Equation 56. In practice most designers choose to add an explicit
capacitor in this location to improve tolerance to small changes in layout, such as may occur when connecting
oscilloscope probes. Ensure the time constant for the divider does not extend over many switching cycles. This
limitation ensures that Line surge or system ESD transient events may disturb the ZCD/CS pin DC level but does
not persist over an excessive number of switching cycles.
Select a single 10-pF, 1000-V, 0805 SMT capacitor with 5% tolerance.
CZC1 10 pF (65)
Use Equation 66 calculate the lower divider capacitor value.
CZC2 K ZC u CZC1 4.01nF (66)
In practice, once the final PCB layout is complete, adjust the lower capacitor value to account for parasitic
capacitances present on the PCB. Consider both the Drain and ZCD/CS pin waveforms and adjust the lower
capacitance value (CZC2) until the value allows the required ratio in signal amplitude. Use a low capacitance
probe for the ZCD/CS pin connection. Figure 28, Figure 29 and Figure 30 present the type of waveforms that
occur during this tuning process.
Figure 28. Amplitude VZC < (VDS/401). Reduce CZC2 Figure 29. Amplitude VZC = (VDS/401). Correct CZC2
Capacitance Capacitance
For this example design, the following values were selected for the RC filter to attenuate switching edge spikes.
R ZC3 3 k: (68)
CZC3 10pF (69)
ROS11 ROS12
ROS2 62.89 k:
K OS 1 (78)
These two divider resistor values can be implemented using easily obtainable values as follows:
ROS2 75 k: / / 390 k: 62.9 k: (79)
ROS12 36.5 k: / / 120 k: 28.0 k: (80)
Actual regulation set point is therefore:
ROS11 ROS12 ROS2
VOut Re g u VOSRe g 390 V
ROS2 (81)
Power dissipated in the VOSNS resistor divider is:
VOut Re g2
POSDiv 15.5 mW
ROS11 ROS12 ROS2 (82)
CCO CCO1
fP
2 u S u CCO u CCO1 u RCO (87)
VOSRe g 1
GCtrl0 u gM u
VOut Re g CCO CCO1 (88) (88)
Rearranging Equation 86, Equation 87 and Equation 88 yields:
f 1 § VOut Re g ·
CCO1 Z u u¨ u gM ¸
fP GCtrl0 ¨© VOSRe g ¸
¹ (89)
fP fZ
CCO u CCO1
fZ (90)
1 1
RCO u
2 u S u fZ CCO (91)
For maximum phase Boost at the gain cross-over frequency, compensator design proceeds by placing the pole
and zero an equal distance above and below the gain cross-over frequency (fB) on the Bode plot. Because the
frequency axis is logarithmic this yields the following pole (fP) and zero (fZ) frequencies:
f
fZ B
K (92)
fP fB u K (93)
Phase margin of the loop is equal to the phase boost provided by the type 2 compensator, because the
underlying integrator characteristics of the plant and compensator combine to provide 180° of phase lag. To
achieve the desired phase margin (ΦPM) at fB the separation between the pole and zero frequencies may be
found by substituting Equation 92 and Equation 93 into Equation 85, and solving for K in terms of the phase
boost angle.
§) S·
K tan ¨ PM
© 2 4 ¸¹ (94)
The next step is to select the desired phase margin. A typical phase margin range 45° to 75°. For this example
design a target phase margin of 65° is selected.
S
)PM 65q u
180q (95)
§) S·
K tan ¨ PM 4.51
© 2 4 ¸¹ (96)
The next step is to determine the loop gain cross-over frequency (fB). A faster loop, results in more twice Line
frequency ripple on the COMP pin voltage, leading to increased Line current distortion.
Begin by setting a target of 1% third harmonic distortion due to twice Line frequency COMP voltage ripple. To
achieve this target, the twice Line frequency COMP pin ripple must be less than 2% of the DC value during
steady-state full power operation. The design proceeds by selecting the loop gain cross-over frequency (fB) that
ensures twice Line frequency COMP pin ripple amplitude does not exceed 2% of its DC level.
Use Equation 97 to calculate twice Line frequency voltage ripple amplitude across the output capacitor.
POutMax 1
'VOut u 4.95 V
VOut Re g 2 u 2 u S u fLine u COut (97)
The output voltage ripple amplitude must be attenuated by the feedback network to meet our target of 2% ripple
amplitude on the COMP pin voltage.
VCOMax u 2%
GCtrl j2 u S u 2 u fLine
'VOut (98)
Equation 99 simplifies Equation 98.
0.0202
GCtrl0 u 4 u S u fLine 0.624 Hz
K2
where
• 2 x fLine >> fP
• 2 x fLine >> fZ (99)
Equation 100 describes unity at the gain cross-over frequency.
GPlant j2 u S u fB u GCtrl j2 u S u fB 1 (100)
Equation 100 can also be expressed as shown in Equation 101.
1
fB u GPlant0 u GCtrl0 u K 6.66 Hz
2uS (101)
Calculate the pole and zero frequencies using Equation 92 and Equation 93. Then determine the compensation
component values using Equation 89, Equation 90 and Equation 91.
f
fZ B 1.48 Hz
K (102)
fP fB u K 30.0 Hz (103)
fZ 1 VOSRe g
CCO1 u u u gM 25 nF
fP GCtrl0 VOut Re g (104)
fP fZ
CCO u CCO1 0.49 PF
fP (105)
1 1
RCO u 220 k:
2 u S u fZ CCO (106)
75 0
Gain_Plant Phase_Plant
Gain_Ctrl Phase_Ctrl
50 Gain_Loop -30 Phase_Loop
25 -60
Gain (dB)
Phase (°)
0 -90
-25 -120
-50 -150
-75 -180
0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000 0.1 0.2 0.5 1 2 3 4 5 7 10 2030 50 100 200 500 1000
Frequency (Hz) d001
Frequency (Hz) d002
Figure 31. Gain vs Frequency Figure 32. Phase vs Frequency
98% 1
97.5% 0.95
97%
0.9
96.5%
0.85
96%
95.5% 0.8
Efficiency (%)
Power Factor
95% 0.75
94.5% 0.7
94% 0.65
93.5% 0.6
93%
85Vac 0.55 85Vac
92.5%
115Vac 0.5 115Vac
92% 230Vac 230Vac
91.5% 265Vac 0.45 265Vac
91% 0.4
0 20 40 60 80 100 120 140 160 180 0 20 40 60 80 100 120 140 160 180
Output Power (W) d000
Output Power (W) d000
Figure 33. Efficiency vs Output Power Figure 34. Power Factor vs Output Power
20%
85Vac
115Vac
18% 230Vac
265Vac
16%
THD (%)
14%
12%
10%
8%
40 60 80 100 120 140 160 180
Output Power (W) d000
10 Layout
VEE RVCC
RCO
ROS2b
ROS2a
CCO1
COuta COutb
CCO
COS2
ROS12a ROS11c ROS11b ROS11a
CCC
COMP VOSNS
ROS12b
DRV ZCD/CS RZC3
U1
RZC1c
RZC2
GND VCC
CZC1
Q1
RDR1
CZC2b
CZC2a
CZC3
RDR
VOut+
RZC1b
DDR
RZC1a
RCSa
RDG
RCSb
JP4 JP5
RCSc VOut-
CIn
NTC
DBST
D1
LBST
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
STMicroelectronics is a registered trademark of STMicroelectronics.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 1-Feb-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
UCC28056DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 8056
& no Sb/Br)
UCC28056DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 8056
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Feb-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Jan-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Jan-2018
Pack Materials-Page 2
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