IEEE SIGNAL PROCESSING LETTERS, VOL. 20, NO.

5, MAY 2013 483

CORDIC Based Fast Radix-2 DCT Algorithm

Hai Huang and Liyi Xiao, Member, IEEE

Abstract—This letter proposes a novel coordinate rotation
digital computer (CORDIC)-based fast radix-2 algorithm for
computation of discrete cosine transformation (DCT). The
proposed algorithm has some distinguish advantages, such as
Cooley-Tukey fast Fourier transformation (FFT)-like regular
data flow, uniform post-scaling factor, in-place computation and
arithmetic-sequence rotation angles. Compared to existing DCT
algorithms, this proposed algorithm has lower computational com-
plexity. Furthermore, the proposed algorithm is highly scalable,
modular, regular, and suitable for pipelined VLSI implementation.
In addition, this letter also provides an easy way to implement the
reconfigurable or unified architecture for DCTs and inverse DCTs.
Index Terms—Coordinate rotation digital computer (CORDIC),
discrete cosine transformation (DCT), fast radix-2 algorithm.
I. INTRODUCTION
duced using their orthogonal properties, respectively. Similar to
the Cooley-Tukey fast Fourier transformation (FFT) algorithm,
the proposed algorithm can generate the next higher-order
DCT from two identical lower-order DCTs. Furthermore, it
has some distinguish advantages, such as FFT-like regular data
flow, uniform post-scaling factor, in-place computation and
arithmetic-sequence rotation angles. By using the unfolding
CORDIC technique, this algorithm can overcome the problem
of difficult to realize pipeline that in conventional CORDIC
algorithms. This results in a pipeline and high-speed VLSI
implementation. Compared to existing DCTs, the proposed
algorithm has low computational complexity, and is highly
scalable, modular, regular, and able to admit efficient pipelined
implementation. In addition, this letter also provides an easy
way to implement the reconfigurable or unified architecture for
DCTs and IDCTs using the orthogonal property.

S INCE the discrete cosine transformation (DCT) was pro-

posed by Ahmed [1], various fast algorithms have been re-
ported in the literature. Existing fast algorithms can be classi-
II. PROPOSED CORDIC BASED FAST DCT ALGORITHM
For an -point signal, , the DCT is defined as:
fied into nonradix and radix categories. Algorithms in the non-
radix category attempt to reduce computational complexity and
make computations more efficient, such as matrix factorization
[2]–[5], directly deduced from signal flow graphs [6]–[9], and (1)
coordinate rotation digital computer (CORDIC) -based fast al- where if , and otherwise.
gorithms [10]–[18]. Due to extensive design optimization for According to (1), neglecting the post-scaling factor without
cost reduction and performance enhancement, these DCT algo- loss of generality, the main operation of an -point DCT de-
rithms are often complicated and hardly scalable to more than noted as can be written as:
8-point DCTs. Compared to nonradix algorithms, radix algo-
rithms allow us to generate higher-order DCTs from lower-order (2)
DCTs [19]–[26]. Furthermore, radix algorithms generally have
a regular computational structure, which reduces implementa-
tion complexity. However, due to their recursive nature, radix A length- input sequence , with is power-of-two, can
algorithms are difficult to realize pipeline and are not suitable be decomposed into and , which are defined as:
for high-speed applications.
(3)
Among radix algorithms, the radix-2 algorithm is the most
popular because of its computational efficiency and structural (4)
simplicity. In this letter, we propose a CORDIC-based radix-2
fast DCT algorithm. Based on the proposed algorithm, signal where .
flows of DCTs and inverse DCTs (IDCTs) are developed and de- So the original signal, , can be obtained from and
as follows:

Manuscript received January 22, 2013; revised March 07, 2013; accepted (5)
March 10, 2013. Date of publication March 14, 2013; date of current version
March 22, 2013. The associate editor coordinating the review of this manuscript (6)
and approving it for publication was Prof. Lei Wang.
H. Huang is with the Microelectronics Center, Harbin Institute of Tech- Substituting (5) and (6) into (2), (2) can be rewritten as:
nology, Harbin, China and also with the School of Software, Harbin University
of Science and Technology, Harbin, China (e-mail: ic@hrbust.edu.cn;
husthh@yahoo.com.cn).
L. Xiao is with the Microelectronics Center, Harbin Institute of Technology,
Harbin, China (e-mail: xiaoly@hit.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. (7)
Digital Object Identifier 10.1109/LSP.2013.2252616

1070-9908/$31.00 © 2013 IEEE

484 IEEE SIGNAL PROCESSING LETTERS, VOL. 20, NO. 5, MAY 2013

Fig. 1. Signal flow of an -point fast discrete cosine transformation (DCT).

Fig. 2. Signal flow of a 2-point fast discrete cosine transformation (DCT).

Fig. 4. Signal flow of an 8-point fast discrete cosine transformation (DCT).

Let

(11)

Combing the constant values 2 and in recursively de-

composing stages with the post-scaling factor, the DCT can be
written as:

Fig. 3. Signal flow of a 4-point fast discrete cosine transformation (DCT).

where .
Since
(12)
According to (12), we can decompose the -point DCT into
two -point DCTs based on the CORDIC algorithm. For
power-of-two point DCT, the proposed algorithm computes the
(8) DCT by recursively decomposing it into 2-point DCT. Since
the basic operation of the algorithm is a 2-point DCT, similar
we get (9) and (10) to the radix-2 FFT, this algorithm is called fast radix-2 DCT. In
addition, the rotation angles of the CORDICs are arithmetic se-
quences with a common difference of . Another impor-
tant aspect is that all outputs, , , have
the uniform post-scaling factor. Furthermore, the post-scaling
factor can be merged into negative powers of two in the 2-D
DCT, which can be implemented with shifting operations.
(9)
III. DCT AND IDCT SIGNAL FLOW BASED ON
PROPOSED ALGORITHM
The general signal-flow graph for the proposed fast DCT al-
gorithm given in (12) is shown in Fig. 1, while the signal-flow
graphs of 2-point DCT, 4-point DCT, and 8-point DCT are re-
spectively represented in Figs. 2–4, where the angles in the cir-
(10) cles are used to represent CORDICs with this rotation angles.
In Fig. 1, there are two separate -point DCTs and one
where . CORDIC array. As mentioned above, the CORDIC array has
From (9) and (10), we find that each equation has two CORDICs with arithmetic-sequence rotation angles. The
-point with two different coefficients, and the four inputs are addressed in bit-reverse order and the outputs are ad-
coefficients just make one CORDIC. Hence, we combine the dressed in natural order. It also supports in-place computation
two equations to realize a CORDIC based fast DCT algorithm. like the FFT. Regular and pure feed-forward data paths of the
HUANG AND XIAO: CORDIC BASED FAST RADIX-2 DCT ALGORITHM
TABLE I
TRANSFER FUNCTIONS OF THE DCT AND IDCT
signal flow make them suitable for pipelined VLSI implemen-
tation. For special applications, a double-angle formula can be
used to reduce CORDIC types. Hence, the architecture based
on the signal flow is highly modular. Furthermore, the modified
unfolded CORDIC, which presented in our previous work [10],
can be used to speed up computations and overcome recursive
problems in conventional CORDICs.
Similarly, the fast algorithm for the -point IDCT can be
deduced like the fast DCT algorithm. Alternatively, it can be
obtained more easily using their orthogonal property. As is
known, the DCT and IDCT are orthogonal transformations,
and the signal flow of the -point IDCT can be easily obtained
by inverting the transfer function of each building block shown
in Table I and reversing the signal flow direction.
In Table I, the CORDICs in the DCT and IDCT have the same
rotation angle but opposite rotation directions. When changing
the CORDIC from a clockwise to an anticlockwise rotation with
the same angle, the only thing that is required is to change all
adders to subtractors, and subtractors to adders in the rotation
iteration stage. This results in an easy way to implement a re-
configurable or unified architecture for DCTs and IDCTs. Notice
that the proposed fast IDCT algorithm has the same arithmetic
complexity as does the DCT one.
IV. IMPLEMENTATION CONSIDERATION AND COMPARISONS
The -point proposed DCT algorithm needs two -point
DCTs, CORDICs, and additions. Therefore, the
number of CORDICs required by the proposed algorithm is
(13)
and the number of additions is
(14)
Fig. 5 compares the computational complexity of the pro-
posed algorithm and other algorithms [3], [7], [16], [20],
[22] and [23] in terms of the numbers of additions and the
numbers of the multipliers or CORDICs. In [3], Chen et al.
propose a fast recursive algorithm to factor any power-of-two
point DCT with requires additions and
multipliers. In [7], a fast multiplierless
approximation of the DCT with the lifting scheme is derived
from Chen’s algorithm. Hence, it has the same computational
complexity as the Chen’s algorithm. Furthermore, it presents
an efficient low-complexity fast VLSI implementation for the
DCT using only binary shift and addition operation. In [11],
the DCT is obtained through computing the DHT with requires
485
Fig. 5. Comparison of the computational complexity among the proposed and
other algorithms: (a) numbers of additions and (b) numbers of multiplications/
CORDICS.
additions and CORDICs. In [20], Hou propose
a fast recursive DCT algorithm by decomposing the transforms
into even-and odd-numbered frequency samples and implement
them with low hardware complexity by reusing the lower-order
DCT architecture. In [22], a fast parallel recursive radix-2 DCT
algorithm is proposed by decomposing the even-length DCT
into two balanced lower order DCTs. In [23], a fast algorithm
for composite-sequence-length DCT is proposed. For radix-2
DCT, the algorithms in [20], [22] and [23] have the same
computational complexity with additions,
and multipliers. The fast DCT algorithm based on
a shifted discrete Fourier transformation (SDFT) proposed by
Hsiao [16] only needs to compute partial results of the SDFT
to generate -point DCT, and is implemented with a linear
array with requires additions and CORDICs. It
reduces the computational complexity by reusing the two basic
processors. We propose a CORDIC-based fast radix-2 DCT al-
gorithm that requires additions and
CORDICs.
The following compares some of the major features of our
proposed CORDIC-based fast DCT algorithm.
Hardware complexity: The CORDIC-based algorithm is
highly suitable for VLSI implementation, since it is built
using shifters and adders only. Liang et al. [7] propose lifting
scheme-based fast multiplierless approximation of the DCT
using only binary shift and addition operations. This results
in a very low hardware complexity VLSI implementation. We
use the modified unfolded CORDIC to realize a low hardware
complexity VLSI implementation also using only binary shift
and addition operations. Moreover, the computational accuracy
can be selected based on the trade-off between the hardware
complexity and approximation error. In addition, since our
proposed algorithm has uniform post-scaling factor, it is also
suitable for scaled DCT implementation.
Fig. 6 shows the block diagram and the corresponding layout
view of the proposed 8-point DCT after placement and routing
based on SMIC 0.18 standard cell library. This design (ex-
cluding the I/O pads) has area of 627738 with power con-
sumption of 12.5 mW under operating frequency of 66.7 MHz.
Scalability: Many CORDIC-based algorithms are limit to
short-length DCT, such as the algorithms based on Loeffler’s
DCT [6], [17]. Our proposed algorithm provides much easier
486
Fig. 6. Block diagram and the corresponding layout view of the proposed
8-point DCT after P&R based on SMIC. 0 18 standard cell library.
and more regular way to realize the scalability, which can be
easily extended to compute long-length DCTs as long as the
transform length is power-of-two.
Modularity: For -point DCT, our proposed algorithm re-
quires CORDICs with only dif-
ferent CORDIC types. Furthermore, the rotation angles of the
CORDICs in our proposed algorithm are arithmetic-sequence,
the double-angle formula can be used to reduce the number of
the CORDIC types and make this algorithm highly modular.
Compared to the CORDIC-based architectures in [3], [16], our
architecture has better modularity.
Pipelinability: The architectures in [20], [22], [23] is recur-
sive in nature, thus making them difficult to realize pipeline. We
use the modified unfolding CORDIC to overcome this problem.
Moreover, the regular and purely feed forward data path makes
our proposed algorithm based architecture suitable for pipelined
VLSI implementation.
Reconfigurability: In [22], a method for mapping the type-IV
DCT to the type II-DCT is presented. However the method re-
quired additional arithmetic computation. We present an easy
way to implement a reconfigurable architecture for DCT and
IDCT with the same arithmetic complexity by taking the orthog-
onal property of them.
V. CONCLUSIONS
In this letter, we propose a novel CORDIC-based radix-2 fast
DCT algorithm. This algorithm can generate the next higher-
order DCT from two identical lower-order DCTs. Compared
to existing DCT algorithms, our proposed algorithm has sev-
eral distinct advantages, such as low computational complexity,
and being highly scalable, modular, regular, and able to admit
efficient pipelined implementation. Furthermore, the proposed
algorithm also provides an easy way to implement a reconfig-
urable or unified architecture for DCTs and IDCTs, which will
be researched in our future work. In addition, other types (types
I and IV) of CORDIC-based fast DCT algorithms will also be
examined in our future work.
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