A New 16-bit High Speed and Variable Stage

Carry Skip Adder

ABSTRACT

Adders are basic integral part of arithmetic circuits.

The adders have been realized with two styles: Fixed stage size and Variable

stage size. In this project, fixed stage and variable stage carry skip adder

configurations have been analyzed and then a new 16-bit high speed variable

stage carry skip adder is proposed by modifying the existing structure. The

proposed adder has seven stages where first and last stage are of 1 bit each, it

keeps increasing steadily till the middle stage which is the bulkiest and hence is

the nucleus stage. The delay and power consumption in the existing adder is

reduced by 61.75% and 8% respectively. The existing adder is implemented and

simulated using 90 nm CMOS technology in Cadence Virtuoso. The existing

adder in this work is suitable for high speed and low power VLSI based

arithmetic circuits and Aim is to enhance the VLSI parameters.

Keywords— carry skip; variable stage; fixed stage