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Design and FPGA Implementation of Sequential Digital FIR Filter using

Microprogrammed Controller

Conference Paper · October 2012

DOI: 10.1109/ICUMT.2012.6459641

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 First Workshop on Emerging Technologies and Devices in Signal Processing 2012
Design and FPGA Implementation of Sequential
Digital FIR Filter using Microprogrammed Controller
Syed Manzoor Qasim, Mohammed S. BenSaleh,
Mazen Bahaidarah, Hesham AlObaisi
King Abdulaziz City for Science and Technology
National Center for Electronics, Communications and
Photonics, Micro Sensors and Devices Division
Riyadh, Saudi Arabia
Abstract—Digital finite impulse response (FIR) filters play a
very important role in digital signal processing (DSP)
applications ranging from image and video processing to
wireless communication. Digital FIR filter is primarily
composed of multipliers, adders and delay elements. Several
techniques have been reported in the open literature to
implement digital FIR filters using Field Programmable Gate
Array (FPGA). This paper also presents an FPGA
implementation of FIR filter but using a novel
microprogrammed controller based design approach. The
proposed controller controls the sequence of operation of the
filter. To demonstrate the technique, design of a sequential 4-tap
digital FIR filter based on the microprogrammed controller is
presented. The proposed FIR filter is coded in VHDL using
modular design approach and implemented in Spartan-3E
FPGA. Performance evaluation is done based on the
implementation results obtained through Xilinx ISE tool.
I. INTRODUCTION
Digital finite impulse response (FIR) filters are the basic
building block of many digital signal processing (DSP)
systems. FIR Filters are used due to their stability and linear
phase properties. The main objectives of digital FIR filter are
to filter out undesirable parts of the signal, shape the spectrum
of signals in communication channels, signal detection or
analysis in radar applications. Adders, multipliers and delay
elements are the main components used in the implementation
of digital FIR filters. These components are arranged and
interconnected in different ways based on the architecture of
the FIR filter [1].
FIR filter performs a linear convolution on a window of N
data samples which can be mathematically expressed as
follows:
N −1
(1)
y ( n) = ∑ h ( k ) ⋅ x ( n − k )
k =0
A direct form implementation of an FIR filter can be
readily developed from the convolution sum as shown in fig.1.
978-1-4673-2015-3/12/$31.00 ©2012 IEEE
Tariq AlSharif, Mosab AlZahrani and Hani AlOnazi†
†
King Abdulaziz University/ King Saud University
Department of Electrical and Computer Engineering
†
Department of Electrical Engineering
College of Engineering
†
Jeddah/ Riyadh, Saudi Arabia
Figure 1. Direct form FIR filter architecture
Direct form FIR filters are also known as tapped delay line or
transversal filters. N-tap FIR filter consists of N delay
elements, N multipliers and N-1 adders or accumulators. The
impulse response of the FIR filter can be directly inferred
from the tap coefficients hk.
Several techniques for the implementation of digital FIR
using Field Programmable Gate Array (FPGA) have been
reported in the open literature [2-4]. The objective of this
paper is to demonstrate a novel microprogrammed controller
[5-7] based technique using an example of sequential 4-tap
digital FIR filter.
The rest of the paper is organized into four sections. The
datapath and microprogrammed controller architecture of the
proposed FIR filter are discussed in section II and III
respectively. FPGA implementation and simulation results are
presented in section IV. Finally, section V presents the
concluding remarks and some recommendations for future
work.
II. DATAPATH ARCHITECTURE
The proposed FIR filter architecture comprises of two
main building blocks which are datapath unit and control unit.
The block diagram of the 4-tap sequential FIR filter with the
integrated datapath and control unit is shown in fig. 2. Fig. 3
illustrates the datapath design of 4-tap FIR filter. The datapath
architecture consists of the following sub modules: four 8-bit
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 Figure 2. Block Diagram of FIR filter

Figure 4. Microprogrammed Controller

paper, we used microprogrammed controller to organize the

operation of FIR filter. The most important advantage of the
microprogrammed controller is its flexibility to add or modify
by simply changing the microprogram in the ROM based
control memory [9-10]. This makes the design of larger tap
FIR filter much easier.
As shown in fig. 4, microprogrammed controller consists
of two main parts. The first part is responsible for addressing
microinstructions kept in the control memory and the second
part is used to hold and generate microinstructions for the
datapath unit. The sequence of operations listed in table I is
followed to generate the output for the sequential FIR filter
architecture. The control signals generated by the
microprogrammed controller are listed in table I. The tap
coefficient registers (w0, w1, w2, w3) are loaded with data based
on load enable (LE) signal and the decoder output signals
(Ld1 and Ld0). After loading the input data in the first
register, the input data is multiplied and accumulated based on
the select signals (S1 and S0), product select (Ps) and load
accumulator (lacc) signals.

Figure 3. Datapath architecture

TABLE I. CONTROL SIGNALS

data registers, one 2-to-4 decoder, four 8-bit coefficient

registers (wo, w1, w2, w3), two 4:1 multiplexers which are used
as data selectors, single multiplier and 16-bit adder, one 2:1
multiplexer to control the flow of data from multiplier or
accumulator, 16-bit accumulator and 16-bit register to latch
the output [8]. Each sub modules are coded in VHDL and
finally integrated to obtain the complete datapath. The control
signals generated by the microprogrammed controller for this
datapath are fed to different sub modules for proper operation
of the FIR filter.

III. MICROPROGRAMMED CONTROLLER

There are several methods to design the controller, such as
hardwired controller and microprogrammed controller. In this

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 The filtered output data is available only after the output
latch (YL) signal is asserted high. The process is continued for
the remaining registers only after the data move (Dm) signal is
asserted high.

IV. FPGA IMPLEMENTATION AND SIMULATION RESULTS

The sequential FIR filter is designed and simulated using
VHDL. To implement the proposed architecture, Spartan-3E
(xc3s500e-4fg320) FPGA device is used. For the synthesis,
translation, mapping and place-and-route processes, Xilinx
ISE 12.2 webpack is used. Different reports are generated by
the tools. A summary of the results generated by the tool is
summarized in FPGA device utilization table II. The
maximum operating frequency of the designed FIR filter is Figure 6. Simulation snapshot of datapath unit for test case no. 1
119.775 MHz and consumes a small area out of the entire
FPGA real estate leaving plenty of room for implementing
other parallel processors [11]. The RTL view generated by the
tool is shown in fig. 5 which clearly shows the integration of
the datapath with the control unit.
TABLE II. FPGA DEVICE UTILIZATION

Figure 7. Simulation snapshot of datapath unit for test case no. 2

Figure 8. Simulation snapshot of datapath unit for test case no. 3

Three different test data are used for testing the designed
Figure 5. Integration of Datapath and Control unit (RTL View) circuit. The filter taps are chosen randomly with an objective
to provide something that is observable at the output. These
taps could be changed depending on the requirement of the
TABLE III. SIMULATION TEST CASES FOR 4-TAP FIR FILTER application [12]. The functionality of the FIR filter is verified
through simulation using Xilinx ISE built-in simulator.
Test No. Tap Coefficients (W) Input Data (X) Output Data (Y) Fig. 6, 7 and 8 shows the simulation waveform of the
datapath which verifies the three test cases listed in table III
1 {1, 2, 2, 1} {1, 2, 3, 3} {1, 4, 9, 14} respectively. Fig. 9 presents a snapshot of simulation results
for the microprogrammed controller. Finally, the datapath and
2 {3, 6, 6, 5} {2, 10, 3, 3} {6, 42, 81, 97} microprogrammed controller are integrated together to
demonstrate the simulation results of 4 tap FIR filter for each
3 {5, 4, 4, 1} {3, 9, 7, 7} {15, 57, 83, 102} test case. Fig. 10, 11 and 12 depicts the simulation waveforms
of the top level FIR filter for each case respectively.

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Figure 9. Simulation snapshot of microprogrammed controller
Figure 10. Simulation snapshot of FIR filter for test case no. 1
Figure 11. Simulation snapshot of FIR filter for test case no. 2
Figure 12. Simulation snapshot of FIR filter for test case no. 3
V. CONCLUSIONS
In this paper, we have presented a design of 4-tap FIR
filter using microprogrammed controller and its FPGA
implementation. The microprogrammed controller is used for
controlling the operation of digital FIR filter. A sequential
architecture utilizing single multiplier and adder along with
other building blocks are used to demonstrate the proposed
technique. Performance evaluation is done by synthesizing
and implementing the design in target Spartan-3E FPGA using
Xilinx ISE XST synthesis tool.
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The maximum operating frequency of the designed FIR
filter is 119.775 MHz which is much greater than the system
clock frequency (50 MHz) of the used board and consumes a
small area out of the entire FPGA real estate leaving plenty of
room for implementing other parallel processors. Since the
size of the FIR filter presented in the paper is small, the results
are not that significant, however, for larger tap FIR filters,
these results would be significant.
Future work would concentrate on developing an
equivalent parallel architecture of the FIR filter, extending the
tap size of the FIR filter architectures, applying optimization
techniques such as pipelining and comparing both the
architectures for speed, area and power.
ACKNOWLEDGMENT
The authors gratefully acknowledge the financial support
provided by the National Center for Electronics,
Communications and Photonics, King Abdulaziz City for
Science and Technology (KACST) under the Ejaz project
(IRU No. 31/513).
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