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Ec6311 - Analog and Digital Circuits
Ec6311 - Analog and Digital Circuits
C.VIJAY….. BE-ECE
BHARATHIDASAN ENGINEERING COLLEGE
NATTRAMPALLI-635 854
Name : --------------------------------------------
Reg.No : --------------------------------------------
C.VIJAY….. BE-ECE
BHARATHIDASAN ENGINEERING COLLEGE
NATTRAMPALLI-635 854
DEPARTMENT OF ECE
VISION
To emerge as a centre of excellence in providing quality education and produce
technically competent Electronics and Communication Engineers to meet the needs of
industry and Society.
MISSION
M1: To provide best facilities, infrastructure and environment to its students, researchers and
faculty members to meet the Challenges of Electronics and Communication
Engineering field.
M2: To provide quality education through effective teaching – learning process for their
future career, viz placement and higher education.
M3: To expose strong insight in the core domains with industry interaction.
M4: Prepare graduates adaptable to the changing requirements of the society through life
long learning.
PROGRAMME EDUCATIONAL OBJECTIVES
1. To prepare graduates to analyze, design and implement electronic circuits and systems
using the knowledge acquired from basic science and mathematics.
2. To train students with good scientific and engineering breadth so as to comprehend,
analyze, design and create novel products and solutions for real life problems.
3. To introduce the research world to the graduates so that they feel motivated for higher
studies and innovation not only in their own domain but multidisciplinary domain.
4. Prepare graduates to exhibit professionalism, ethical attitude, communication
skills, teamwork and leadership qualities in their profession and adapt to current
trends by engaging in lifelong learning.
5. To practice professionally in a collaborative, team oriented manner that embraces
the multicultural environment of today’s business world.
PROGRAMME OUTCOMES
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5. Modern tool usage: Able to create, select and apply appropriate techniques, resources,
and modern Engineering IT tools including prediction and modeling to complex Engineering
activities with an understanding of the limitations.
6. The Engineer and society: Able to apply reasoning informed by the contextual
knowledge To access societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional Engineering practice.
7. Environment and sustainability: Able to understand the impact of the professional
Engineering solutions in societal and environmental context, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Able to apply ethical principles and commit to professional ethics and
responsibilities and norms of the Engineering practice.
9. Individual and Team work: Able to function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Able to communicate effectively on complex Engineering activities
with the Engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
11. Project Management and Finance: Able to demonstrate knowledge and understanding
of the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life – long learning: Able to recognize the needs for, and have the preparation and
ability to engage in independent and life-long learning in the broadest contest of
technological.
1. Graduates should demonstrate an understanding of the basic concepts in the primary area
of Electronics and Communication Engineering, including: analysis of circuits containing
both active and passive components, electronic systems, control systems, electromagnetic
systems, digital systems, computer applications and communications.
2. Graduates should demonstrate the ability to utilize the mathematics and the fundamental
knowledge of Electronics and Communication Engineering to design complex systems
which may contain both software and hardware components to meet the desired needs.
3. The graduates should be capable of excelling in Electronics and Communication
Engineering industry/Academic/Software companies through professional careers.
COURSE OUTCOMES:
At the end of the course, the student should be able to:
CO1: Analyze various types of biasing and amplifier configuration.
CO2: Analyze the limitation in bandwidth of single stage and multi stage amplifier
CO3: Measure CMRR in differential amplifier
CO4: Simulate amplifiers using Spice
CO5: Use simplification techniques to design a combinational hardware circuit.
CO6: Design and Implement combinational and sequential circuits.
CO7: Design and Implement a simple digital system.
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EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY LTPC
0032
OBJECTIVES:
3. Darlington Amplifier
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
TOTAL: 45 PERIODS
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ANALOG CIRCUITS
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(A) ANALOG CIRCUITS LABORATORY
INDEX
Model Graph:
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Expt No: FIXED BIAS COMMON EMITTER AMPLIFIER Date:
Aim:
i.To design and construct BJT common emitter amplifier using fixed bias.
ii.To draw DC load line of the transistor and to find Q-point
iii.To measure the gain and to plot the frequency response.
iv. To measure the following parameters listed below
a) Bandwidth b) Gain bandwidth (GBW) product.
v. To justify CE amplifier as a low frequency amplifier.
Components & Equipment required:
2 Capacitor 0.1μFd 1
3 Transistor BC 107 1
4. Function Generator 1
5. CRO 1
Theory:
The common emitter amplifier is a Low noise amplifier and it is used in the low
frequency - voltage amplifier circuits. These amplifiers are used typically in the RF circuits.
The common emitter amplifier is an inverting amplifier which provides 180°phase shift. It
has medium input impedance and high output impedance. Since the current gain and power
gain of the common emitter amplifier is high, it is a most preferable amplifier configuration.
In fixed bias circuit, base current IB is fixed.The input of this amplifier is taken from the
base terminal, the output is collected from the collector terminal and the emitter terminal is
common for both the terminals.
DESIGN:
Step 1: To obtain hfe using multimeter
hfe= β (it will varies depend up on the material used by the transistor)
Step 2:
6
RC = 2 103 =3KΩ ≈3.3 KΩ
Choosing a standard value for RC as 3.3KΩ
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Step 3 :
To find RB using KVL at the input side
3
IB = I C = 2 10 = 8µ A
250
RB= (VCC – VBE) / IB = 12 0.7 = 1.4M Ω
6
8 10
Calculation of Bandwidth:
Bandwidth = fH - fL
Gain bandwidth product (GBW) = (Amid – 3dB) (fH - fL)
FREQUENCY RESPONSE:
VIN = 50mV at 1 KHz
Gain =
Frequency in Hertz Vo (volts) Gain = 20log(Vo/Vin) dB
Vo/Vin
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DC ANALYSIS:
To find Q point:
When Transistor operates at Cut-off region, IC = 0;
VCE = VCC =12V
Verification of KVL
To do DC ANALYSIS:
1. All AC voltage sources are removed from the circuit because DC analysis is
concerned only with DC sources.
2. All the capacitors in the circuit should be short circuited because Capacitors block
DC and Bypass AC.
3. Now let's do the calculations to find the VB, RB, ICQ, and VCEQ. From this, we
can find the Q-point of this transistor circuit.
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b. DC Load Line Curve
PROCEDURE:
1. Connect the circuit as based on the designed values.
2. Verify the KVL at both input and output side of the circuit
3. Set Vin =50mV at 1 KHz in the function generator. Keeping input voltage as constant,
vary the frequency in regular intervals.
4. As per the frequency variations, the changes in the output voltage has to be measured
using CRO.
5. Calculate the Gain in dB using the formula mentioned.
6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.
7. Calculate the Bandwidth and Gain bandwidth product from the frequency response
graph.
TO PLOT THE FREQUENCY RESPONSE:
1. The frequency response curve is plotted with Gain(dB) on a semi log scale
2. Line is drawn at 3 dB below with respect to the maximum of Amid & intersection
points are noted
3. The high frequency point is called the upper 3dB point (fH)
4. The lower frequency point is called the lower 3dB point (fL)
5. The difference between the upper 3dB point and the lower 3dB point in the
frequency scale gives the bandwidth of the amplifier
6. From the graph the bandwidth was calculated. (i.e.) Bandwidth = fH - fL
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EXERCISE:
1. Construct the CE amplifier using fixed bias with the following specification:
VCC= 10V, IC=1.2mA (find β value and substitute)
2. Construct the CE amplifier using fixed bias with the following specification:
VCC =16V, IC=2mA (find β value and substitute)
3. Construct the CE amplifier using fixed bias with the following specification:
VCC= 9V, IC=1.8mA, AV= 30 (find β value and substitute)
INFERENCE:
RESULT:
(i) Thus a BJT common emitter amplifier with fixed bias circuit is designed
and constructed.
(ii) The Q point of the transistor is found out and the DC load line is drawn.
(iii)The frequency response curve is plotted as per the readings taken.
(iv) The following parameters are measured and calculated
(i) Bandwidth (BW):
(ii)Gain Bandwidth (GBW):
(v) Thus, the CE Amplifier is justified as low frequency amplifier.
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Circuit Diagram:
Model Graph:
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Expt No: COMMON BASE AMPLIFIER Date:
Aim:
Apparatus Required:
3 Transistor BC 107A 1
5. CRO 30MHz 1
Theory:
It is also used as current buffer since it has a current gain of approximately unity.
When the circuit is preceded by a common emitter stage, it is called a cascode circuit. The
cascode circuit has the benefits of both configurations, such as high input impedance and
isolation
To Find RE
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9+ 10 - 4.5+ ICRC -9=0
RE =
ICRC =5.5
RE = IC= 1mA
RE = 10 KΩ
Rc
To find RC
-VEE +IERE-VCE+ICRC-VCC=0
DC ANALYSIS:
Verification of Kirchoff’s law at the input side
VEE+IERE-VBE = 0
Theoretical: -9 + 10 - 0.7 ≈ 0
Practical value:
Practical value:
= 0.9 mA ≈ 1 mA
αIE =IC =1 mA
VCBQ = VCC –ICRC
= 9 - 1 mA * 5.5 K
= 3.5 V
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Q point analysis: (Practical)
measure VCEQ at the collector terminal using multimeter.
Q-point: (ICQ =_____ ; VCEQ =______ )
FREQUENCY RESPONSE:
Gain =
Frequency Vo(volts) Gain = 20log(Vo/Vin)db
Vo/Vin
Calculation of Bandwidth:
f f
Bandwidth = H L
A 3dB f f
Gain bandwidth product (GBW) = ( mid )( H L )
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PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Set Vin =50mV in the function generator. Keeping input voltage constant, vary the
frequency in regular steps.
3. Note down the corresponding output voltage
4. Plot the graph: Gain in dB Vs Frequency in Hz
5. Calculate the Bandwidth from the frequency response graph
INFERENCE
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Exercise2: Construct the CB amplifier as mentioned below and compare the
performance with the CE amplifier
RESULT:
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Circuit Diagram:
Model Graph:
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Expt No: COMMON COLLECTOR AMPLIFIER WITH VOLTAGE Date:
Aim:
(i) To design and construct BJT Common Collector Amplifier using voltage divider bias
(ii) To draw DC load line of the transistor and to find Q-point
(iii)To plot the frequency response characteristics.
(iv) To measure the following parameters listed below:
a. Gain b. Gain bandwidth Product
(v) To justify CC amplifier as a unity gain amplifier.
Apparatus Required:
2. Capacitor 0.1μFd 2
3. Transistor BC 107 1
4. Function Generator - 1
5. CRO 1
Theory:
A common collector amplifier is a unity gain BJT amplifier used for impedance
matching and as a buffer amplifier. The circuit works well, when a positive half-cycle of the
input signal is applied to Base emitter junction of transistor the forward bias voltage V be is
increased, which in turn increases the base current Ib of transistor. Since emitter current Ie is
directly proportional to Ib the voltage drop across the Emitter Ve= IeRe is increased, hence,
output voltage Vo is increased, thus, we get positive half-cycle of the output. It means that a
positive-going input signal results in a positive going output signal and, consequently, the
input and output signals are in phase with each other. Similarly the negative half cycle of
input signal produces negative going output signal.
At the result, the output voltage is nearly equal to the input voltage. Examined from
the perspective of output voltage change for a given amount of input voltage change, this
amplifier has a voltage gain of almost unity (1), or 0 dB. Common Collector is designed with
output at Emitter terminal. Output follows input, hence called Emitter Follower.
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Design:
To find RE :
6v
Now RE = VRE / IE= = 6kΩ
1*103
Design of R1 & R2
Drop across RE is 6V
Drop across VBE is 0.6V
Drop across the resistance R2 is VR2 = VBE + VRE =6.6V
Assume R1 & R2 of equal values say 10KΩ
FREQUENCY RESPONSE:
Vin = 0.1V at 1 KHz
Gain =
Frequency Vo(volts) Gain = 20log(Vo/Vin)db
Vo/Vin
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DC Analysis:
find the quiescent or just simply the q-point of a Transistor Circuit.
Procedure:
1. All AC voltage sources are taken out of the circuit because they're AC
sources. DC analysis is concerned only with DC sources.
2. All the capacitors in the circuit should be removed since Capacitors block DC.
(i.e) everything before and after capacitors are removed.
3. Now let's do the calculations to find the Vbb, Rb, IEQ, and VCEQ. From this,
we can find the q-point of this transistor circuit.
R1
VBB = VCC
( R1 R2)
10K
= 12 = 6V
(10 K 10 K)
V V 6 0.7
BB
R
BE
IEQ = B R = 5K 5.6K = 0.9mA
ß 1
100
E
V V
CEQ CC I R
EQ E
= 12 - (0.9mA* 5.6k)
= 6.96V
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Q point analysis: (Practical)
measure VCEQ at the collector terminal using
multimeter. Q-point: (VCEQ =______ ,IEQ =_____ ;)
Model Graph (DC Load line):
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Procedure:
1. Connect the circuit as per the circuit diagram with designed values.
2. Set Vin =0.1V in the function generator. Keeping input voltage constant, vary the
frequency in regular steps. As per the frequency variations, the changes in the output
voltage has been measured using CRO.
INFERENCE:
Exercise:
1. Construct the CC amplifier using self bias with the following specification
Vcc = 15v,Ic=2mA, β = (find β value and substitute)
2. Construct the CC amplifier using self bias with the following specification
Vcc = 12v,IE=1mA, β = (find β value and substitute)
RESULT:
(i) Thus a BJT Common Collector Amplifier using voltage divider bias (self bias)
is designed and constructed.
(ii) The Q point of the transistor is found out and the DC load line is drawn.
(iii)The frequency response characteristics curve is plotted as per the readings taken.
(iv) The following parameters are measured and calculated
(i) Gain
(ii) Gain bandwidth Product
(v) CC amplifier is justified as a unity gain amplifier.
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Circuit Diagram:
Model Graph:
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Expt No: COMMON SOURCE AMPLIFIER Date:
Aim:
Apparatus Required:
Transistor J310 1
1.
5. CRO 30 MHz 1
6. Bread Board 1
7. Capacitor 0.1µF 2
Theory:
These devices have the advantage over bipolar transistors of having extremely high
input impedance along with a low noise output making them ideal for use in amplifier circuits
that have very small input signals. Self bias is the most common type of JFET bias.
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Frequency Response:
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)
Calculation:
Bandwidth = f2-f1
A 3dB
Gain bandwidth product (GBW) = ( mid ) (f2-f1 )
A 3
=( mid dB) (BW)
PROCEDURE:
1. Connect the circuit as based on the designed values.
2. Verify the KVL at both input and output side of the circuit
3. Set Vin =50mV at 1 KHz in the function generator. Keeping input voltage as constant,
vary the frequency in regular intervals.
4. As per the frequency variations, the changes in the output voltage has to be measured
using CRO.
5. Calculate the Gain in dB using the formula mentioned.
6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.
7. Calculate the Bandwidth and Gain bandwidth product from the frequency response
graph
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DC ANALYSIS
V 2
I
ID DSS
1
GS
VP
Applying KVL at the input side,
6
IG(10 ) + VGS + IS(2.2 K) = 0
Since, the gate current is zero, so IS = ID and
VGS = −2200 ID.
Substitute VGS in ID
2
V
VGS = (2 10 )(1 10
3 3
) 1 GS
1
Rearranging this expression for VGS ,
2
we get, 2.2 V GS + 5.4VGS + 2.2 = 0 and
VGS = (−0.515 V, - 1.93 V)
VGS must be negative but less negative than the pinch-off voltage of the n-channel
JFET, so, the − 0.50V result must be the correct choice.
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The corresponding value of ID becomes
2
3 0.50V
I D 10 A 1
1V
VDS can be found by applying KVL at the output
VDD- IDRD-VDS-ISRS = 0
-6 3) -6 3)
20 – (250 x 10 x 33 x10 – VDS – (250 x 10 x 2.2 x10 =0
VDS = 11.2V
IS = ID = 250 μA
To verify dc condition
1. VGS : = ____________
2. VDS = ____________
3 ID =
Q-point:
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INFERENCE:
Result:
(i) Thus , the CS amplifier is constructed.
(ii) The Q point of the transistor is found out and the DC load line is drawn.
(iii) The Frequency Response of the amplifier is plotted.
(iv) The following parameters are measured and calculated
a. Gain :
b. Gain bandwidth Product:
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Circuit Diagram:
Model Graph:
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Expt No: DARLINGTON AMPLIFIER USING BJT Date:
Aim:
1. Transistor BC 107 1
3. Capacitor 47µF 2, 1
5. CRO 30MHz 1
7. Bread Board 1
Theory:
Using the NPN Darlington pair as the example, the collectors of two transistors
are connected together, and the emitter of Q1 drives the base of Q2. This configuration
achieves β multiplication because for a base current IB, the collector current is β*IB where
the current gain is greater than one, or unity. Because of direct coupling dc output current of
the first stage is (1+hfe ) Ib1..Due to very large amplification factor even two stages
Darlington connection has large output current and output stage may have to be a power
stage. As the power amplifiers are not uses in this amplifier circuits, it is not possible to use
more than two transistors in the Darlington connection. In Darlington transistor connection,
the second transistor amplifies the leakage current of the first transistor and overall leakage
current may be high, which does not desire.
IC = IC1 + IC2
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DC - Analysis:
β1 and β2 are the gains of the
individual transistors.
Since β= β1=β2; [βD =β1β2]
Collector current, IC
IC = βD IB
= βD {(VB-VBE ) / (RB +
βDRE)} =922mA
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Q point analysis: (Practical)
Measure VCEQ at the collector terminal using multimeter.
Measure ICQ at the collector terminal using ammeter.
Q-point: (VCEQ =______ ,IEQ =_____ ;)
Frequency Response :
Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
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Procedure:
INFERENCE
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Result:
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Circuit Diagram:
Common Mode
Differential Mode:
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Expt No: DIFFERENTIAL AMPLIFIER USING BJT Date:
Aim:
2. Transistor BC107 2
3. Function Generator - 1
4. Multimeter - 1
Theory:
The differential amplifier amplifies the difference between two input voltage signals.
Hence it is also called difference Amplifier. In an ideal differential amplifier, the output
voltage Vo is proportional to the difference between the two input signals. Hence we can
write, VO = Ad (V1-V2) Where Ad refers to differential gain, which amplifies the difference
between two input signals.
Vo = Ad vd ;
Ad=Vo/Vd
Generally the differential gain is expressed in its decibel (dB) value as, Ad=20 log10
(Ad) in dB. An average level of the two input signals is called common mode signal denoted
as Vc, Vc= (V1+V2)/2 The gain with which it amplifies the common mode signal to produce
the output is called common mode gain of the differential amplifier denoted as Ac.
V0=AcVc ;
Ac=VO/Vc
Vo =AdVd+AcVc
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Tabulation:
Common Mode:
Differential Mode:
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Practical calculation:
DESIGN:
hie =1.2k
Ic 1 *10 3
I
B 250 4A
= =
Choose RB as 57k
hfeRc
Ad
Rs hie
hfeRc
AC
Rs hie 2RE (1 hfe)
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PROCEDURE:
1. Connect the circuit as based on the designed values (differential mode, common
mode).
2. Verify the KVL at both input and output side of the circuit.
3. Set VIN =50mV at 1 KHz in the function generator. Keeping input voltage as
constant, for both transistors.(at common mode)
4. To find output voltages V01 and V02 and also find output voltage V0.
5. Calculate the common Gain AC in dB using the formula mentioned.
6. Set V1 =50mV at 1 KHz in the function generator input for transistor Q1 and Set
V2 =100mV at 1 KHz in the function generator input for transistor Q2 (at
Differential mode)
7. To find output voltages V01 and V02 and also find output voltage V0.
8. Calculate the Differential mode Gain Ad in dB using the formula mentioned.
9. Calculate the Common Mode Rejection Ratio (CMRR) = 20 log (Ad/Ac) in dB.
INFERENCE:
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Result:
(i) Thus, the Differential amplifier is designed and constructed using BJT.
(ii) Common mode gain and Differential mode gain are calculated.
(iii)The CMRR of Differential Amplifier is dB
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Circuit Diagram:
Model Graph:
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Expt No: CASCODE AMPLIFIER Date:
Aim:
Apparatus Required:
S.No. Name Range Quantity
1. Transistor BC107 2
5. CRO 30 MHz 1
6. Bread Board 1
Theory:
Cascode amplifier is a special case of cascade amplifier. Cascode amplifier is a two
stage amplifier, which comprises a CE amplifier driving a CB amplifier. The CE amplifier
has with significant current and voltage gain, moderate input and output impedance. The CE
is used most often for voltage amplification .It can provide a large output voltage swing.
In multistage system current stage output becomes the input of the next stage of the
system .The emitter resistor amplifier is similar to the CE amplifier but has lower voltage
gain and higher input impedance .The CB amplifier has low input impedance and relatively
high output impedance.
In Cascode Amplifier Transistor Q1forms the CE amplifier and CB amplifier utilizes
Q2 .This configuration has the advantage of increased output resistance and wider frequency
response while maintaining high voltage gain. The low input impedance of the CB circuit
forms the load resistance for the CE stage .The collector current of Q2 is almost equal to the
collector current of Q1, which in turn drives the load.
Design:
Rc = RL / 10 = 90kΏ / 10 = 9KΏ
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(ii) To calculate RE:
= 20V – 3V – 3V- 5V
VRC = 9V
RE = VE / IE ; Where IE = Ic = 1.1mA
RE = 4.5K
a. R3 = 10 RE = 47KΩ
= 5V + 3V + 0.7V
= 8.7V
R2 = 24.8KΩ
= 93.4 KΏ
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Determination of Capacitor Values:
To Find C1 :
= 57.9μF
To Find C2 :
To Find C3 :
C3 = * 1 / 2πf1hib ]
= 256μF
To Find C4 :
= 0.64 μF
DC Analysis
Here, in this circuit the Q point should be found out for each stage of amplifier.
Firstly, CE amplifier’s Q point is calculated and then for CB amplifier as found out in
the previous experiments.
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.Frequency Response:
Keep the input voltage constant, Vin =……..(volts)
Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
Calculation:
Bandwidth = f2-f1
A 3dB
Gain bandwidth product (GBW) = ( mid ) (f2-f1 )
A 3
=( mid dB) (BW)
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PROCEDURE:
1. Connect the circuit as based on the designed values.
2. Verify the KVL at both input and output side of the circuit
3. Set Vin =20mV at 1 KHz in the function generator. Keeping input voltage as constant,
vary the frequency in regular intervals.
4. As per the frequency variations, the changes in the output voltage has to be measured
using CRO.
5. Calculate the Gain in dB using the formula mentioned.
6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.
7. Calculate the Bandwidth and Gain bandwidth product from the frequency response
graph
Exercise:
INFERENCE
Result:
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Circuit Diagram:
Model Graph:
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Expt No: CASCADE AMPLIFIER Date:
Aim:
Apparatus Required:
1. Transistor BC107 2
3.3kΩ,56kΩ,600Ω,
2. Resistor 1,1,1,1,2,2,2
560Ω,33kΩ,5.6kΩ,2.2kΩ
5. CRO 30 MHz 1
6. Bread Board 1
Theory:
A single stage of amplification is not enough for a particular application. The overall
gain can be increased by using more than one stage, so when two amplifiers are connected in
such a way that the output signal of the first serves as the input signal to the second, the
amplifiers are said to be connected in cascade. The most common cascade arrangement is the
common-emitter RC coupled cascade amplifier. Common-emitter amplifier exhibit high
voltage, high current, and high power gains, so they are very familiar than other
configurations.
Amplifier with two or more stages is also known as multistage amplifier. Multistage
amplifiers can be used either to increase the overall small signal voltage gain, or to provide
an overall voltage gain greater than 1, with a very low output resistance. The bandwidth of
multistage amplifier is always less than that of the bandwidth of a single stage amplifier.
Non linear distortion is more in multistage amplifier than single stage amplifier. In circuit,
Capacitors C1and C3 couples the signal into Q1and Q2 respectively. C5 is used for coupling
the signal from Q2 to its load
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Design:
Given Data:
Vcc = 10v, Ic = 2mA , , (Find the value using multimeter)
Step 1:
Vcc
Vc= 2 = 10 / 2 =5V
Vc -3
R3 = Ic = 5 / (2*10 ) = 2.5K
Step 2:
Ie ≈ Ic
For temperature stability,Ve 1V
Ve -3
R4 Ie 1 / (2*10 ) = 500 ohms
Step 3:
Vbe = Vb – Ve
For silicon transistor Vbe = 0.7 V
Vbe + Ve = 0.7 + 1 = 1.7V
Step 4:
VCC R2
VR2 = Vb = R2 R1
Let R2= 5K,
R1= 24K
Note:
Here, in cascade amplifier,2 stages of CE amplifier is combined to form
Cascade amplifier. So, R1 = R5 , R2 = R6, R3 = R7, R4 = R8
Frequency Response:
Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)
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Calculation:
Bandwidth = f2-f1
A 3dB
Gain bandwidth product (GBW) = ( mid ) (f2-f1 )
A 3
=( mid dB) (BW)
DC Analysis
Here, in this circuit the Q point should be found out for each stage of amplifier.
Each CE amplifier’s Q point is calculated as per the procedure given in the previous
experiment.
Procedure:
INFERENCE:
Exercise:
1. Design a three stage amplifier using BJT transistor to achieve a gain of 150 and
input resistance of 100k and output resistance of 50 ohms.
Result:
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COMMON EMITTER AMPLIFIER
Circuit Diagram:
Model Graph:
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Expt.No: SPICE SIMULATION OF COMMON EMITTER AND Date:
Aim:
Software Required:
Procedure:
TYPE PROGRAM
FILE SAVE AS .CIR then change file type as circuit files then CLICK OK
RUN PROGRAM
TRACE ADD TRACE select your input node and output node [Eg:
V(1),V(2),V(3),… etc] CLICK OK
Note: To view input and output graph separately split the window using the following
procedure
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Common Emitter amplifier Program:
.LIB NOM.LIB
.OPTIONS NOPAGE NOECHO
.TRAN/OP 50US 2MS
.AC DEC 10 1HZ 80MEGHZ
.OP
VIN 1 0 AC 10MV SIN (0 10MV 1KHZ)
VCC 7 0 DC 15V
RS 1 2 500
R1 7 3 47K
R2 3 0 5K
RC 7 4 10K
RE 5 0 2K
RL 6 0 20K
C1 2 3 10UF
C2 4 6 10UF
CE 5 0 10UF
Q1 4 3 5 0 QM
.MODEL QM NPN (IS=2E-16 BF=100 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS
+ CJE=0.4PF VJE=0.8 ME=0.4 CJC=0.5PF VJC=0.8 CCS=1PF VA=100)
.PLOT TRAN V(4) V(6) V(1)
.PLOT AC VM(6) VP(6)
.PROBE
.END
Common Source Amplifier
Circuit Diagram:
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PROGRAM:
.LIB NOM.LIB
.OPTION NOPAGE NOECHO
VIN 1 0 AC 0.5V SIN (0 0.5V 1KHZ)
VDD 7 0 DC 20V
R1 1 2 50
RG 3 0 0.5MEG
RD 7 4 3.5K
RS 5 0 1.5K
RL 6 0 20K
C1 2 3 1UF
C2 4 6 1UF
CS 5 0 10UF
J1 4 3 5 JMOD
.MODEL JMOD NJF (IS=100E-14 RD=10 RS=10 BETA=1E-3 CGD=5PF
CGS=1PF VTO=-5).
.AC DEC 10 1HZ 80MEGHZ
.TRAN/OP 10US 1MS
.OP
.PLOT TRAN V(6) V(1)
.PROBE
.END
Model Graph:
Result:
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CIRCUIT DIAGRAM:
Vcc=+12V
+
A (0-10)mA
R1=30K RC=1K
C1=22uF
B
BC548
E
+ +
C2=100uF
Vin=50mV R2=4.7K
Freq=1kHZ FG CRO
- RE=470Ω - Vout
GND
Model Graph:
Observation:
VO = Idc =
Design
Input Power:
Pin =Vdc* Idc
Output Power:
2
vo
Pout = RL
Pou t
% Efficiency: % *100
P
in
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Expt No: CLASS-A POWER AMPLIFIER Date:
Aim:
(i) To construct the Class - A Power amplifier.
(ii) To calculate the efficiency of a Class A amplifier.
Apparatus Required:
Theory:
The power amplifier is said to be Class A amplifier if the Q point and the input signal
are selected such that the output signal is obtained for a full input signal cycle.
For all values of input signal, the transistor remains in the active region and never
enters into cut-off or saturation region. When an AC signal is applied, the collector voltage
varies sinusoidally hence the collector current also varies sinusoidally. The collector current
0
flows for 360 (full cycle) of the input signal i.e. the angle of the collector current flow is
0
360 .
Procedure:
1. Give the connections as per the circuit diagram.
2. Set input as 50mv.
3. Note down Idc, Vo in mid frequency region.
4. Calculate η using formulas.
RESULT:
Thus class A power amplifier is constructed
Efficiency =
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CIRCUIT DIAGRAM:
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Expt No:CLASS B COMPLEMENTARY SYMMETRY Date:
POWER AMPLIFIER
Aim:
(i) To analyze a Class B complementary symmetry power amplifier.
(ii) To observe the waveforms with and without cross-over distortion
(iii)To compute maximum output power and efficiency.
Apparatus Required:
Theory:
For class B operation, the quiescent point is located on the X-axis itself. Due to this
collector current flows only for a half cycle of the input signal. Hence the output signal is
distorted. To get a full cycle across the load, a pair of transistors is used in class B operation.
The two transistors conduct in alternate half cycles of the input signal and a full cycle across
the load is obtained. The two transistors are identical in characteristics and called matched
transistors.
Depending upon the types of the two transistors whether p-n-p or n-p-n, the two
circuit configurations of class B amplifier are possible .These are,
1. When both the transistors are of same type i.e. either n-p-n or p-n-p then the circuit
is called push pull class B A.F. power amplifier circuit.
2. When the two transistors form a complementary pair i.e. one n-p-n and other p-n-p
then the circuit is called complementary symmetry class B A.F.power amplifier
circuit.
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Model Graph:
(i)With Cross Over Distortion
V0
t(ms)
V0(V)
t(ms)
Formula Used:
V *I
Input Power (W ) =vo dc in dc
2
Output power (W o ) =
R
L
Wo
Efficiency =
W
in
Efficiency Calculation:
i) Pdc = 2 Vcc Im
(Vcc = Vm)
2Vm
= Vcc RL
2
1 Vcc
2
2
2
R
78.5%
Vcc (Pac) L
ii) Pdc = iii)= max
2 Vcc
p 2
RL dc 4
R
L
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Procedure:
Result:
(i) Thus the complementary symmetry class –B Power amplifier was constructed
(ii) Maximum output power and efficiency are calculated and compared with the
theoretical values.
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Circuit Diagram:
A 1N4001 K
9
R=1K
AC I/P 230V
Vo
CRO 0
GND
R=1K C=100uF
AC I/P 230V
CRO
Vo 0
GND
A 1N4001 K
9
R=1K
Z 9.1 - -
0
DRB
GND
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Expt No: POWER SUPPLY CIRCUIT-HALF WAVE RECTIFIER WITH Date:
Aim:
1. To Calculate DC voltage under load and ripple factor and compare with calculated
values.
Apparatus Required:
2. Resistor 1KΩ 1
3. Capacitor 100µfd 1
4. Transformer 9-0-9V 1
5. CRO 1
6. DRB 1
7. Voltmeter (0 – 30)V 1
8. Ammeter (0 – 10) mA 1
9. Breadboard - 1
Theory:
It converts an ac voltage into a pulsating dc voltage using only one half of the applied
ac voltage. The rectifying diode conducts during one half of the ac cycle only. During the
positive half cycle of the input signal, the anode of the diode becomes positive with respect to
the cathode and hence the diode conducts
During the negative half cycle of the input signal, of the anode of the diode becomes
negative with respect to the cathode and hence the diode does not conduct. Output voltage is
seen for positive Half of input only. Output of Rectifier is pulsating DC (With ripples) and
remove them, C Filter is connected parallel with load which Bypasses AC components to
Ground
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Tabular Column:
Without Filter:
2
vm vm (vrms )
Vin (dc) vm (v) (v) Ripple Factor= 1
v v
(volts) rms
=2 dc
= (vdc )
2
v vr vm v1
1 = T1= T2=
With Filter:
v v v Ripple Factor
v vr r
Vin (dc) m (volts) r (volts) rms v dc v m
=v /v
3 2 rms dc
Current (mA)
Voltage (Volts)
1 1
2 3 f * c * RL 2 3 * 50 *100 f *1k = 0.05
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PROCEDURE:
RESULT:
Thus the Half wave Rectifier is designed with and without Capacitor filter and
the corresponding dc voltage and the ripple factors are measured and verified
Ripple Factor Theoretical values Practical values
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Circuit Diagram:
Full wave rectifier without filter fig (i)
A K
1N4001
A K
1N4001
GND
A K
1N4001
C=100uF
AC I/P 230V R=1K
CRO
Vo
A K
1N4001
1N4001 GND
C=100uF (0-10)mA. + +
(0-10)V
+
AC I/P 230V
A V
CRO
Z 9.1 - - Vo
0 -
DRB
GND
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Expt No: POWER SUPPLY CIRCUIT –FULL WAVE RECTIFIER Date:
Aim:
Apparatus Required:
The full wave rectifier conducts for both the positive and negative half cycles of the
input ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in
this circuit. The diodes feed a common load RL with the help of a centre tapped transformer.
The ac voltage is applied through a suitable power transformer with proper turn’s ratio. The
rectifier’s dc output is obtained across the load. The dc load current for the full wave rectifier
is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave
rectifier.
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Tabular Column:
Without filter:
vm 2
2vm (vrms )
Vin (dc) vm (v) (v) RippleFactor= 1
v v 2
(volts) rms
=2 dc
= (vdc )
v vr vm v1
With filter: 1 = T1= T2=
v
v r v vr Ripple Factor=
Vin (dc) vm vr rms dc v m v /v
(volts) (volts) 2 3 2 rms dc
Current (mA)
Voltage (Volts)
Formula Used:
1 1 = 0.028
4 3 f * c * RL 4 3 * 50 *100 f *1k
The efficiency of full wave rectification is twice that of half wave rectification. The
ripple factor also for the full wave rectifier is less compared to the half wave rectifier
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Model Graph:
RESULT:
Thus the full wave Rectifier is designed with and without Capacitor filter and the
corresponding dc voltage and the ripple factors are measured and verified with the theoretical
values
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SAMPLE VIVA –VOCE QUESTIONS AND ANSWERS
The proper flow of zero signal collector current and the maintenance of proper collector
emitter voltage during the passage of signal is called as transistor biasing.
2. What is the need to draw a DC load line on the output characteristics of a transistor?
The selected point on the load line, which represents the values of IC and VCE when
no signal is applied at the input, is known as quiescent point or Q-point.
1 . dIB
S= dIC
method. Advantages:
Disadvantages:
2. There are good chances of thermal runway. This is due to high stability factor S.
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1. It has the smallest value of S among the three biasing circuits.
It is necessary to stabilize the operating point of a transistor because the operating point
tends to shift its position due to any or all of the following three main factors.
i) Reverse saturation current, ICO, which doubles for every 10C increase in
temperature
The common mode rejection ratio [CMRR] serves as a figure of merit of a differential
amplifier and is defined as the ratio of the differential mode voltage gain (Ad) to the common
mode voltage gain (Ac) CMRR=Ad/Ac
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The curve drawn between the voltage gain and signal frequency of an amplifier is
known as the frequency response of an amplifier.
14. What are the different regions in the frequency response curve?
Midband region is the important region because the amplifier gain is constant
16. How a bandwidth can be can be calculated from the frequency response curve?
Bandwidth of an amplifier can be calculated from the frequency response curve by the
following procedure
Step2: Draw a –3dB horizontal line (parallel to x-axis) on the frequency response curve and
obtain the two intersection points.
Step3: Project these points on the x-axis as they correspond to the 3dB frequencies f1 and f2
Step4: Calculate BW = f2 – f1
18. Why the amplifier gain reduces at lower and upper frequencies?
At lower frequencies the amplifier gain reduces due to the coupling capacitors C1, C2
and bypass capacitors.
At upper frequencies the amplifier gain reduces due to the internal transistor
capacitance and stray capacitance.
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19.Mention two disadvantages which are specific to Darlington connection
(i)The main drawback of the Darlington pair is that the leakage current of the first transistor
is also amplified by the second stage, hence the overall leakage current may be high, so
Darlington connection of three or more is impractical.
(ii) The principal merit of Darlington circuit is its high input impedance. But the biasing
arrangement reduces the input impedance considerable in the case of ordinary emitter
follower as well as Darlington emitter follower.
20. List out the difference between small signal and large signal amplifier
Other name of small signal amplifier is Other name of large signal amplifier is
1
known as Voltage Amplifier known as Power Amplifier
3 Power dissipation is less than 0.5W Power dissipation is greater than 0.5W
The classification is based up on the transistor biasing and the amplitude of the input
signal. (i.e., Position of Q-point on the Load Line).
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22. What is cross over distortion?
In class B amplifiers, the transistors are biased at cutoff region these transistors can
operate in the active region if and only if the base emitter junction is forward biased.
To forward bias the base emitter junction, the i/p voltage must be greater than the cut-in
voltage. The cut-in voltage for silicon transistor is 0.7v
Thus as long as the i/p voltage is less than the cut in voltage, the transistors will
remain in the off state and the o/p will be zero.
Advantages:-
1. Simple circuit
2. Less cost
Disadvantages:-
3. The transformer is not effectively utilized i.e., its TUF is only 28.6%
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DIGITAL EXPERIMENTS
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(B) DIGITAL CIRCUITS LABORATORY
INDEX
Page
S.N0 Experiment Name
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AND GATE:
SYMBOL: PIN DIAGRAM:
OR GATE:
SYMBOL: PIN DIAGRAM:
NOT GATE:
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EXPT NO. : STUDY OF LOGIC GATES
DATE :
AIM:
To study about logic gates and verify their truth tables.
COMPONENTS REQUIRED:
THEORY:
A logic gate is an electronic circuit which makes logical decisions. To
arrive at these decisions, the most common logic gates used are OR, AND,
NOT, NAND and NOR gates. The NAND and NOR gates are called as the
Universal gates. The exclusive OR (XOR) gate is another logic gate which can
be constructed using basic gates such as AND, OR and NOT gates. Each
gate has two or more input and only one output except for the Not gate,
which has only one input. The logic gates are the building blocks of
hardware which are available in the form of various IC families. Each gate
has a distinct logic symbol and its operation can be described by means of
an algebraic function. The relationship between input and output variables
of each gate can be represented in a tabular form called a truth table.
AND GATE:
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2-INPUT NAND GATE:
SYMBOL: PIN DIAGRAM:
NOR GATE:
SYMBOL: PIN DIAGRAM:
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If A and B are the input variables of an AND gate and Y is its output,
then Y = A.B
Where the dot (.) denotes the AND operation.
OR GATE:
NOT GATE:
The NOT gate performs the basic logical function called inversion or
complementation. The purpose of this gate is to convert one logic level into
the opposite logic level. It has one input and one output. When a HIGH level
is applied to an inverter, a LOW level appears as its output and vice versa.
If A is an input variable of a NOT gate and Y is its output,
then Y =
NAND GATE:
NOR GATE:
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X-OR GATE :
SYMBOL : PIN DIAGRAM :
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If A and B are the input variables of a NOR gate and Y is its output,
then Y =
PROCEDURE:
Exercise
1. Draw the truth table for the following logic circuit and find
the output expression. What gate does the expression
represent?
RESULT:
Thus all logic gates are studied and their truth tables are verified.
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BINARY TO GRAY CODE CONVERTER
TRUTH TABLE:
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
G3 = B3 G2=B3’B2 +B3B2’
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EXPT NO. : DESIGN AND IMPLEMENTATION OF CODE
DATE : CONVERTER
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter using logic gates.
COMPONENTS REQUIRED:
THEORY:
The availability of large variety of codes for the same discrete elements
of information results in the use of different codes by different systems. A
conversion circuit must be inserted between the two systems if each uses
different codes for same information. Thus, code converter is a circuit that
makes the two systems compatible even though each uses different binary
code.
The bit combination assigned to binary code to gray code. Since each
code uses four bits to represent a decimal digit. There are four inputs and
four outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from
K-Map for each output variable.
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K-Map for G1: K-Map for G0:
LOGIC DIAGRAM:
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GRAY CODE TO BINARY CONVERTER
TRUTH TABLE:
B3 = G3 B2=G3’G2 + G3G2’
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K-Map for B1: K-Map for B0
B1=G3’G2’G1+G3’G2G1’+G3G2G1+G3G2’G1’ B0=G3’G2’G1’G0+G3’G2’G1G0’+G3’G2G1’G0’
= G1(G3’G2’+G3G2) + G1’(G3’G2+G2G3’) +G3’G2G1G0+ G3G2 G1’G0+G3G2G1G0’
= G1 (G2 G3) +G3G2’G1’G0’+G3G2’G1G0
LOGIC DIAGRAM:
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BCD TO EXCESS-3 CONVERTER
TRUTH TABLE:
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
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K-Map for E1: K-Map for E0:
LOGIC DIAGRAM
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EXCESS-3 TO BCD CONVERTER
TRUTH TABLE:
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
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K-Map for C: K-Map for D:
LOGIC DIAGRAM
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A code converter is a circuit that makes the two systems compatible
even though each uses a different binary code. To convert from binary code
to Excess-3 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuit as a function of the four
input variables.
A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. Now the OR gate whose output is
C+D has been used to implement partially each of three outputs.
PROCEDURE:
(iii) Observe the logical output and verify with the truth tables.
Exercise:
1. Design a code converter that converts
i) The 8,4,-2,-1 code to BCD code
ii) The gray code to 8,4,-2,-1 code
2. Design a code converter that converts a 2 4 2 1 code to gray code
RESULT:
Thus the code converters are designed using logic gates and their
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LOGIC DIAGRAM:
A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
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EXPT NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR
DATE :
AIM:
To design and implement 4-bit adder/subtractor and BCD adder
using IC 7483.
COMPONENTS REQUIRED:
THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers. It can be constructed with full adders connected in
cascade, with the output carry from each full adder connected to the input
carry of next full adder in chain. The augends bits of ‘A’ and the addend bits
of ‘B’ are designated by subscript numbers from right to left, with subscript
0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripples
through the full adder to the output carry C4.
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LOGIC DIAGRAM:
BCD ADDER K Map for Y Y =
S4 S3 + S4 S2
OUTPUT :
A B Carry Sum
Sl.No A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1
1
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4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one
circuit with one common binary adder. The mode input M controls the
operation. When M=0, the circuit is adder circuit. When M=1, it becomes
subtractor.
PROCEDURE:
(iii) Observe the logical output and verify with the truth tables.
Exercise:
RESULT:
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BLOCK DIAGRAM FOR 4:1 MULTIPLEXER: FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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EXPT NO. : DESIGN AND IMPLEMENTATION OF
DATE : MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic
gates.
COMPONENTS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND Gate IC 7411 2
2. OR Gate IC 7432 1
3. NOT Gate IC 7404 1
4. IC Trainer Kit - 1
5. Connecting Wires - Few
THEORY:
MULTIPLEXER:
Multiplexer means, transmitting a large number of information units
over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally there are 2n input line
and n selection lines whose bit combination determine which input is
selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It
takes information from one line and distributes it to a given number of
output lines. For this reason, the demultiplexer is also known as a data
distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the
AND gates. The data select lines enable only one gate at a time and the data
on the data input line will pass through the selected gate to the associated
data output line.
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BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
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PROCEDURE:
Exercise:
Multiplexers.
RESULT:
Thus the multiplexer/Demultiplexer are designed using logic
gates.
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TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
D0 = E’A’B’
D1 = E’A’B
D2 = E’AB’
D3 = E’AB
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EXPT NO : DESIGN AND IMPLEMENTATION OF ENCODER
DATE : AND DECODER
AIM:
To design and implement encoder and decoder using logic gates.
COMPONENTS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P NAND Gate IC 7410 2
2. OR Gate IC 7432 3
3. NOT Gate IC 7404 1
4. IC Trainer Kit - 1
5. Connecting Wires - Few
THEORY:
ENCODER:
An encoder is a digital circuit that performs inverse operation of a
decoder. An encoder has 2n input lines and n output lines. In encoder the
output lines generates the binary code corresponding to the input value. In
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise
the circuit is meaningless. It has an ambiguity that when all inputs are zero
the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which
converts coded input into coded output where input and output codes are
different. The input code generally has fewer bits than the output code. Each
input code word produces a different output code word i.e there is one to
one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2n
possible outputs. 2n output values are from 0 through out 2n – 1.
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TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
A= Y4 + Y5 + Y6 + Y7
B= Y2 + Y3 + Y6 + Y7
C = Y1 + Y3 + Y5 + Y7
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PROCEDURE:
Exercise:
RESULT:
Thus the Decoder and Encoder are designed and implemented
using Logic gates.
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PIN DIAGRAM FOR IC 7476:
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EXPT NO. : CONSTRUCTION AND VERIFICATION OF 4 BIT
DATE : RIPPLE COUNTER AND MOD 10/MOD 12
COUNTER
AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple
counter.
COMPONENTS REQUIRED:
THEORY:
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LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
TRUTH TABLE:
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
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LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
TRUTH TABLE:
CLK QA QB QC QD
(LSB) (MSB)
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
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LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
TRUTH TABLE:
CLK QA QB QC QD
(LSB) (MSB)
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
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PROCEDURE:
Exercise:
RESULT:
Thus 4-bit Ripple counter, MOD-10/MOD-12 Counters is
designed and their truth tables are verified.
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STATE DIAGRAM:
TRUTH TABLE:
Input Present Next State A B C
Up/Down State QA+1 Q B+1 QC+1 JA KA JB KB JC KC
QA QB QC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
K MAP
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EXPT NO. : DESIGN AND IMPLEMENTATION OF 3 BIT
DATE : SYNCHRONOUS UP/DOWN COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
COMPONENTS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK Flip Flop IC 7476 2
2. 3 I/P AND Gate IC 7411 1
3. OR Gate IC 7432 1
4. XOR Gate IC 7486 1
5. NOT Gate IC 7404 1
6. IC Trainer Kit - 1
7. Connecting Wires - Few
THEORY:
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CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LOGIC DIAGRAM:
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PROCEDURE:
(i) Connections are given as per circuit diagram.
Exercise:
1. Design a four bit synchronous counter with D flip flops
2. Construct 3 bit synchronous Up/ Down counter using T flip flops
RESULT:
Thus the 3-bit synchronous UP/DOWN counter is designed
and its truth table is verified.
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LOGIC DIAGRAM: PIN DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE
TRUTH TABLE
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EXPT NO. : DESIGN AND IMPLEMENTATION OF SHIFT
DATE : REGISTER
AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out shift registers using Flip Flops.
COMPONENTS REQUIRED:
THEORY:
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LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
1 1 0 0 1 1
2 0 0 0 0 0
3 0 0 0 0 0
4 0 0 0 0 1
LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:
TRUTH TABLE:
DATA INPUT OUTPUT
CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
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PROCEDURE:
Exercise:
RESULT:
Thus the Serial in serial out, Serial in parallel out, Parallel in
serial out and Parallel in parallel out are constructed.
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CONTENT BEYOND SYLLABUS
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LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR
K MAP
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DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
THEORY:
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TRUTH TABLE
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LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
TRUTH TABLE:
PROCEDURE:
RESULT:
Thus the 2 and 8 bit magnitude comparators were designed and the
output was verified.
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PIN DIAGRAM FOR IC 74180:
FUNCTION TABLE:
INPUTS OUTPUTS
Number of High Data PE PO ∑E ∑O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1
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16 BIT ODD/EVEN PARITY CHECKER /GENERATOR
AIM:
To design and implement 16 bit odd/even parity checker generator
using IC 74180.
APPARATUS REQUIRED:
THEORY:
In even parity, the added parity bit will make the total number is even
amount. In odd parity, the added parity bit will make the total number is
odd amount. The parity checker circuit checks for possible errors in the
transmission. If the information is passed in even parity, then the bits
required must have an even number of 1’s. An error occur during
transmission, if the received bits have an odd number of 1’s indicating that
one bit has changed in value during transmission.
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LOGIC DIAGRAM:
TRUTH TABLE:
LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATOR
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O
1 1 0 0 0 0 0 0 11 0 0 0 0 00 1 1 0
1 1 0 0 0 0 0 0 11 0 0 0 0 00 0 0 1
1 1 0 0 0 0 0 0 01 0 0 0 0 00 0 1 0
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PROCEDURE:
RESULT:
Thus the 16 bit odd/even parity checker and generator were designed
and the output was verified.
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Demonstration of following 3 bit variable Boolean expression
logic circuit.
Output Y=A
Step 1:
Y=AB’C’+AB’C+ABC+ABC’
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Using Boolean algebra techniques, the expression may be simplified as
Step 2:
Step 3:
Now OR1 Gate always produces the output 1 for all input combinations, In
AND2 and AND4 one input is always high. So, these Gates act as a buffer.
To simplify the logic circuit, Remove AND2, AND4, OR1 and NOT2 Gates.
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Step 4:
Step 5:
Now OR2 Gate always produces output one for all input combinations, after
Output Expression is Y=A, hence No gates required for the given Boolean
expression.
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Experiment No. 4
Design a digital Circuit having a 3 inputs and 1 output in which output will be
Experiment No.5
C When the binary input is 0,1,2,3 the binary output is one greater than the
input and when the binary input is 4,5,6,7 binary outputs is one less than
input.
Experiment No.6
Experiment No.7
Construct a Boolean function of three Variables P,Q and R that has an output
one When exactly two P,Q and R are having values Zero and output ‘Zero’ in
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SAMPLE VIVA VOCE QUESTIONS AND ANSWERS
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6. Draw the EX-NOR gate by using only NAND gate?
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8. What is a combinational logic circuit? Write an example.
When logic gates are connected together to produce a specified
output for certain specified combinations of input variables, with no
storage involved, the resulting circuit is called ‘combinational logic
circuit’.
9. What is a half-adder?
A half adder is an arithmetic circuit that adds two binary digits. It
has two inputs and two outputs only (sum and carry).
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14. What is a half-subtractor?
A half-subtractor is an arithmetic circuit that subtracts one binary
digit form another. It has two inputs and two outputs (difference and
borrow).
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20. List out the differences between Decoder and Encoder.
Encoder Decoder
1. In decoder one of the output 1. In encoder, the output lines
lines is activated corresponding generate the binary code,
to the binary input. corresponding to the input value.
2. Input of the decoder is an 2. Input of the encoder is a decoded
encoded information presented information presented as 2n
as n inputs prodcing 2n possible inputs producing n possible
outputs. outputs.
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23. List out the applications of Multiplexer?
It can be used to realize a Boolean Function
Data routing
Control Sequencer
It can be used in Communication Systems E.g; Time division
Multiplexing
24. Mention the uses of Decoder?
Decoders are used in Counter system
Used in code converter
Decoder outputs can be used to drive a display system.
25. What is a Comparator?
A comparator is a logic circuit that compares the magnitudes of
two binary numbers. The EX – NOR gate(coincidence gate) is a basic
comparator.
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29. Define Flip flop.
Flip flop is defined as a digital circuit which maintains its output
state either at 1 or 0 until directed by an input signal to change its
state. (1-bit storing element)
(Or)
Flip - flop is a sequential device that normally samples its inputs and
changes its outputs only at times determined by clocking signal.
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33. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the
output
Q is set and if D=0, the output is reset.
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38. What is a shift register?
The binary information in a register can be moved from stage to
stage within the register or into or out of the register upon application
of clock pulses. This type of bit movement or shifting is essential for
certain arithmetic and logic operations used in microprocessors. This
gives rise to group of registers called shift registers.
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42. Give the comparison between synchronous & Asynchronous
sequential circuits.
Synchronous sequential circuits Asynchronous sequential circuits
2. The change in input signals can 2. The change in input signals can
affect memory element upon affect memory element at any
activation of clock signal. instant of time.
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45. Compare the state diagram and the state table.
State table
The State table repre The state table representation of a
sequential circuit consists of three sections labelled present state, next
state and output. The present state designates the state of flip-flops
before the occurrence of a clock pulse. The next state shows the states
of flip-flops after the clock pulse, and the output section lists the
value of the output variables during the present state.
State Diagram
In addition to graphical symbols, tables or equations,
flip-flops can also be represented graphically by a state diagram. In
this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the
circles.
An example of a state diagram is shown in Figure below
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