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A 15-B Resolution 2-Mhz Nyquist Rate Adc in A 1-M Cmos Technology
A 15-B Resolution 2-Mhz Nyquist Rate Adc in A 1-M Cmos Technology
A 15-B Resolution 2-Mhz Nyquist Rate Adc in A 1-M Cmos Technology
I. INTRODUCTION
of the first integrator is 320 MHz. Note that the closed-loop gain of 80 dB and a closed-loop pole of 320 MHz. Hence, the
dominant pole of the subsequent integrators is slightly smaller, total switch resistance has to obey
due to the progressive scaling. However, this fact does not
impair the system performance, since the requirements for the (3)
last integrators are more relaxed.
This means that the sum of the resistance of the two switches
C. Effect of the Nonzero Switch Resistance on both sides of the first integrator sampling capacitor has to
be smaller than 200 .
The nonzero switch resistance combined with the finite
closed-loop pole can introduce a significant degradation in
the overall transfer function of an integrator [12]. Fig. 3(c) D. Effect of the Finite OTA Slew Rate
presents the results of the behavioral simulations of the overall Considering an OTA with finite gain and with a finite closed-
converter as a function of the switch resistance, for an OTA loop dominant pole, the effect of the OTA slew rate can be
1068 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
(a) (b)
(c) (d)
Fig. 3. (a) SNR as function of the OTA gain. (b) SNR as function of the OTA closed-loop pole. (c) SNR as function of the sampling time constant.
(d) SNR as function of OTA slew-rate.
modeled as described in [13]. Using the nonlinear difference sampling capacitor. This considerably slows down the initial
equations to model the performance of every integrator of the “charge redistribution,” reducing the amplitude of the initial
modulator, the performance of the overall converter as a feedforwarded voltage and relaxing the slew-rate specification.
function of the normalized OTA slew rate is evaluated through Using a more elaborate model, that accounts for this effect,
behavioral simulations. Fig. 3(d) presents the converter perfor- and considering the value of the RC time constant used in this
mance as a function of the normalized OTA slew-rate. Hence, design, the previous slew-rate specification could be relaxed
the slew-rate should obey to approximately 300 V/ s.
[4], but, in fact, to avoid signal-dependent charge injection, with the associated switching logic is presented in Fig. 5. One
only the falling clock edges need to be delayed [14]. Hence, aspect of the design worth mentioning is the relative scaling of
in this design, in order to efficiently use the short clock the top and bottom regeneration loops. For signals below the
period, the falling clock edges are delayed and the rising clock resolution of the comparator, the initial imbalance is difficult
edges are synchronized. The circuit designed to implement this to regenerate. Hence, to avoid an eventual improper trigger
clocking scheme is shown in Fig. 4. of the SR latch, the metastable point at the top regeneration
loop must be made higher than the threshold voltage of the
SR latch.
B. Design of the Comparator
The specifications of the comparator were not discussed
in the previous section because, in general, they are quite C. Design of the OTA
relaxed. One can find, by behavioral simulations, that the Due to its good frequency characteristics, a fully differential
offset and hysteresis should be smaller than 100 and 40 mV, folded cascode OTA is selected [15]. The gain is increased
respectively. Although both specifications are easy to achieve, with a gain-boosting stage [16], with just one transistor, that
it is interesting to note that the hysteresis is more important can be designed so that neither the frequency nor the settling
than the offset for the converter operation. The comparator [18] characteristics are impaired [17]. The schematic diagram of the
1070 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
(5)
(6)
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC 1071
(7)
and (8) and (9), shown at the bottom of the page. The total
sampled noise power of a white noise source with
Fig. 8. Simplified schematic diagram of the OTA.
an equivalent noise resistance , filtered by the transfer
function , is given by
broad-band and a sampled noise component at the output of
the integrator [19]. The broad-band component is due to the (10)
all noise sources that inject noise at the output in, at least, one
phase. The sampled noise component results from the sampling
Due to the oversampling nature of the converter, only the
on of the broad-band noise. Since the noise bandwidth of
part of this noise that lies in the Nyquist band contributes to
the broad-band noise is always much larger than the sampling
the converter noise power. The inband noise power is just
frequency, the OTA flicker noise is completely “submerged”
by the aliased sampled noise. Hence, the OTA flicker noise is OSR (11)
neglected in this analysis. Moreover, since the sampled noise is
folded, and appears at the output integrated, it is much higher In the case of the switches resistance noise, the equivalent
than the broad-band noise. At high frequencies, the broad- resistance is just the switches resistance . In the case of the
band noise component still contributes somewhat to the noise OTA noise, the equivalent resistance is 2/3 , where is
of the second integrator, but there, it is of lesser importance the OTA excess noise factor [15]. For this OTA structure, the
[see (1)]. Therefore, the broad-band noise component is also excess noise factor is given approximately by
neglected in this analysis.
The sampled noise component due to the switches resistance (12)
and the OTA is now discussed. There are three important
noise contributions to the total sampled noise. First, during which is, in this design, about 2.75.
the sampling phase, the switches resistance noise is sampled The inband sampled noise power for each of the previous
on , and it is integrated on the next phase. Second, during noise sources is then given by
(8)
(9)
1072 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
(a)
Fig. 10. Plot of the poles and zero versus scaling of the bias current of the
gain-boosting transistors. x: real part of the pole; o: zero frequency; dashed
line: closed-loop dominant pole.
TABLE II
CALCULATED SAMPLED NOISE POWERS
Nrs -102 dBv
Nri -102 dBv
Noi -110 dBv
(b) Nwn -99 dBv
Fig. 14. Plot illustrating the converter noise floor with the inputs short
circuited.
TABLE III
CONVERTER PERFORMANCE
DR 91 dB
SNR 90 dB
SNDR 85 dB
Oversampling Ratio 24
Sampling Rate 48 MHz
Signal Bandwidth 1 MHz
Supply Voltage 5V
Power Consumption 230 mW
Technology 1 m CMOS DMDP
Die Area 2
2.5 2.1 mm2
Fig. 15. Spectrum of the converter output for a sinusoidal input signal.
Fig. 17. Figure of merit for several published 16 converters.
REFERENCES Vincenzo Peluso, photograph and biography not available at the time of
publication.
[1] L. Williams and B. Wooley, “Third-order cascaded Sigma-Delta modu-
lators,” IEEE J. Solid-State Circuits, vol. 38, pp. 489–497, May 1991.
[2] B. Boser and B. Wooley, “The design of Sigma-Delta modulation
analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 23, pp.
1298–1308, Dec. 1988. Michel S. J. Steyaert (S’85–A’89–SM’92) was
[3] B. Brandt and B. Wooley, “A 50-MHz multi-bit Sigma-Delta modulator born in Aalst, Belgium, in 1959. He received the
for 12-b 2-MHz A/D conversion,” IEEE J. Solid-State Circuits, vol. 26, Master’s degree in electrical–mechanical engineer-
pp. 1746–1756, Dec. 1991. ing and the Ph.D. degree in electronics from the
[4] G. Yin and W. Sansen, “A high-frequency and high-resolution fourth- Katholieke Universiteit Leuven, Heverlee, Belgium,
order 61 A/D converter in BiCMOS technology,” IEEE J. Solid-State in 1983 and 1987, respectively.
Circuits, vol. 29, pp. 857–865, Aug. 1994. From 1983 to 1986, an IWNOL Fellowship (Bel-
[5] T. Brooks, D. Robertson, D. Kelly, A. Muro, and S. Harston, “A 16 gian National Foundation for Industrial Research)
b 61 ADC with 2.5 MHz output data-rate,” in Proc. ISSCC’97, Feb. allowed him to work as a Research Assistant at the
1997, pp. 208–209. ESAT Laboratory, Katholieke Universiteit Leuven.
[6] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “Optimal parame- In 1987, he was responsible for several industrial
ters for cascade 16 modulators,” in Proc. IEEE ISCAS’97, June 1997, projects in the field of analog micropower circuits at the ESAT Laboratory,
pp. 61–64. as an IWONL Project Researcher. In 1988, he was a Visiting Assistant
[7] V. Peluso, A. Marques, M. Steyaert, and W. Sansen, “Optimal param- Professor at the University of California, Los Angeles. In 1989, he was
eters for single loop 16 modulators,” in Proc. IEEE ISCAS’97, June appointed a Research Associate by the National Fund of Scientific Research
1997, pp. 57–60. (Belgium) at the ESAT Laboratory, where he was appointed a Senior Research
[8] K. Martin and A. Sedra, “Effects of the op amp finite gain and bandwidth Associate in 1992 and a Research Director in 1996. Between 1989–1996,
on the performance of SC filters,” IEEE Trans. Circuits Syst., vol. he was also a Part-Time Associate Professor and, since 1997, he has been
CAS-28, pp. 822–829, Aug. 1981. an Associate Professor at the Katholieke Universiteit Leuven. His current
[9] G. Temes, “Finite gain and bandwidth effects in SC filters,” IEEE J. research interests are high-performance and high-frequency analog integrated
Solid-State Circuits, vol. SC-15, pp. 358–361, June 1980. circuits for telecommunication systems and analog signal processing.
[10] R. Geiger and E. Sanchez-Sinencio, “Operational amplifier gain- Prof. Steyaert received the 1990 European Solid-State Circuits Conference
bandwidth product effects on the performance of switched-capacitor Best Paper Award, the 1995 ISSCC Evening Session Award, and the 1991
networks,” IEEE Trans. Circuits Syst., vol. CAS-29, pp. 96–106, Feb. NFWO Alcatel–Bell Telephone Award for innovative work in integrated
1982. circuits for telecommunications.
[11] G. Fisher and G. Moschytz, “On the frequency limitations of SC filters,”
IEEE J. Solid-State Circuits, vol. SC-19, pp. 510–518, Aug. 1984.
[12] A. Robertini and W. Guggenbühl, “Errors in SC circuits derived from
linearly modeled amplifiers and switches,” IEEE Trans. Circuits Syst. I,
vol. 39, pp. 93–101, Feb. 1992. Willy Sansen (S’66–M’72–SM’86–F’95) was born
[13] W. Sansen, H. Qiuting, and K. Halonen, “Transient analysis of charge in Poperinge, Belgium, in 1943. He received the
transfer in SC filters—Gain error and distortion,” IEEE J. Solid-State Master’s degree in electrical engineering from the
Circuits, vol. SC-22, pp. 268–276, Apr. 1987. Katholieke Universiteit Leuven, Heverlee, Belgium,
[14] D. Haigh and B. Singh, “A switching scheme for switched capacitor in 1967 and the Ph.D. degree in electronics from the
filters which reduces the effects of parasitic capacitances associated with University of California, Berkeley, in 1972.
switch control terminals,” in Proc. ISCAS’83, 1983, pp. 586–589. In 1968, he joined the Katholieke Universiteit
[15] K. Laker and W. Sansen, Design of Analog Integrated Circuits and Leuven as a Research Assistant. During 1971, he
Systems. New York: McGraw-Hill, 1994. was a Teaching Fellow at the University of Califor-
[16] K. Bult and G. Geelen, “A fast-settling CMOS op amp for SC cir- nia, Berkeley. In 1972, he was appointed a Research
cuits with 90-dB DC gain,” IEEE J. Solid-State Circuits, vol. 25, pp. Associate by the National Fund of Scientific Re-
1379–1384, Dec. 1990. search (Belgium) at the ESAT Laboratory, Katholieke Universiteit Leuven,
[17] D. Flandre, A. Viviani, J. Eggermont, B. Gentine, and P. Jespers, where he has been a Full Professor since 1981. During 1984–1990, he was
“Design methodology for CMOS gain-boosted folded-cascode OTA also the Head of the Electrical Engineering Department. In 1978, he spent the
with application to SOI technology,” in Proc. ESSCIRC’96, 1996, pp. winter quarter at Stanford University, Stanford, CA, as a Visiting Assistant
320–323. Professor. He was a Visiting Professor at the Federal Technical University,
[18] G. Yin, F. Op’t Eynde, and W. Sansen, “A high-speed CMOS com- Lausanne, Switzerland, at the University of Pennsylvania, Philadelphia, and
parator with 8-b resolution,” IEEE J. Solid-State Circuits, vol. 27, pp. at the Technical University, Ulm, Germany, in 1981, 1985, and 1994,
208–211, Dec. 1990. respectively. He is a member of the editorial committees of several journals,
[19] C. Gobet and A. Knob, “Noise analysis of switched capacitor networks,” including Sensors and Actuators and High Speed Electronics. He has been
IEEE Trans. Circuits Syst., vol. CAS-30, pp. 37–43, Jan. 1983. involved in design automation and in numerous analog integrated circuit
[20] S. Rabii and B. Wooley, “A 1.8-V digital-audio Sigma-Delta modulator designs for telecom, consumer electronics, medical applications, and sensors.
in 0.8-m CMOS,” IEEE J. Solid-State Circuits, vol. 32, pp. 783–796, He has supervised 30 Ph.D. theses. He has authored or coauthored 300
June 1997. papers in international journals and conference proceedings and six books,
including the textbook (with K. Laker) Design of Analog Integrated Circuits
and Systems.
Prof. Sansen is a Member of the Editorial Committee of the IEEE
Augusto Manuel Marques was born in Tomar, JOURNAL OF SOLID-STATE CIRCUITS. He serves regularly on the program
Portugal, in 1967. He received the B.Sc. degree committees of various conferences, including ISSCC, ESSCIRC, ASICTT,
in computer engineering and the M.S. degree in EUROSENSORS, TRANSDUCERS, and EDAC.
technological physics from the Faculty of Science
and Technology, University of Coimbra, Coimbra,
Portugal, in 1990 and 1992, respectively. He is
currently working towards the Ph.D. degree at the
Katholieke University Leuven, Heverlee, Belgium.
In 1992, he joined the Physics Department, Uni-
versity of Coimbra, Coimbra, Portugal, as a Re-
search Assistant. His current research interests are
the design and testing of high-speed and high-resolution analog-to-digital and
digital-to-analog data converters.