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Ee101 DGTL 4 PDF
Ee101 DGTL 4 PDF
Ee101 DGTL 4 PDF
M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
A A B X1 X2
X1
X2
B
* A, B: inputs, X1 , X2 : outputs
NAND latch (RS latch)
A A B X1 X2
X1
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
NAND latch (RS latch)
A A B X1 X2
X1
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
NAND latch (RS latch)
A A B X1 X2
X1
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
The circuit has “latched in” the previous state.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
The circuit has “latched in” the previous state.
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not
allowed for reasons that will become clear later.
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 1 1
* A, B: inputs, X1 , X2 : outputs
* Consider A = 1, B = 0.
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
* Consider A = 0, B = 1.
Show that X1 = 1, X2 = 0.
* Consider A = B = 1.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
The circuit has “latched in” the previous state.
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not
allowed for reasons that will become clear later.
M. B. Patil, IIT Bombay
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
NAND latch (RS latch)
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B 0 0 invalid
A A B X1 X2 R R S Q Q
X1 Q
1 0 0 1 1 0 0 1
0 1 1 0 0 1 1 0
1 1 previous 1 1 previous
X2 Q
B 0 0 invalid S
0 0 invalid
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S 0 0 invalid Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S 0 0 invalid Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S 0 0 invalid Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t1 , R goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S 0 0 invalid Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t1 , R goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S 0 0 invalid Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t1 , R goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.
* At t = t3 , S goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3
NAND latch (RS latch)
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3 t4
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3 t4
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q
Q t
S 0 0 1 1 Q
t
t1 t2 t3 t4 t5
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q ?
Q t
S 0 0 1 1 Q ?
t
t1 t2 t3 t4 t5
R
R R S Q Q t
Q
1 0 0 1 S
0 1 1 0 t
1 1 previous Q ?
Q t
S 0 0 1 1 Q ?
t
t1 t2 t3 t4 t5
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S
1 1 invalid
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S
1 1 invalid
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S
1 1 invalid
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S
1 1 invalid
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S
0 0 invalid
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S
1 1 invalid
A
Vs R Vo
Chatter (bouncing) due to a mechanical switch
A
Vs R Vo
B
Vo
A
Vs
Vs R Vo
t
expected
B
Vo
A
Vs
Vs R Vo
t
expected
B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual
B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual
5V
S
R S Q Q
t
R Q 1 0 0 1
B 0 1 1 0 R
A 1 1 previous t
S
0 0 invalid Q
t
5V
5V
S
R S Q Q
t
R Q 1 0 0 1
B 0 1 1 0 R
A 1 1 previous t
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when
the switch is thrown from A to B.
5V
S
R S Q Q
t
R Q 1 0 0 1
B 0 1 1 0 R
A 1 1 previous t
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when
the switch is thrown from A to B.
* However, for S = R = 1, the previous value of Q is retained, causing a single
transition in Q, as desired.
* Complex digital circuits are generally designed for synchronous operation, i.e.,
transitions in the various signals are synchronised with the clock.
* Complex digital circuits are generally designed for synchronous operation, i.e.,
transitions in the various signals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages
at the nodes (both output nodes and internal nodes) can change only at specific
times.
* Complex digital circuits are generally designed for synchronous operation, i.e.,
transitions in the various signals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages
at the nodes (both output nodes and internal nodes) can change only at specific
times.
* A clock is a periodic signal, with a positive-going transition and a negative-going
transition.
positive−going negative−going
transition transition
1
0 t
T
* Complex digital circuits are generally designed for synchronous operation, i.e.,
transitions in the various signals are synchronised with the clock.
* Synchronous circuits are easier to design and troubleshoot because the voltages
at the nodes (both output nodes and internal nodes) can change only at specific
times.
* A clock is a periodic signal, with a positive-going transition and a negative-going
transition.
positive−going negative−going
transition transition
1
0 t
T
* The clock frequency determines the overall speed of the circuit. For example, a
processor that operates with a 1 GHz clock is 10 times faster than one that
operates with a 100 MHz clock.
CLK R S Q Q
S A A B Q Q
A
Q 0 X X previous Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B
1 1 1 invalid
CLK R S Q Q
S A A B Q Q
A
Q 0 X X previous Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B
1 1 1 invalid
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.
CLK R S Q Q
S A A B Q Q
A
Q 0 X X previous Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B
1 1 1 invalid
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS
latch (right), we can construct the truth table for the clocked RS latch.
CLK R S Q Q
S A A B Q Q
A
Q 0 X X previous Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B
1 1 1 invalid
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS
latch (right), we can construct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK
is 0 or 1).
CLK R S Q Q
S A
Q 0 X X previous
1 1 0 0 1
CLK
1 0 1 1 0
Q 1 0 0 previous
R B
1 1 1 invalid
CLK
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active
(CLK = 1), the flip-flop output is allowed to change, depending on the R and S
inputs.
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active
(CLK = 1), the flip-flop output is allowed to change, depending on the R and S
inputs.
* In an edge-sensitive flip-flop, the output can change only at the active clock
edge (i.e., CLK transition from 0 to 1 or from 1 to 0).
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active
(CLK = 1), the flip-flop output is allowed to change, depending on the R and S
inputs.
* In an edge-sensitive flip-flop, the output can change only at the active clock
edge (i.e., CLK transition from 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R Q R Q
CLK CLK
S Q S Q
R S Q Q R
J
1 0 0 1 Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
JK flip-flop
R S Q Q R
J
1 0 0 1 Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
JK flip-flop
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1 Q
1 0 0 previous (Qn )
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S 1 1 1 toggles (Qn )
RS latch
Truth table for RS latch Truth table for JK flip−flop
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
1 0 0 previous (Qn )
CLK 1 0 1 0
1 1 0 1
Q
K
S 1 1 1 toggles (Qn )
RS latch
Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
1 0 0 previous (Qn )
CLK 1 0 1 0
1 1 0 1
Q
K
S 1 1 1 toggles (Qn )
RS latch
Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
1 0 0 previous (Qn )
CLK 1 0 1 0
1 1 0 1
Q
K
S 1 1 1 toggles (Qn )
RS latch
Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
1 0 0 previous (Qn )
CLK 1 0 1 0
1 1 0 1
Q
K
S 1 1 1 toggles (Qn )
RS latch
Truth table for JK flip−flop
Master Slave
Q
K
RS latch 1 RS latch 2
CLK CLK
JK flip-flop (Master-Slave)
Master Slave
Q
K
RS latch 1 RS latch 2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its
previous value (because CLK = 0 → R2 = S2 = 1).
JK flip-flop (Master-Slave)
Master Slave
Q
K
RS latch 1 RS latch 2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its
previous value (because CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since
R1 = S1 = 1), and Q1 can now affect Q.
JK flip-flop (Master-Slave)
Master Slave
Q
K
RS latch 1 RS latch 2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its
previous value (because CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since
R1 = S1 = 1), and Q1 can now affect Q.
* In other words, the effect of any changes in J and K appears at the output Q
only when CLK makes a transition from 1 to 0.
This is therefore a negative edge-triggered flip-flop.
JK flip-flop (Master-Slave)
Master Slave
CLK J K Qn+1
J
0 0 Qn
0 1 0
1 0 1
Q
K 1 1 Qn
RS latch 1 RS latch 2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its
previous value (because CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since
R1 = S1 = 1), and Q1 can now affect Q.
* In other words, the effect of any changes in J and K appears at the output Q
only when CLK makes a transition from 1 to 0.
This is therefore a negative edge-triggered flip-flop.
JK flip-flop (Master-Slave)
Master Slave
CLK J K Qn+1
J
0 0 Qn
0 1 0
1 0 1
Q
K 1 1 Qn
RS latch 1 RS latch 2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its
previous value (because CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since
R1 = S1 = 1), and Q1 can now affect Q.
* In other words, the effect of any changes in J and K appears at the output Q
only when CLK makes a transition from 1 to 0.
This is therefore a negative edge-triggered flip-flop.
* Note that, unlike the RS NAND latch which does not allow one of the
combinations of R and S (viz., R = S = 0), the JK flip-flop allows all four
combinations.
M. B. Patil, IIT Bombay
JK flip-flop
K Q 1 0 1 1 0 1
K Q
1 1 Qn 1 1 Qn
K Q 1 0 1 1 0 1
K Q
1 1 Qn 1 1 Qn
* Both negative (e.g., 74101) and positive (e.g., 7470) edge-triggered JK flip-flops
are available as ICs.
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
CLK J K Qn+1
J Q Qn
0 0
CLK 0 1 0
K Q 1 0 1
1 1 Qn
CLK
K Q 1 0 1 1 0 1
K Q
1 1 Qn 1 1 Qn
CLK CLK
J J
K K
Q Q
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
time (msec) time (msec)
t
K Q K2 K Q
K1 Q2
CLK t
t1 t2 t3 t4 t5
JK flip-flop
t
K Q K2 K Q
K1 Q2
CLK t
t1 t2 t3 t4 t5
t
K Q K2 K Q
K1 Q2
CLK t
t1 t2 t3 t4 t5
t
K Q K2 K Q
K1 Q2
CLK t
t1 t2 t3 t4 t5
t
K Q K2 K Q
K1 Q2
CLK t
t1 t2 t3 t4 t5
J1 Q1 J2 t1 1 0 1
1 J Q J Q Q2 t
Q1 t2 0 1 0
t t3 1 0 1
K Q K2 K Q
K1 Q2 t4 0 1 0
t t5 1 0 1
CLK
t1 t2 t3 t4 t5
J1 Q1 J2 t1 1 0 1
1 J Q J Q Q2 t
Q1 t2 0 1 0
t t3 1 0 1
K Q K2 K Q
K1 Q2 t4 0 1 0
t t5 1 0 1
CLK
t1 t2 t3 t4 t5
J1 Q1 J2 t1 1 0 1
1 J Q J Q Q2 t
Q1 t2 0 1 0
t t3 1 0 1
K Q K2 K Q
K1 Q2 t4 0 1 0
t t5 1 0 1
CLK
t1 t2 t3 t4 t5