B.E.

(Electronics & Telecommunication / Electronics & Communication Engineering)

Eighth Semester (C.B.S.)
Elective – III : CMOS VLSI Design

P. Pages : 2 TKN/KS/16/7655
Time : Three Hours *0706* Max. Marks : 80
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Notes : 1. All questions carry marks as indicated.
2. Solve Question 1 OR Questions No. 2.
3. Solve Question 3 OR Questions No. 4.
4. Solve Question 5 OR Questions No. 6.
5. Solve Question 7 OR Questions No. 8.
6. Solve Question 9 OR Questions No. 10.
7. Solve Question 11 OR Questions No. 12.
8. Due credit will be given to neatness and adequate dimensions.
9. Illustrate your answers whenever necessary with the help of neat sketches.

1. a) Explain the working of E-type PMOS transistor in 3 different region of operation. 7

b) Calculate the native threshold voltage for an N-transistor at 300ºK for a process with a Si 7
16 3
substrate with N A  1.8 x 10 / CM , a SiO 2 gate oxide with thickness 200ºA
(Assume ms  0.9V, mc  0) .
OR
2. a) Derive the basic DC equation of MOS transistor in 3 region of operation. 7

b) Explain the small signal model for a MOS transistor and find the expression for gm and 7
gds.

3. Explain the five regions of operation of CMOS inverter D.C. transfer characteristics. 13
Hence derive the expression for the same.
OR
4. a) What is BiCMOS inverter? Compare with CMOS inverter. 7

b) What is transmission gate? Explain in detail. 6

5. Design CMOS logic gate for the following function. 13

i) f   A  BE  DE ii ) f  ABCD
iii ) f  A B  AB iii ) f  A B  AB
OR
6. a) Draw and explain the operation of DRAM cell. 6

b) Design a CMOS positive Edge triggered D flip flop. 7

7. a) Derive an expression for Rise time, fall time and delay time of a CMOS inverter. 10

b) Write a short note on charge sharing. 4

OR
8. a) Derive an expression for static, dynamic and short circuit dissipation and hence total 9
power dissipation.

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 b) Write a short note on capacitance estimation. 5

9. a) What are different layout design rules? Explain  -Based design rule. 6

b) Draw the stick diagram of 7

i) CMOS inverter. ii) NAND gate.
OR
10. Write a short note on any three. 13

i) Fan-in & Fan-out. ii) Domino logic.

iii) Clocking strategies. iv) Transistor sizing.

11. a) What is DFT? What is its need? Explain. 6

b) Explain in detail 'Boundary scan Technique'. 7

OR
12. a) What is BIST? Explain its operation with advantages & disadvantages. 7

b) What are the different types of Faults? Explain in detail. 6

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