EE/COSC 2390 Homework Set 5 Solutions Spring 2004

4-1(a,b) For the combinational circuit given. . .

(a) Derive the Boolean expressions for T1 through T4 . Evaluate the outputs F1 and F2 as a function of
the four inputs.

T1 = B
C
T2 = A
B
T3 = A + T1 = A + B
C
T4 = D ⊕ T2 = D ⊕ A
B = A
BD
+ D(A + B
) = A
BD
+ AD + B
D
F1 = T3 + T4 = A + B
C + A
BD
+ AD + B
D = A + BD
+ B
D + B
C
F2 = D + T2 = D + A
B

Note: to get to the final form of F1 shown above, I applied a K-map.

(b) List the truth table with 16 binary combinations of the four input variables. Then list the binary
values for T1 through T4 and outputs F1 through F2 in the table.

A B C D T1 T2 T3 T4 F1 F2
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 1 1
0 0 1 0 1 0 1 0 1 0
0 0 1 1 1 0 1 1 1 1
0 1 0 0 0 1 0 1 1 1
0 1 0 1 0 1 0 0 0 1
0 1 1 0 0 1 0 1 1 1
0 1 1 1 0 1 0 0 0 1
1 0 0 0 0 0 1 0 1 0
1 0 0 1 0 0 1 1 1 1
1 0 1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 1 1 1
1 1 0 0 0 0 1 0 1 0
1 1 0 1 0 0 1 1 1 1
1 1 1 0 0 0 1 0 1 0
1 1 1 1 0 0 1 1 1 1

1
EE/COSC 2390 Homework Set 5 Solutions Spring 2004

4-2 Obtain the simplified Boolean expressions for output F and G in terms of the input variables in the
circuit given.

From the circuit diagram in the text, we have the following:

F = (A
(A
D)
)
(A
+ BC)

= (A + A
D)(A
+ BC)
= AA
+ ABC + A
A
D + A
BCD
= ABC + A
D + A
BCD
= ABC + A
D

and

G = (A
+ BC)((A
D)
)

= (A
+ BC)(A + D
)
= A
A + A
D
+ ABC + BCD

= A
D
+ ABC

where the last simplification step in both F and G might be aided via a K-map.

4-4 Design a combinational circuit with three inputs and one output. The output is 1 when the binary
value of the inputs is less than 3. The output is 0 otherwise.

To speak in Boolean function terms, I will call the desired function H and the inputs, from most significant
bit to least significant bit, A and B and C. So, in SOP canonical form, we want to design a circuit such
that

H(A, B, C) = (0, 1, 2) .
You can use a K-map to find that this reduces to

H(A, B, C) = A
B
+ A
C
= A
(B
+ C
) .

A schematic for this circuit is shown below.

A
INV

AND2
B H
INV
OR2

C
INV AND2

4-28 Design a circuit using a 3-to-8 decoder and external gates to provide the following Boolean functions:

F1 = x
y
z
+ xz
F2 = xy
z
+ x
y
F3 = x
y
z + xy

2
EE/COSC 2390 Homework Set 5 Solutions Spring 2004

First note that for a decoder design, we want to know the canonical SOP (list of minterms). For our given
functions, using the order F1 (x, y, z) as a basis for the minterm numbering, we have. . .


F1 (x, y, z) = x
y
z
+ xz = (0, 5, 7)


F2 (x, y, z) = xy
z
+ x
y = (2, 3, 4)


F3 (x, y, z) = x
y
z + xy = (1, 6, 7)

So, we’re just left to “hook up the external gates” after correctly attaching the inputs to the select lines
of the decoder. A schematic is shown below.

D3_8E

z A0 D0

y A1 D1 F1

x A2 D2
OR3
D3

D4 F2

D5
VCC OR3
D6

E D7 F3

OR3

The particular decoder I used in the schematic happens to be in the Xilinx symbol set for the xc95108.
Because this one has an enable, I had to tie it to an “always enabled” condition. Your mileage may vary
depending upon the mux you use.

3
EE/COSC 2390 Homework Set 5 Solutions Spring 2004

4-31 Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers. Use block diagrams.

In order to describe the design scheme, I’ll assume that we have 16 data inputs in the bus D(15:0) and
four select lines Sel(3:0), The scheme is to use the two 8 × 1 muxes to select data from within the upper
and lower “bytes” of D(15:0), then the final 2 × 1 mux selects the appropriate byte. The schematic
shown below summarizes this connection. Note in particular the wiring of the select lines, with the most
significant bit Sel(3) controlling the final mux.

D(15:0)

M8_1E
D(0) D0

D(1) D1
Sel(3:0)
D(2) D2

D(3) D3
O
D(4) D4

D(5) D5

D(6) D6

D(7) D7

Sel(0) S0

Sel(1) S1

Sel(2) S2
M2_1
D0
VCC O
E M
D1

S0
Sel(3)

M8_1E
D(8) D0

D(9) D1

D(10) D2

D(11) D3
O
D(12) D4

D(13) D5

D(14) D6

D(15) D7

Sel(0) S0

Sel(1) S1

Sel(2) S2

VCC E