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TOPIC: Timing Checks: Module 3.1 Delays in Verilog
TOPIC: Timing Checks: Module 3.1 Delays in Verilog
Violation is reported if
(Treference_event – Tdata_event) < limit.
$setup example
Violation is reported if
( Tdata-event - Treference-event) < limit
$hold task example
specify
$hold(posedge-clear, data, 5);
endspecify
$width Check
Violation is reported if
( Tdata-event – Treference-event) < limit.
$width Check example
specify
$width (posedge clock, 6 ) ;
endspecify