DDCA Ch1

Chapter 1 :: From Zero to One Chapter 1 :: Topics
• Background
• The Game Plan
• The Art of Managing Complexity
• The Digital Abstraction
Digital Design and Computer Architecture
• Number Systems
David Money Harris and Sarah L. Harris
• Logic Gates
• Logic Levels
• CMOS Transistors
• Power Consumption
Copyright © 2007 Elsevier 1-<1> Copyright © 2007 Elsevier 1-<2>
Background The Game Plan
• Microprocessors have revolutionized our world • The purpose of this course is that you:
– Cell phones, Internet, rapid advances in medicine, etc. – Learn what’s under the hood of a computer
• The semiconductor industry has grown from $21 – Learn the principles of digital design
billion in 1985 to $213 billion in 2004 – Design and build a microprocessor
1
The Art of Managing Complexity Abstraction
Application
• Abstraction • Hiding details when Software
programs
• Discipline they aren’t important Operating

Systems
device drivers
• The Three –Y’s Architecture

instructions
registers
focus of this course

– Hierarchy Micro- datapaths
architecture controllers
– Modularity adders
Logic
memories
– Regularity
Digital AND gates
Circuits NOT gates
Analog amplifiers
Circuits filters
transistors
Devices
diodes
Physics electrons
Discipline The Three -Y’s
• Intentionally restricting your design choices • Hierarchy

– to work more productively at a higher level of – A system divided into modules and submodules
abstraction • Modularity
• Example: Digital discipline – Having well-defined functions and interfaces
– Considering discrete voltages instead of continuous • Regularity
voltages used by analog circuits
– Encouraging uniformity, so modules can be easily
– Digital circuits are simpler to design than analog reused
circuits – can build more sophisticated systems
– Digital systems replacing analog predecessors:
• I.e., digital cameras, digital television, cell phones, CDs
2
Example: Flintlock Rifle Example: Flintlock Rifle
• Hierarchy • Modularity
– Three main modules: – Function of stock:
lock, stock, and mount barrel and
barrel lock
– Submodules of lock: – Interface of stock:
hammer, flint, length and location
frizzen, etc. of mounting pins
• Regularity
– Interchangeable
parts
The Digital Abstraction The Analytical Engine
• Most physical variables are continuous, for • Designed by Charles

example Babbage from 1834 –
– Voltage on a wire 1871
– Frequency of an oscillation • Considered to be the first
– Position of a mass
digital computer
• Built from mechanical
• Instead of considering all values, the digital
gears, where each gear
abstraction considers only a discrete subset of represented a discrete
values value (0-9)
• Babbage died before it
was finished
3
Digital Discipline: Binary Values George Boole, 1815 - 1864
• Typically consider only two discrete values: • Born to working class parents
– 1’s and 0’s • Taught himself mathematics and
– 1, TRUE, HIGH joined the faculty of Queen’s
College in Ireland.
– 0, FALSE, LOW
• Wrote An Investigation of the Laws
• 1 and 0 can be represented by specific voltage of Thought (1854)
levels, rotating gears, fluid levels, etc. • Introduced binary variables
• Digital circuits usually depend on specific voltage • Introduced the three fundamental
levels to represent 1 and 0 logic operations: AND, OR, and
NOT.
• Bit: Binary digit
Number Systems Powers of Two
• Decimal numbers • 20 = • 28 =
• 21 = • 29 =
1000's column
10's column
1's column
100's column
• 22 = • 210 =
537410 = • 23 = • 211 =
• 24 = • 212 =
• Binary numbers
• 25 = • 213 =
8's column
2's column
1's column
4's column
• 26 = • 214 =
11012 = • 27 = • 215 =
4
Number Conversion Binary Values and Range
• Decimal to binary conversion: • N-digit decimal number

– Convert 101012 to decimal – Represents 10N possible values
– Range is: [0, 10N - 1]
– For example, a 3-digit decimal number represents 103 =
1000 possible values, with a range of [0, 999]
• Decimal to binary conversion: • N-bit binary number

– Represents 2N possible values
– Convert 4710 to binary
– Range is: [0, 2N - 1]
– For example, a 3-digit binary number represents 23 = 8
possible values, with a range of [0, 7]
(0002 to 1112)
Hexadecimal Numbers Hexadecimal Numbers

Hex Digit Decimal Equivalent Binary Equivalent
0 0 • Base 16
1 1
2 2
• Shorthand to write long binary numbers
3 3
4 4
5 5
6 6
7 7
8 8
9 9
A 10
B 11
C 12
D 13
E 14
F 15
5
Hexadecimal to Binary Conversion Bits, Bytes, Nibbles…
• Hexadecimal to binary conversion: • Bits 10010110

– Convert 4AF16 (also written 0x4AF) to binary most least
significant significant
bit bit
byte
• Bytes & Nibbles
10010110
• Hexadecimal to decimal conversion: nibble
– Convert 0x4AF to decimal
• Bytes CEBF9AD7
most least
significant significant
byte byte
Powers of Two Estimating Powers of Two
• 210 = 1 kilo ≈ 1000 (1024) • What is the value of 224?

• 220 = 1 mega ≈ 1 million (1,048,576)
• 230 = 1 giga ≈ 1 billion (1,073,741,824)
• How many values can a 32-bit variable

represent?
6
Addition Binary Addition Examples
• Decimal 11 carries • Add the following

1001
3734 4-bit binary
+ 0101
+ 5168 numbers
8902
• Binary 11 carries
1011
• Add the following 1011
+ 0011 4-bit binary + 0110
1110 numbers
Overflow Signed Binary Numbers
• Digital systems operate on a fixed number of • Sign/Magnitude Numbers

bits • Two’s Complement Numbers
• Addition overflows when the result is too big
to fit in the available number of bits
• See previous example of 11 + 6
7
Sign/Magnitude Numbers Sign/Magnitude Numbers
• 1 sign bit, N-1 magnitude bits • Problems:

• Sign bit is the most significant (left-most) bit – Addition doesn’t work, for example -6 + 6:
– Positive number: sign bit = 0
A : {a N −1 , a N −2 ," a2 , a1 , a0 } 1110
– Negative number: sign bit = 1
n −2
+ 0110
A = ( −1) an −1 ∑ ai 2i
i =0 10100 (wrong!)
• Example, 4-bit sign/mag representations of ± 6: – Two representations of 0 (± 0):
+6 = 1000
-6= 0000
• Range of an N-bit sign/magnitude number:
Two’s Complement Numbers Two’s Complement Numbers
• Don’t have same problems as sign/magnitude • Same as unsigned binary, but the most
numbers: significant bit (msb) has value of -2N-1
– Addition works n −2
– Single representation for 0 A = an −1 ( −2 n −1

) + ∑a 2 i
i
i =0
• Most positive 4-bit number:
• Most negative 4-bit number:
• The most significant bit still indicates the sign
(1 = negative, 0 = positive)
• Range of an N-bit two’s comp number:
8
“Taking the Two’s Complement” Two’s Complement Examples
• Flip the sign of a two’s complement number • Take the two’s complement of 610 = 01102
• Method:
1. Invert the bits
2. Add 1
• Example: Flip the sign of 310 = 00112
• What is the decimal value of 10012?
Two’s Complement Addition Increasing Bit Width
• Add 6 + (-6) using two’s complement • A value can be extended from N bits to M bits
numbers (where M > N) by using:
– Sign-extension
0110 – Zero-extension
+ 1010
• Add -2 + 3 using two’s complement

numbers
1110
+ 0011
9
Sign-Extension Number System Comparison
• Sign bit is copied into most significant bits. Number System Range
Unsigned [0, 2N-1]
• Number value remains the same.
Sign/Magnitude [-(2N-1-1), 2N-1-1]
Two’s Complement [-2N-1, 2N-1-1]
• Example 1:
– 4-bit representation of 3 = 0011 For example, 4-bit representation:
– 8-bit sign-extended value: 00000011 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
• Example 2: Unsigned 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
– 4-bit representation of -5 = 1011

1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Two's Complement
– 8-bit sign-extended value: 11111011
0000
1111 1110 1101 1100 1011 1010 1001
1000
0001 0010 0011 0100 0101 0110 0111 Sign/Magnitude
Logic Gates Single-Input Logic Gates
• Perform logic functions: NOT BUF

– inversion (NOT), AND, OR, NAND, NOR, etc.
A Y A Y
• Single-input:
– NOT gate, buffer Y=A Y=A
• Two-input: A Y A Y
– AND, OR, XOR, NAND, NOR, XNOR 0 1 0 0
1 0 1 1
• Multiple-input
10
Two-Input Logic Gates More Two-Input Logic Gates
XOR NAND NOR XNOR

AND OR A A A A
Y Y Y Y
A A B B B B
Y Y
B B
Y=A+B Y = AB Y=A+B Y=A+B
Y = AB Y=A+B A B Y A B Y A B Y A B Y
0 0 0 0 0 1 0 0 1 0 0
A B Y A B Y 0 1 1 0 1 1 0 1 0 0 1
0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0
0 1 1 1 1 0 1 1 0 1 1 0 1 1
0 1 0
1 0 0 1 0 1
1 1 1 1 1 1
Multiple-Input Logic Gates Logic Levels
NOR3 AND4 • Define discrete voltages to represent 1 and 0

A A
B Y B
C Y • For example, we could define:
C D
– 0 to be ground or 0 volts
Y = A+B+C Y = ABCD
– 1 to be VDD or 5 volts
A B C Y • But what if our gate produces, for example, 4.99
0 0 0
0 0 1 volts? Is that a 0 or a 1?
0 1 0
0 1 1
• What about 3.2 volts?
1 0 0
1
1
0
1
1
0
• Multi-input XOR: Odd parity
1 1 1
11
Logic Levels The Static Discipline
• Define a range of voltages to represent 1 and 0 • Given logically valid inputs, every circuit
• Define different ranges for outputs and inputs to element must produce logically valid outputs
allow for noise in the system
• Noise is anything that degrades the signal • Discipline ourselves to use limited ranges of
• For example, a gate (driver) could output a 5 voltages to represent discrete values
volt signal but, because of losses in the wire and
other noise, the signal could arrive at the
receiver with a degraded value, for example, 4.5
volts Noise
Driver Receiver
Copyright © 2007 Elsevier

5V 4.5 V 1-<61> Copyright © 2007 Elsevier 1-<62>
Logic Levels Noise Margins

Driver Receiver Driver Receiver
Output Characteristics Input Characteristics Output Characteristics Input Characteristics

VDD VDD
Logic High Logic High
Output Range Logic High Output Range Logic High
VO H Input Range VO H Input Range
NMH NMH
Forbidden VIH Forbidden VIH
Zone VIL Zone VIL
VO L NML VO L NML
Logic Low Logic Low
Logic Low Input Range Logic Low Input Range
Output Range Output Range
GND GND
NMH = VOH – VIH

Copyright © 2007 Elsevier 1-<63> Copyright © 2007 Elsevier NML = VIL – VOL 1-<64>
12
DC Transfer Characteristics DC Transfer Characteristics
Ideal Buffer: Real Buffer: A Y

V(Y) V(Y)
A Y
VOH VDD VDD

V(Y)
VOH Output Characteristics Input Characteristics
V DD VDD
V OH
VO H
NMH
Forbidden VIH
Zone VIL
Unity Gain
Points
VOL Slope = 1 Unity Gain NML
Points VO L
VOL 0 V(A) V(A) V OL Slope = 1
0
VDD / 2 VDD VIL VIH VDD
V(A)
VIL, VIH 0
V IL V IH V DD GND
NMH = NML = VDD/2 NMH , NML < VDD/2

VDD Scaling Logic Family Examples
• Chips in the 1970’s and 1980’s were designed

using VDD = 5 V Logic Family VDD VIL VIH VOL VOH
• As technology improved, VDD dropped
TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4
– Avoid frying tiny transistors
– Save power CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84
• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …
LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4
• Be careful connecting chips with different
supply voltages LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7
Chips operate because they contain magic smoke
Proof:
– if the magic smoke is let out, the chip stops working
13
Transistors Robert Noyce, 1927 - 1990
• Logic gates are usually built out of transistors • Nicknamed “Mayor of Silicon
• Transistor is a three-ported voltage-controlled switch Valley”
– Two of the ports are connected depending on the voltage • Cofounded Fairchild
on the third port
Semiconductor in 1957
– For example, in the switch below the two terminals (d and
s) are connected (ON) only when the third terminal (g) is 1 • Cofounded Intel in 1968
g=0 g=1
• Co-invented the integrated circuit
d d d
g OFF ON
s s s
Silicon MOS Transistors
• Transistors are built out of silicon, a semiconductor • Metal oxide silicon (MOS) transistors:
• Pure silicon is a poor conductor (no free charges) – Polysilicon (used to be metal) gate
• Doped silicon is a good conductor (free charges) – Oxide (silicon dioxide) insulator
– n-type (free negative charges, electrons) – Doped silicon
source gate drain
– p-type (free positive charges, holes) Polysilicon
Free electron Free hole SiO2
Si Si Si Si Si Si Si Si Si
- +
n n
+ -
Si Si Si Si As Si Si B Si
p substrate
Si Si Si Si Si Si Si Si Si
gate
Silicon Lattice n-Type p-Type source drain

nMOS
14
Transistors: nMOS Transistors: pMOS
• pMOS transistor is just the opposite

Gate = 0, so it is OFF Gate = 1, so it is ON – ON when Gate = 0
(no connection between (channel between – OFF when Gate = 1
source and drain) source and drain)
source gate drain
source drain source gate drain Polysilicon
gate VDD SiO2
GND
+++++++
------- p p
n n n n
channel n
p p substrate
substrate substrate
GND GND gate
source drain
Transistor Function Transistor Function
• nMOS transistors pass good 0’s, so connect source

g=0 g=1
to GND
d d d
OFF
• pMOS transistors pass good 1’s, so connect source
nMOS g ON
to VDD
s s s
pMOS
pull-up
s s s network
pMOS g OFF inputs

ON
d output
d d
nMOS
pull-down
network
15
CMOS Gates: NOT Gate CMOS Gates: NAND Gate
NOT VDD NAND

A P2 P1
A Y Y
B Y
P1
A Y A N1
Y=A Y = AB
N1 B N2
A Y A B Y
0 1 0 0 1
1 0
GND 0 1 1
1 0 1
1 1 0 A B P1 P2 N1 N2 Y
A P1 N1 Y 0 0
0 0 1
1 1 0
Copyright © 2007 Elsevier 1-<77> Copyright © 2007 Elsevier
1 1 1-<79>
CMOS Gate Structure NOR Gate
How do you build a three-input NAND gate?

pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
16
Other CMOS Gates Transmission Gates
How do you build a two-input AND gate? • nMOS pass 1’s poorly
EN
• pMOS pass 0’s poorly
• Transmission gate is a better switch A B
– passes both 0 and 1 well
• When EN = 1, the switch is ON: EN
– EN = 0 and A is connected to B
• When EN = 0, the switch is OFF:
– A is not connected to B
Pseudo-nMOS Gates Pseudo-nMOS Example
• nMOS gates replace the pull-up network with a Pseudo-nMOS NOR4

weak pMOS transistor that is always on
• The pMOS transistor is called weak because it
pulls the output HIGH only when the nMOS weak
network is not pulling it LOW
Y
weak
A B C D
Y
inputs nMOS
pull-down
network
17
Gordon Moore, 1929 - Moore’s Law
• Cofounded Intel in
1968 with Robert
Noyce.
• Moore’s Law: the
number of transistors
on a computer chip
doubles every year
(observed in 1965)
• “If the automobile had followed the same development cycle as
• Since 1975, transistor the computer, a Rolls-Royce would today cost $100, get one
counts have doubled million miles to the gallon, and explode once a year . . .”
every two years. – Robert Cringley
Power Consumption Dynamic Power Consumption
• Power = Energy consumed per unit time • Power to charge transistor gate capacitances
• Two types of power consumption: • The energy required to charge a capacitance, C, to
– Dynamic power consumption VDD is CVDD2
– Static power consumption • If the circuit is running at frequency f, and all
transistors switch (from 1 to 0 or vice versa) at
that frequency, the capacitor is charged f/2 times
per second (discharging from 1 to 0 is free).
• Thus, the total dynamic power consumption is:
Pdynamic = ½CVDD2f
18
Static Power Consumption Power Consumption Example
• Power consumed when no gates are switching • Estimate the power consumption of a wireless
• It is caused by the quiescent supply current, IDD, handheld computer
also called the leakage current – VDD = 1.2 V
• Thus, the total static power consumption is: – C = 20 nF
– f = 1 GHz
Pstatic = IDDVDD – IDD = 20 mA
19

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Chapter 1 :: From Zero to One Chapter 1 :: Topics

Background The Game Plan

Copyright © 2007 Elsevier 1-<3> Copyright © 2007 Elsevier 1-<4>

• Discipline they aren’t important Operating

• The Three –Y’s Architecture

focus of this course

Copyright © 2007 Elsevier 1-<5> Copyright © 2007 Elsevier 1-<6>

Discipline The Three -Y’s

• Intentionally restricting your design choices • Hierarchy

The Digital Abstraction The Analytical Engine

• Most physical variables are continuous, for • Designed by Charles

Copyright © 2007 Elsevier 1-<11> Copyright © 2007 Elsevier 1-<12>

Copyright © 2007 Elsevier 1-<13> Copyright © 2007 Elsevier 1-<14>

Number Systems Powers of Two

Copyright © 2007 Elsevier 1-<15> Copyright © 2007 Elsevier 1-<17>

• Decimal to binary conversion: • N-digit decimal number

• Decimal to binary conversion: • N-bit binary number

Hexadecimal Numbers Hexadecimal Numbers

• Hexadecimal to binary conversion: • Bits 10010110

Powers of Two Estimating Powers of Two

• 210 = 1 kilo ≈ 1000 (1024) • What is the value of 224?

• 230 = 1 giga ≈ 1 billion (1,073,741,824)

• How many values can a 32-bit variable

Copyright © 2007 Elsevier 1-<28> Copyright © 2007 Elsevier 1-<29>

• Decimal 11 carries • Add the following

Copyright © 2007 Elsevier 1-<31> Copyright © 2007 Elsevier 1-<32>

Overflow Signed Binary Numbers

• Digital systems operate on a fixed number of • Sign/Magnitude Numbers

Copyright © 2007 Elsevier 1-<34> Copyright © 2007 Elsevier 1-<35>

• 1 sign bit, N-1 magnitude bits • Problems:

Two’s Complement Numbers Two’s Complement Numbers

– Single representation for 0 A = an −1 ( −2 n −1

Copyright © 2007 Elsevier 1-<42> Copyright © 2007 Elsevier 1-<44>

Two’s Complement Addition Increasing Bit Width

• Add -2 + 3 using two’s complement

– 4-bit representation of -5 = 1011

Copyright © 2007 Elsevier 1-<49> Copyright © 2007 Elsevier 1-<51>

Logic Gates Single-Input Logic Gates

• Perform logic functions: NOT BUF

Copyright © 2007 Elsevier 1-<52> Copyright © 2007 Elsevier 1-<53>

XOR NAND NOR XNOR

Copyright © 2007 Elsevier 1-<55> Copyright © 2007 Elsevier 1-<57>

Multiple-Input Logic Gates Logic Levels

NOR3 AND4 • Define discrete voltages to represent 1 and 0

Copyright © 2007 Elsevier 1-<59> Copyright © 2007 Elsevier 1-<60>

Copyright © 2007 Elsevier

Logic Levels Noise Margins

Output Characteristics Input Characteristics Output Characteristics Input Characteristics

NMH = VOH – VIH

Ideal Buffer: Real Buffer: A Y

VOH VDD VDD

NMH = NML = VDD/2 NMH , NML < VDD/2

VDD Scaling Logic Family Examples

• Chips in the 1970’s and 1980’s were designed

Silicon MOS Transistors

Silicon Lattice n-Type p-Type source drain

• pMOS transistor is just the opposite

GND GND gate

Transistor Function Transistor Function

• nMOS transistors pass good 0’s, so connect source

pMOS g OFF inputs

Copyright © 2007 Elsevier 1-<75> Copyright © 2007 Elsevier 1-<76>