1.

Write verilog code to display the following

1
12
123
1234
12345

2. Write verilog code to display the following

A
BB
CCC
DDDD
EEEEE

3. What does `timescale 1 ns/ 1 ps signify in a verilog code?

4. Write the verilog code for.

A new flip flop is having behavior as described below .it has two inputs
x and y and when both are same they are 1,1 the flip flop is going to set
else flip flop resets if both inputs are different and they are 0,1 the flip
flop complements itself Otherwise it is to retain the last state

5. Write the verilog code for:

The DUT used is a simple ALU, limited to a single operation: the add
operation the inputs and outputs are represented in Figure 1.1
6. Write verilog code to generate random even and odd numbers
7. Write verilog code that has a clock and a reset as input. It has an
output that can be called clk_out. The clk_out is also a clock that has a
frequency one third the frequency of the input clock. It has synchronous
reset and if there if the reset is 1, the out clock resets to 0. Write test
bench to verify it.
8. Write verilog code for:
Car parking system there is a sensor which is activated to detect a
vehicle coming. Once the sensor is triggered, a password is requested to
open the gate. If the entered password is correct, the gate would open to
let the vehicle get in. Otherwise, the gate is still locked. If the current car
is getting in the car park being detected by the exit sensor and another
car comes, the door will be locked and requires the coming car to enter
passwords.
Solution:
http://www.fpga4student.com/2016/11/verilog-code-for-parking-
systemusing.
Html
9. Verilog code for a simple timer which generates a continuous stream
of interrupt pulses at intervals determined by a parameter abd each pulse
should last 4 clock cycles
module irq_gen
(
input clk, reset,
output irq
);
parameter INTERVAL = 'd80,
IRQ_LENGTH = 'd4;
localparam INT_W = log2(INTERVAL);
reg [INT_W-1:0] cnt_int;
reg [IRQ_LENGTH-1:0] irq_reg;
always @(posedge clk or posedge reset)
if ( reset )
cnt_int <= {INT_W{1'b0}};
else
if ( cnt_int == INTERVAL ) cnt_int <= 'h0;
else cnt_int <= cnt_int + 1'b1;
always @(posedge clk)
if ( cnt_int == INTERVAL ) irq_reg <= 'h1;
else irq_reg <= irq_reg << 1;
assign irq = |irq_reg;
//////////// log2 function //////////////
function integer log2; //
input [31:0] value; //
for (log2=0; value>0; log2=log2+1) //
value = value>>1; //
endfunction //
////////////////////////
Endmodule
10. Difference between `define and parameter.