Quiz Compilation

Problem 1: Use D-Type flip flops to design a 4 bit counter (A, B, C, D) with the repeated binary sequence 0, 1, 2, 4, 8. Determine the
following. (SET B)
(a) The circuit’s state table. Present state entries should be in ascending order.
Present State Next State FF Inputs
₰ m
A B C D A B C D DA DB DC DD
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 0 2 0 1 0 0
Excitation Table
0 0 1 1 3 x x x x
for D Flip Flop
0 1 0 0 1 0 0 0 4 1 0 0 0
Q Q(t) Output
0 1 0 1 5 x x x x
0 0 0
0 1 1 0 6 x x x x
0 1 1
0 1 1 1 7 x x x x
1 0 0
1 0 0 0 0 0 0 0 8 0 0 0 0
1 1 1
1 0 0 1 9 x x x x
1 0 1 0 10 x x x x
1 0 1 1 11 x x x x
1 1 0 0 12 x x x x
1 1 0 1 13 x x x x
1 1 1 0 14 x x x x
1 1 1 1 15 x x x x

(b) The flips flop’s input equation in SOP. Show necessary maps and most economical grouping of minterms
For DA: For DB:
CD CD 00 01 11 10
00 01 11 10 AB
AB
00 0 0 x 0 00 0 0 x 1
01 1 x x x 01 0 x x x
11 x x x x 11 x x x x
10 x x x x 10 0 x x x

DA = B DB = C
For DC: For DD:
CD CD
00 01 11 10 00 01 11 10
AB AB
00 0 1 x 0 00 1 0 x 0
01 0 x x x 01 0 x x x
11 x x x x 11 x x x x
10 0 x x x 10 0 x x x

DC = D DD = A’B’C’D’

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 1

Problem 2: At time t=0, a low signal was momentarily sent over the reset line before fixing the signal to logic 1. Using the figure below,
determine the ff.

Register C

C
C3 C2 C1 C0
Reset
Clear Register C
S0
S1

Register A

C
A3 A2 A1 A0 Full Adder
Reset FA
Clear Register A
Input Signal A S0
S1
1111 1010 X
S

Clk Y
Register B
C
Z

C
B3 B2 B1 B0
Reset
Clear Register B Carry
S0
S1
0000 1011
D Q

Reset

Note: A B and C are most significant bits

Note: Justify your answer by showing the truth table above circuit. Use the table format shown.
t A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 X Y Z S C D Q
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
4 1 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0
5 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 0 1 1 0
6 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1
7 1 1 1 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0
8 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 2

(a) Value of SCDQ after the arrival of the 5th initiating clock
0110
(b) Value of XYZ after the arrival of the 7th initiating clock
110
(c) Content of Register C (C3 C2 C1 C0) after the arrival of the 6th initiating clock
0100
(d) Value of XYZ after the arrival of the 6th initiating clock
001
(e) Value of SCDQ after the arrival of the 8th initiating clock
0111
(f) Content of Register C after the arrival of the 8th initiating clock
0101

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 3

Problem 3: A sequential circuit has three D flip-flops A, B, and C (whose state format is in the form of ABC) and the input X. The circuit is
describe by the following input equations: (SET B)
DA = (BC’+B’C) X + (BC+B’C’) X’ DB = A DC = B
(a) The circuit’s state table. Present state entries should be in ascending order.
Present State Input Next State
A B C X A B C
0 0 0 0 1 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 1
1 0 0 0 1 1 0
1 0 0 1 0 1 0
1 0 1 0 0 1 0
1 0 1 1 1 1 0
1 1 0 0 0 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 0 1 1

(b) Draw the state diagram for X = 0 and for X = 1

For X = 0: For X = 1:
1
0
000 100
000 100
0
1
001 101 0
0
001 1 101
0 0
010 110 1 1
1
0 010 110

011 111
1
011 1 111
0

Note: Draw a separate state diagram for (b) and (c)

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 4

Problem 4: A sequential circuit has three D flip flops A, B, and C and one input X. The circuit’s behaviour is described by the given state
diagram. (SET B)
0
0
1

1 0 1
001 010 011 100

1 1

0 0
001

(a) Show the circuit’s table. Treat unused combinations (if any) as don’t care minterms. Show the present state section entries in
ascending order
Present State Input Next State
A B C X A B C
0 0 0 0 x x x
0 0 0 1 x x x
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 1 0 0
1 0 0 0 1 0 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 1 0 0
1 1 0 0 x x x
1 1 0 1 x x x
1 1 1 0 x x x
1 1 1 1 x x x

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 5

(b) Derive the flip flop input equations for DA, DB, DC in SOP
For DA: For DB:
CX CX 00 01 11 10
00 01 11 10 AB
AB
00 x x 0 0 00 x x 1 0
01 0 1 1 0 01 1 0 0 0
11 x x x x 11 x x x x
10 1 1 1 0 10 0 0 0 0

DA = BX + AC’ + AX DB = A’B’X + A’C’X’

For DC:
CX
00 01 11 10
AB
00 x x 0 1
01 1 0 0 1
11 x x x x
10 1 0 0 1

DC = X’

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 6

Problem 5: A J-N Flip-Flop has 2 inputs J and N. Input J behaves like J input of a JK Flip-Flop and Input N behaves like the complement of
the K input of a JK Flip-Flop (that is N=K’). Show the characteristic table of the flip-flop by using table format below
Solution:
For JK Flip Flop
J K Q Remarks
0 0 Q(t) Retain last state
0 1 0 Reset
1 0 1 Set
1 1 Q(t)’ Toggle

J K’ Q Remarks
0 1 0 Reset
0 0 Q(t) Retain last state
1 1 Q(t)’ Toggle
1 0 1 Set

J = J input of a JK Flip-Flop
N = K’ input of a JK flip-flop
J N Q Remarks
0 0 0 Reset
0 1 Q(t) Retain last state
1 0 Q’(t) Toggle
1 1 1 Set

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 7

Problem 6: A 5-bit positive edge-triggered ripple counter with an initial state of 10101 uses J-K Flip-Flops in monitoring a certain
sequence of activity. The inputs to the flip-flops are always high while the output of one flip-flop serves as the clock signal to the next-
higher-order flip-flop. The output signal follows the format ….Q2, Q1, Q0 where Q0 represents the least significant bit in the output signal
of the circuit. The least significant flip-flop receives the master clock in its clock port. Determine the state of the circuit (in its equivalent
decimal number) after the arrival of the following (a) 20th initiating clock (b) 25th (c) 30th (d) 35th (e) 40th (f) 45th
Solution:
Q4 Q3 Q2 Q1 Q0 Dec. Q4 Q3 Q2 Q1 Q0 Dec.
0 1 0 1 0 1 21 23 1 1 1 1 0 30
1 1 0 1 0 0 20 24 1 1 1 0 1 29
2 1 0 0 1 1 19 25 1 1 1 0 0 28
3 1 0 0 1 0 18 26 1 1 0 1 1 27
4 1 0 0 0 1 17 27 1 1 0 1 0 26
5 1 0 0 0 0 16 28 1 1 0 0 1 25
6 0 1 1 1 1 15 29 1 1 0 0 0 24
7 0 1 1 1 0 14 30 1 0 1 1 1 23
8 0 1 1 0 1 13 31 1 0 1 1 0 22
9 0 1 1 0 0 12 32 1 0 1 0 1 21
10 0 1 0 1 1 11 33 1 0 1 0 0 20
11 0 1 0 1 0 10 34 1 0 0 1 1 19
12 0 1 0 0 1 9 35 1 0 0 1 0 18
13 0 1 0 0 0 8 36 1 0 0 0 1 17
14 0 0 1 1 1 7 37 1 0 0 0 0 16
15 0 0 1 1 0 6 38 0 1 1 1 1 15
16 0 0 1 0 1 5 39 0 1 1 1 0 14
17 0 0 1 0 0 4 40 0 1 1 0 1 13
18 0 0 0 1 1 3 41 0 1 1 0 0 12
19 0 0 0 1 0 2 42 0 1 0 1 1 11
20 0 0 0 0 1 1 43 0 1 0 1 0 10
21 0 0 0 0 0 0 44 0 1 0 0 1 9
22 1 1 1 1 1 31 45 0 1 0 0 0 8
th
(a) 20 initiating clock = 00001 = 110
(b) 25th initiating clock = 11100 = 2810
(c) 30th initiating clock = 10111 = 2310
(d) 35th initiating clock = 10010 = 1810
(e) 40th initiating clock = 01101 = 1310
(f) 45th initiating clock = 01000 = 810

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 8

Problem 7: A clocked sequential circuit has one D flip-flop with an output of Q. This flip-flop is connected to a full-adder with inputs X, Y,
Z (where Z is the most significant bit and Y is the least significant bit) and output S and C. The C output series as input to the D flip-flop
while the flip-flop’s Q output series as the Z input to the full adder circuit. Determine the following:
(a) State table of the circuit using the prescribed table below

FA
X S
Y
C
Z
D Q

Clk

Present State Inputs Next State Output

m
Z X Y Q (t+1) C S
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 2
0 1 1 1 0 3
1 0 0 0 1 4
1 0 1 1 0 5
1 1 0 1 0 6
1 1 1 1 1 7

(b) The input equation for the D Flip-Flop

D is shorted to C
For D:
XY
00 01 11 10
Z
0 0 0 1 0
1 0 1 1 1

D = XY+XZ+YZ

(c) The equation for the output signal S

For S:
XY
00 01 11 10
Z
0 0 1 0 1
1 1 0 1 0

D = X’Y’Z+X’YZ’+XYZ+XY’Z’

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 9

Problem 8: A ring counter is a shift register that consists of flip-flop with the serial output connected to the serial input of the
neighbouring flip flop. Beginning in state 10….0, how many states are there in the count sequence of (a) 4 –bit counter? Draw the
circuit (b) an 8-bit counter? Draw the circuit. Give a short justification of your answer
Solution:
(a) 4-bit counter

D0 Q0 D1 Q1 D2 Q2 D3 Q3

Clk

State Q0 Q1 Q2 Q3
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
The state is repeated, therefore
No. of State = 4 states
(b) 8-bit counter

D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7

Clk

State Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 1 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0
3 0 0 0 1 0 0 0 0
4 0 0 0 0 1 0 0 0
5 0 0 0 0 0 1 0 0
6 0 0 0 0 0 0 1 0
7 0 0 0 0 0 0 0 1
8 1 0 0 0 0 0 0 0
The state is repeated, therefore
No. of State = 8 states

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 10

Problem 9: Design a sequential circuit with two JK flip flops A & B and two inputs E & K. If E=0, the circuit remains in the same state
regardless the value of X. When E=1 and X=1, the circuit goes through the state transitions from 00 to 01 to 10 to 11, back to 00 and
then repeats. When E=1 and X=0, the circuit goes to the state transitions 00 to 11 to 10 to 01, back to 00, and then repeats. Determine
the following
(a) The state table for the above circuit
Present State Inputs Next State Flip Flops Inputs
m
A B E X A B JA KA JB KB
J-K Flip Flop Excitation Table
0 0 0 0 0 0 0 0 x 0 x
Present State Next State Inputs
1 0 0 0 1 0 0 0 x 0 x
Q(t) Q(t+1) J K
2 0 0 1 0 1 1 1 x 1 x
0 0 0 x
3 0 0 1 1 0 1 0 x 1 x
0 1 1 x
4 0 1 0 0 0 1 0 x x 0
1 0 x 1
5 0 1 0 1 0 1 0 x x 0
1 1 x 0
6 0 1 1 0 0 0 0 x x 1
7 0 1 1 1 1 0 1 x x 1
8 1 0 0 0 1 0 x 0 0 x
9 1 0 0 1 1 0 x 0 0 x
10 1 0 1 0 0 1 x 1 1 x
11 1 0 1 1 1 1 x 0 1 x
12 1 1 0 0 1 1 x 0 x 0
13 1 1 0 1 1 1 x 0 x 0
14 1 1 1 0 1 0 x 0 x 1
15 1 1 1 1 0 0 x 1 x 1

(b) The input equation for JA, KA, JB & KB

For JA: For KA:
EX EX 00 01 11 10
00 01 11 10 AB
AB
00 0 0 0 1 00 x x x x
01 0 0 1 0 01 x x x x
11 x x x x 11 0 0 1 0
10 x x x x 10 0 0 0 1

JA = BEX + B’EX’ KA = BEX + B’EX’

For JB: For KB:
EX EX
00 01 11 10 00 01 11 10
AB AB
00 0 0 1 1 00 x x x x
01 x x x x 01 0 0 1 1
11 x x x x 11 0 0 1 1
10 0 0 1 1 10 x x x x

JA = E KB = E

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 11

Problem 10: Design a BCD counter that uses four (4) T flip flops using the given table format below, the output signal Y=1 only during
the counter transition from 1001 to 0000, otherwise, Y=0, determine the following
(a) The state table for the above circuit
Present State Next State Output Flip-Flop Inputs
m
Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1
0 0 0 0 0 0 0 1 0 0 0 0 0 1
0 0 0 1 0 0 1 0 0 1 0 0 1 1 T Flip Flop Excitation Table
0 0 1 0 0 0 1 1 0 2 0 0 0 1 Present State Next State Inputs
0 0 1 1 0 1 0 0 0 3 0 1 1 1 Q(t) Q(t+1) T
0 1 0 0 0 1 0 1 0 4 0 0 0 1 0 0 0
0 1 0 1 0 1 1 0 0 5 0 0 1 1 0 1 1
0 1 1 0 0 1 1 1 0 6 0 0 0 1 1 0 1
0 1 1 1 1 0 0 0 0 7 1 1 1 1 1 1 0
1 0 0 0 1 0 0 1 0 8 0 0 0 1
1 0 0 1 0 0 0 0 1 9 1 0 0 1
1 0 1 0 x x x x 0 10 x x x x
1 0 1 1 x x x x 0 11 x x x x
1 1 0 0 x x x x 0 12 x x x x
1 1 0 1 x x x x 0 13 x x x x
1 1 1 0 x x x x 0 14 x x x x
1 1 1 1 x x x x 0 15 x x x x

(b) The input equations for TQ8, TQ4, TQ2, TQ1

For TQ8: For TQ4:
Q2Q 1 Q2 Q1 00 01 11 10
00 01 11 10 Q8 Q4
Q8 Q 4
00 0 0 0 0 00 0 0 1 0
01 0 0 1 0 01 0 0 1 0
11 x x x x 11 x x x x
10 0 1 x x 10 0 0 x x

TQ8 = Q8Q1 + Q4Q2Q1 TQ4 = Q2Q1

For TQ2: For TQ1:

Q2Q 1 Q2 Q 1
00 01 11 10 00 01 11 10
Q8 Q 4 Q8 Q4
00 0 1 1 0 00 1 1 1 1
01 0 1 1 0 01 1 1 1 1
11 x x x x 11 x x x x
10 0 0 x x 10 1 1 x x

TQ2 = Q’8Q1 TQ1 = 1

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 12

Problem 11: Given the 4 JK Flip Flop connected as T-Flip Flop Circuit’ Diagram, the initial state of the circuit at t=0 is 0001 (Q3Q2Q1Q0)
Determine the following

J3 K3 J2 K2 J1 K1 J0 K0

Clk

Q3 Q2 Q1 Q0

a. Show the content of the circuit for the next 20 clock ticks (initiating clock). Follow the given table below in showing your
answer
Clock (t) Q3 Q2 Q1 Q0
0 0 0 0 1
1 0 0 0 0
2 1 1 1 1
3 1 1 1 0
4 1 1 0 1
5 1 1 0 0
6 1 0 1 1
7 1 0 1 0
8 1 0 0 1
9 1 0 0 0
10 0 1 1 1
11 0 1 1 0
12 0 1 0 1
13 0 1 0 0
14 0 0 1 1
15 0 0 1 0
16 0 0 0 1
17 0 0 0 0
18 1 1 1 1
19 1 1 1 0
20 1 1 0 1

b. How many states can the circuit assume? Must conform with your truth table
The Circuit can assume 16 states.

c. What does the circuit do? Be specific with your answer

The circuits subtracts 1 bit to the present state and yields the difference but will yield 1111 once one is subtracted to 0000.

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 4 COMPILATION PAGE 13