Programmable Logic

Adapted from slides by R. H. Katz

PALs and PLAs

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)

"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs
 PALs and PLAs
Key to Success: Shared Product Terms

Equations
F0 = A + B' C'
Example: F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A

Input Side:
1 = asserted in term
Personality Matrix
0 = negated in term
Product Inputs Outputs - = does not participate
term A B C F0 F1 F2 F3
Output Side:
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1 Reuse 1 = term connected to output
of 0 = no connection to output
AC 1 - 0 0 1 0 0
terms
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1
PALs and PLAs
Example Continued

All possible connections are available

before programming
 PALs and PLAs
Example Continued

Unwanted connections are "blown"

Note: some array structures

work by making connections
rather than breaking them
PALs and PLAs
Alternative representation for high fan-in structures

Short-hand notation
so we don't have to
draw all the wires!

Notation for implementing

F0 = A B + A' B'
F1 = C D' + C' D
PALs and PLAs
Design Example

Multiple functions of A, B, C ABC

A
F1 = A B C
B

F2 = A + B + C C

A
F3 = A B C
B
F4 = A + B + C C

ABC
F5 = A xor B xor C
ABC
F6 = A xnor B xnor C ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6
PALs and PLAs
What is the difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?

PAL concept — implemented by Monolithic Memories, Inc. (AMD)

constrained topology of the OR Array

A given column of the OR array

has access to only a subset of
the possible product terms

PLA concept — generalized topologies in AND and OR planes

 PALs and PLAs
Design Example: BCD to Gray Code Converter
Truth Table K-maps
A B C D W X Y Z A A
0 0 0 0 0 0 0 0 AB AB
0 0 0 1 0 0 0 1 CD 00 01 11 10 CD 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
01 0 1 X 1 01 0 1 X 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0 D D
0 1 1 1 1 0 1 1 11 0 1 X X 11 0 0 X X
1 0 0 0 1 0 0 1 C C
1 0 0 1 1 0 0 0 10 0 1 X X 10 0 0 X X
1 0 1 0 X X X X
1 0 1 1 X X X X B B
1 1 0 0 X X X X
K-map for W K-map for X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 1 X 0 00 0 0 X 1

01 0 1 X 0 01 1 0 X 0
Minimized Functions: D D
11 1 1 X X 11 0 1 X X
C C
W=A+BD+BC 10 1 1 X X 10 1 0 X X
X = B C'
Y=B+C B B
Z = A'B'C'D + B C D + A D' + B' C D' K-map for Y K-map for Z
PALs and PLAs
Programmed PAL:

ABCD

4 product terms per each OR gate

PALs and PLAs
Code Converter Discrete Gate Implementation

\A \A
A 1
\B
4
\C
B D
2 3 W
D
B
C 3
B 2
C D
4 4 Z
A
5
B D 1 \D
22 1 X \B
C 1
C 3
\C \D

2 1: 7404 hex inverters

Y
B 1 2,5: 7400 quad 2-input NAND
\B 3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

4 SSI Packages vs. 1 PLA/PAL Package!

 PALs and PLAs
Another Example: Magnitude Comparator

A A
AB AB
ABCD
CD 00 01 11 10 CD 00 01 11 10

00 1 0 0 0 00 0 1 1 1 ABCD

01 0 1 0 0 01 1 0 1 1 ABCD
D D
11 0 0 1 0 11 1 1 0 1 ABCD
C C
10 0 0 0 1 10 1 1 1 0 AC

B B AC
K-map for EQ K-map for NE
BD

A A BD
AB AB
CD 00 01 11 10 CD 00 01 11 10
ABD
00 0 0 0 0 00 0 1 1 1
BCD
01 1 0 0 0 01 0 0 1 1
D D ABC
11 1 1 0 1 11 0 0 0 0
C C BCD
10 1 1 0 0 10 0 0 1 0

B B
K-map for LT K-map for GT
EQ NE LT GT
PALs and PLAs

• Standard PAL Numbering

PAL10L8

ten inputs eight outputs

active-low output

• PAL16L8 I1 O1

I2 I/O1

I3
I/O2
I4

I5 I/O3
Programmable
AND array
I6 I/O4
I7
I/O5
I8

I9 I/O6

I10 O2
 PALs and PLAs
• Advanced PAL Architectures
Programmable Output Polarity/XOR PALs
CLK OE

Buried Registers: decouple

DQ FF from the output pin
Q

Advantage of XOR PALs: Parity and Arithmetic Operations

ABCD
ABCD
A⊕B⊕C⊕ D AB
ABCD A⊕B⊕C⊕ D
ABCD AB
ABCD
CD
ABCD
CD
ABCD
ABCD
Generic Array Logic (GAL)

• First introduced by Lattice Semiconductor

• A reprogrammable AND array, a fixed OR array, reprogrammable
output logic
• Electrically Erasable PROM (EEPROM, E2PROM) cells are used
(EEPLD)
• Similar to PAL except the Output Logic MacroCells (OLMCs) which
provide more flexibility

input 1 OLMC
input 2 ... input/output 1

. E2CMOS
. ... OLMC input/output 2
programmable
. AND array .
.
.

... OLMC input/output 3

input n
Generic Array Logic (GAL)

• Output Logic MacroCell (OLMC)

– can be configured either for a combinational output or for a registered
output

from
programmable 1-of-4
array multiplexer I/O
flip-flop

S1 S0

to 1-of-2
programmable multiplexer
array

OLMC
S1

s1 s0 = 00 --> registered mode with active-LOW output

= 01 --> registered mode with active-HIGH output
= 10 --> combinational mode with active-LOW output
= 11 --> combinational mode with active-HIGH output
Generic Array Logic (GAL)

• Standard GAL Numbering

GAL16V8

sixteen inputs eight outputs

variable output configuration

• GAL16V8
– can emulate a number of PALs
OE

MUX
VCC

XOR

MUX

combinational configuration
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"

Width of row is called bit-width or wordsize

Address is input, selected word is output

+5V +5V +5V +5V

n
2 -1

i Word Line 0011

Dec
j Word Line 1010

Bit Lines
0 n-1
Address

Internal Organization
 Read-Only Memories
Example: Combination Logic Implementation

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

Address A B C F0 F1 F2 F3 Word Contents
0 0 0 0 0 1 0
0 0 1 1 1 1 0
0 1 0 0 1 0 0
ROM 0 1 1 0 0 0 1
8 w ords =
by 1 0 0 1 0 1 1
4 bits 1 0 1 1 0 0 0
1 1 0 0 0 0 1
1 1 1 0 1 0 0

A B C F0 F1 F2 F3
address outputs
 Read-Only Memories

Not Memory array

Notunlike
unlikeaaPLA
PLA
structure
structure withaa
with
fully
fullydecoded
decoded Decoder
2n word 2n words by
AND
ANDarray!
array! lines m bits

n address m output
lines lines

ROM vs. PLA:

ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when

(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR planes

Read-Only Memories

2764 EPROM 2764 2764

8K x 8 +
VPP
PGM +
VPP
PGM
A12 A12
A11 A11
2764 A10 O7 A10 O7
A9 O6 A9 O6
VPP A8 O5 A8 O5
A7 O4 A7 O4
PGM A6 O3 A6 O3
A12 A5 O2 A5 O2
A4 O1 A4 O1
A11 A3 O0 A3 O0
A2 A2
A10 O7 A1 A1
A0 A0
A9 O6 CS U3 CS U2
A8 OE OE
O5
A7 O4
A13
A6 /OE
O3 A12:A0
A5 O2 D15:D8
A4 D7:D0
O1 2764 2764
A3 O0 + VPP
+
VPP
PGM PGM
A2 A12 A12
A11 A11
A1 A10 O7 A10
A9 O6 A9 O7
A0 A8 O5 A8 O6
CS A7 O4 A7 O5
A6 O3 A6 O4
OE A5 O2 A5 O3
A4 O1 A4 O2
A3 O0 A3 O1
A2 A2 O0
A1 A1
A0 A0
CS U1 CS U0
OE OE
16K x 16
Subsystem