Design of a High Speed 6-bit Successive

Approximate Register Analog to Digital Converter

(SAR ADC) using 45nm CMOS Technology
Agcaoili, Kimberly D.
ECE/ICE/MexE Department
Junior Institute of Electronics
Engineer of the Philippines
Batangas City, Philippines
kimberlydagcaoili@gmail.com
Castillo, Sancho Mico B.
ECE/ICE/MexE Department
Junior Institute of Electronics
Engineer of the Philippines
Batangas City, Philippines
mico_castillo91@yahoo.com
Tugbo, Jed Anthony F.
ECE/ICE/MexE Department
Junior Institute of Electronics
Engineer of the Philippines
Batangas City, Philippines
jedanthony08@gmail.com

Track & Hold block. To implement the binary search

Abstract – The purpose of this study is to design a high speed 6-bit
successive approximate register analog to digital converter (SAR
ADC) using 45nm CMOS technology and to test the functionality
of each building blocks of the SAR ADC as well as to simulate each
part under different conditions and integrate it properly with one
another.
Keywords - SAR ADC, Comparator, DAC, SAR logic, Track &
Hold
I. INTRODUCTION
Comparing Successive Approximation Register, Flash,
Folding and Interpolating and Sigma-Delta ADCs, the SAR
ADC seems allowing the lowest-power consumption. This
architecture has the advantage to be very simple; it implements
the binary search algorithm. Power dissipation scales with the
sample rate, unlike flash ADCs that usually have constant
power dissipation versus sample rate. This is especially useful
in low-power applications. Moreover SAR ADC does not
contain an operational amplifier; that are generally power-
hungry, it needs just one comparator that consume much less
power than operational amplifiers.
SAR ADC has four mains building blocks namely the
Sample-and-Hold Stage (S/H), Digital-to-Analog Converter
(DAC), Comparator and Successive Approximation Register
(SAR). Below shows the topology used by the researchers for
this study.
Figure 1. Simplified N-bit SAR ADC Architecture
The basic functionality of a SAR ADC is very simple
(Figure 2). The analog input voltage VIN is sampled by the
algorithm, the N-bit register is first set to midscale setting the
MSB to '1' and all other bits to ‘0’. This forces the DAC output,
VDAC, to be half of the reference voltage, VREF/2. VIN is
then compared with VDAC, if VIN is greater than VDAC, the
comparator output is logic 1 and the MSB of the N-bit register
remains at 1. Conversely, if VIN is less than VDAC, the
comparator output is logic 0 and the MSB of the register is
cleared to 0. The SAR control logic then moves to the next bit
down, forces that bit high, and does another comparison. The
sequence continues all the way down to the LSB. Once this is
done, the conversion is completed, and the N-bit digital word is
available in the register.
Figure 2. Operation of SAR
SAR ADC works with two different clock
frequencies. The first clock is an input of the chip, and its
frequency, fint, is the one at which the internal circuit works.
The second clock drives the Sample and Hold in order to
sample the analog input value. This second clock is internally
created by a frequency divider; it should be X times slower the
first one, where X is the number of comparison periods needed
from the control logic to complete a conversion. The
conversion rate is determined by this second clock, an N-bit
SAR ADC will require minimum N periods and will not be
ready for the next conversion until the current one is complete.
The logic control block of the ADC has two important
aims. It sets the switches in function of the current state of the
conversion and the output of the comparator; moreover, it
computes and stores the digital converted value to be given as B. Comparator
output at the end of the conversion.

II. REVIEW OF RELATED LITERATURE

A. Track & Hold

The function of a track-and-hold circuit is to buffer its
input signal accurately during track mode providing at its
output a signal which is linearly proportional to the input, and
to maintain a constant output level during hold mode equal to
the T/H output value at the instant it was strobed from track to Figure 4. Double-tail Dual-rail Dynamic Latched Comparator
hold by an external clock signal. Fig. 3.2 shows the waveforms
of a practical sample-and-hold circuit. This double-tail dual-rail dynamic latched comparator
Several parameters describe the speed and accuracy with eliminated the weakened Ni nodes by inserting an inverter
which this operation is performed. The track mode is the state between input and output stages. Due to inverter, weak signal of
when the T/H output follows the T/H input. The hold mode Ni node is regenerated and fed to the output stage. This
refers to the period when the T/H output is maintained at a comparator shows faster operation and lesser power dissipation.
constant value. Track-to-hold transition is the instant when the
circuit switches from the track mode to the hold mode and the
hold-to-track transition refers to the switch from hold mode
back to track mode. The time between successive track-to-hold
transitions is the sample period that’s reciprocal is the sample
rate.
The circuit implementation of the Sample & Hold circuit
is given in the Figure 3. The simple sample and hold circuit
suffers with the problem of substantial charge injection, which
is encounter by adding a dummy device 2 M with half the width
of the sampling switch 1 M and is driven with complementary
clock. Figure 5. Dynamic Differential Input Gain-Stage

Figure 3. Schematic of Sample & Hold Circuit Figure 6. Output Latch-Stage

In the circuit when M1 turns off and injects charge onto

holding capacitor CH, M2 turns on and absorbs charge from the
capacitor. Hence it is exactly half of the M1 channel charge is
injected onto CH, then complete cancellation occurs and the
held voltage on CH is not corrupted by charge injection. A pair
of the same circuit can be used in differential fashion for
Differential SAR ADC.

Figure 7. Conditioning Circuit

 During reset phase (clk= 0V), PMOS transistor M4 and M5
turn on and they charge Ni node voltages to VDD. And Hence
NMOS transistors M18 and M19 turns on and discharges Ni’
nodes voltages to GND. Then M12, M15 and PMOS transistors VDAC is then compared with zero, if VDAC<0 it means
of differential amplifier blocks M13 and M14 turns on, NMOS that Vin>Vref/2, hence the MSB is set to 1. Otherwise, if
transistors of differential amplifier block M8, M9 and M6, M7 VDAC>0 , Vin<Vref/2 , hence the MSB is set to 0. In this case
turns off. The out nodes are charges to VDD. the largest capacitor is reconnected to ground. The conversion
During evaluation phase (clk= VDD), the Ni node proceeds in this manner until all the bits have been determined.
capacitances are discharged from VDD to GND in a rate which From the energy point of view, we consider:
is proportional to the input voltages. At a certain voltage of Ni • The energy to charge Vin on Ctot= 256⋅C0. that is:
nodes, the inverter pairs M16/M18 and M17/M19 invert the Ni
node signal into a regenerated signal. These regenerated signals
turn PMOS transistors M12, M13, M14, and M15 off. And
eventually M6, and M7 turns on. Hence the back-to-back • The sum of the energy dissipated at each step, for step x:
differential pair again regenerates the Ni’ node signals and
because of M6 and M7 being on, the output latch stage converts
the small voltage difference transmitted from Ni’ node into a full Where
scale digital level output.
Specification:
𝑉𝑑𝑑 = 1𝑉
1𝑉
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 6 = 15.625mV
2
2𝑓𝐹 ≥ 𝑐𝑔𝑠 And

C. Digital to Analog Converter (DAC)

MATLAB calculations show that the energy consumption

for our particular case is about 31pJ.

Figure 8. Single Ended Binary Weighted Switched Capacitor Array DAC
Figure 8 is an array of binary weighted capacitors plus
one additional capacitor of weight corresponding to the last
significant bit (LSB), and switches that connect the capacitor
bottom plates to three different voltages: VDD, Vref and
ground. For a n-bit DAC, the value of the capacitors are,
D. SAR Logic
The implemented SAR Logic and its timing diagram are
shown in Figures 9 and 10 respectively. The SAR Logic is
implemented using shift registers (SR0–SR7), latches (LA0–
LA5) and OR gates (OR1–OR5). The shift registers and latches
are custom designed for faster operation using conventional
C2MOS Logic circuits [1]. The outputs of the OR gates (S1–
S5) control the bit cycling sequences. The latches clocked by
shift registers store the bit decisions that are being resolved
during respective bit cycling periods in the outputs (B0–B5).

The conversion is performed in three operation modes. In

the first, the “sample mode”, the top plate is connected to
ground and the bottom plates to the input voltage Vin. In the
“hold mode”, the top grounding switch is then opened, and the
bottom plates are connected to ground. Since the charge on the
top plate is conserved, its potential goes to -Vin. The
“redistribution mode”, begins testing the value of the most
significant bit (MSB). This is done by raising the bottom plate
of the largest capacitor to the reference voltage Vref. Now, the Figure 9. SAR Logic Schematic Diagram
circuit acts as a voltage divider between two equal
capacitances, so the voltage at the output of the DAC is:
 Table 1. Description of Various States of the SAR Logic

Figure 10. SAR Logic Timing Diagram

During the start of bit cycling, all bit cycling controls (S1–
S5) go high. On completion of the MSB bit cycling, S5 goes
low while (S1–S4) still remain high, and along with the
resolved MSB bit trigger the next bit cycling. After the
completion of next MSB bit cycling, S4 goes low and this
process repeats until entire bit decisions are made.
The SAR logic for the ADC is a state machine which takes
the Clock signal as input. The clock signal is divided by 8 to
generate the clock required for Sample & Hold circuit. 6 clock
cycles are required for one complete conversion. Two
additional clock cycles are for Start of Conversion and End of
Conversion. 1. The Start of Conversion (SOC) – 1st Clock
cycle is used to reset all the registers in the logic block. 2. The
2nd Clock cycle – Comparator performs comparison between III. CIRCUIT DESIGNS AND SIMULATIONS
Input data and reference voltage and generates a 1 or 0. The
data is stored in the registers and applied to the DAC. The DAC Below shows the circuit design with its schematic and
sets the reference voltage for the next conversion cycle. The symbols, and the following simulations by each building blocks
same process is repeated for 2nd to 7th clock cycle to complete namely the Track & Hold, Comparator, DAC and SAR Logic
conversion process. 3. The End of Conversion (EOC) – 8th and the integration of each part.
Clock cycle latches the output data to the data bus.
The SAR logic operated over an 8 clock cycle period, with A. Track & Hold
2 cycles allotted for SOC & EOC and 6 clock cycles for digital
data. A 6 bit conversion scheme is used to divide the entire The simple sample and hold circuit was done by adding a
voltage head room of 0 to 1.2 V into 64 levels. If observed dummy device 2 M with half the width of the sampling switch
closely it will be found that the signal in the range of 300 to 600 1 M and is driven with complementary clock as shown in the
mV occupies the digital data in the range of 01XXXX where figure 11.
XXXX varies from 0000 to 1111. This XXXX component is
the 4 bit data of interest. This ensures the input signal is split
into 16 levels of each 18.75 mV and an accurate digital
conversion data is produced. Each level is separated by 18.75
mV which is adequate to combat the variations in DAC output
voltage due to process corner variations. In addition, the SAR
logic also provides the clock signal to the analog sample and
hold circuit as the clock out signal. This clock is based upon
the SPI clock, which is divided down by a factor of eight. This
Figure 11. Track and Hold with 375.6 pF Load
is done with a counter, producing a 50% duty cycle clock.
Clock out is held high for 1 cycle of the standard clock and is
then held low for 7 cycles of the standard clock. The rising Figure 12 is the schematic symbol for Track & Hold
edge of clock out is synchronized with the beginning of the wherein Vin stands for the analog input from 0 to 1. Vin_n and
sample state. Vin_p are the clock of the Track and Hold which are 1/8 cycle
of the whole process while snh_out is the output that is
connected to the input of the comparator.
 load ranging from 1f F– 32fF to see how capacitance affects the
circuit. In transient test bench, the researchers simulated and get
the values of propagation delay and slew rate of the circuit
having no load and with load.

1. Output and Input Swing

Figure 12. Track and Hold Symbol

The simulation below shows the simulation of the

Track & Hold under 240us with 10 samples. The researchers
observed that larger value of capacitance produces better
output.

Figure 16. Input and Output Swing

Figure 13. Track and Hold Simulation

The researchers set the reference voltage to 500mV and set
the input voltage to a design variable ‘x’ and sweep it from 0 to
1V. After the simulation the input and output swing is centered
B. Comparator to 530mV.

2. DC Gain of double-tail dual-rail dynamic latched

comparator using derive function.

Figure 14. DC Test Bench

Figure 17. Gain of Double-tail Dual-rail Dynamic Latched Comparator Using

Derive Function

Using calculator and function derive the researchers plot the

output of the latched comparator and get a total gain of 50dB.

After the simulation of Input and Output Swing, the

researchers get the values of cgs. After launching ADE L, go to
Figure 15. Transient Test Bench
Results Tab then go to Print, DC Operating Point and click the
input transistor (M2 or M3) to get the values of cgs and
The two circuit diagram shown above are the test bench used
resistances.
by the researchers. DC test bench was used for getting the output
and input swing, total gain cgs, resistance and total power of the
comparator. For Transient Test Bench, the researchers simulated
 Table 2. Values of Cgs and Resistances
cgs 122.924aF The researchers simulated the circuit by using the said test
rin 359.151kΩ bench and the input values for transient analysis. By applying
rout 1.2697MΩ and changing the value of the capacitor on the output of the
comparator. The researchers determined that it affects the
behavior of the circuit and its performance. For having no load
the time it takes for the output to be 1 is 4ns and while for 10fF
3. Input Offset Voltage of the Comparator is 4.5ns.

5. Propagation Delay

Figure 18. Input Offset Voltage

By setting a DC reference voltage = 550mV, Vpulse input Figure 21. Transient Analysis of Input and Output of Comparator Without
voltage and clock with parameters of Load

Period = 100ns
Rise Time = 50ns
Delay = Fall Time = Pulse Width = 0s

The researchers get

dx= 3.7563ns
dy=5.3345mV
s = dy/dx = 1.4201MV/s
Figure 22. Transient Analysis of Input and Output of Comparator With 5fF
The researchers determined that the input offset voltage is
equal to dy which is equal to 5.3345mV. To get the propagation delay, the researchers used transient
analysis of the input and output of the comparator. It is defined
that it is the delay between output and input. The researchers
4. Transient Analysis mark the graph of the midpoint of the input by pressing letter
‘m’ and press ‘d’ at the midpoint of the output to get the distance
between them. It can now be determined the values of the
propagation delay and its speed (slew rate).

Table 3. Propagation Delay and Slew Rate Without Load

Propagation Delay = dx 1.014ns
Speed = 1/dx .98618GHz
Distance = dy 30.032mV
Figure 19. Transient Analysis of Comparator Without Load Slew rate = dy/dx 29.611MV/s

Table 4. Propagation Delay and Slew Rate With Load of 5pF

Propagation Delay = dx 1.3008ns
Speed = 1/dx .768757GHz
Distance = dy 3.5007mV
Slew rate = dy/dx 2.6912MV/s

Figure 20. Transient Analysis of Comparator With Load of 10fF

6. Power Consumption receives the inverted output of the SAR Logic and it is the one
responsible if the output of the switch is Vref or Gnd.

Figure 23. Power Consumption of the Comparator

Figure 23. DAC Switch

7. Summary

Table 5. Summary of Sizing of Double-tail Dual-rail Dynamic Latched

The pin reset in figure 24 has the same clocking as the
Comparator
Transistor Width Lengt W/L Vin_n of the Track & Hold. The circuit resets the DAC while
Component the Track & Hold is taking sample.
Type (um) h (um) ratio
High Vt
Mtail 0.12 0.10 1.2
NMOS
Low Vt
M2 & M3 0.12 0.10 1.2
NMOS
Low Vt
M4 & M5 0.12 0.10 1.2
PMOS
High Vt
M6 & M7 0.12 0.10 1.2
NMOS
High Vt
M8 & M9 .23 0.10 2.3
NMOS Figure 24. DAC Reset
High Vt
M10 & M11 0.45 0.10 4.5
PMOS The figure 25 shows the schematic of the DAC.
Low Vt
M12 & M13 0.12 0.10 1.2
PMOS
Low Vt
M14 & M15 0.12 0.10 1.2
PMOS
Low Vt
M16 & M17 0.23 0.10 2.3
PMOS
Low Vt
M18 & M19 0.12 0.10 1.2
NMOS
Low Vt
M20 0.45 0.10 4.5 Figure 25. DAC Schematic
PMOS
Low Vt
M21 & M22 0.12 0.10 1.2
PMOS
M23, M24 Low Vt
0.12 0.10 1.2
& M25 NMOS
Low Vt
M26 0.23 0.10 2.3
PMOS
Low Vt
M27 0.12 0.10 1.2
NMOS

Figure 26. DAC Symbol

C. Digital to Analog Converter (DAC)

Below are the circuit designs for the Single Ended

Binary Weighted Switched Capacitor Array DAC. The pin data
 Figure 31. SAR Logic at Cin = 0V
Figure 27. DAC Output at Cin= 0V

Figure 32. SAR Logic at Cin = 1V

Figure 28. DAC Output at Cin = 1V

E. SAR ADC
D. SAR Logic

The SAR Logic is implemented using shift registers

(top blocks) and control blocks (bottom blocks). The shift
registers consists of 2 Dflipflops, with reset only and with clear
only. The control blocks consist of Dff with reset and clear.

Figure 29. SAR Logic Schematic

Figure 33. SAR ADC Schematic

Figure 30. SAR Logic Symbol

Figure 34. SAR ADC Output


Figure 35. SAR ADC Sample at 498.91mV
Figure 36. SAR ADC Sample at 546.12mV
Figure 37. SAR ADC Sample at 852.87mV
IV. CONCLUSIONS
The researchers were able to design a high speed 6-bit
successive approximate register analog to digital converter
(SAR ADC) using 45nm CMOS technology in the Cadence
Virtuoso. Parameters needed in the simulation of the
comparator were attained. Each part was able to compare
properly samples from 0 to 1. But the post simulation of the
layout of the comparator is not accomplished. Due to the
problem encountered in the conversion of the comparator in the
integration of SAR ADC.
V. RECOMMENDATIONS
It is recommended to calculate and matched the required
values in the integration of the circuit design to the other parts
of the SAR ADC for it to work properly. Also, the comparator
needs a clock generator from the SAR Logic. The input of the
comparator is low impedance where the output of the DAC and
Track & Hold were affected when connected to the comparator.
Transistor level D-flipflop was suggested to use for the SAR
Logic to lesser the use of the transistor and to minimize glitch.
Better sizing of all the transistors used by the SAR ADC was
also recommended.
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