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Memory Design PDF
Memory Design PDF
Memory Design PDF
• Memory Types
• Memoryy Organization
g
• ROM design
• g
RAM design
• PLA design
DRAM LIFO
Shift Register
CAM
READ
Write cycle
Read access Read access
WRITE
Write access
Data valid
DATA
Data written
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
words A K2 1
N SN 2 2
Word N 2 2 Decoder Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N
Input-Output Input-Output
(M bits) (M bits)
Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals: K = log2N
N words
d == N select
l t signals
i l
Row Decoder
A K1 1 Word line
AL2 1
M.2K
Amplify swing to
Sense amplifiers / Drivers rail-to-rail amplitude
A0
Column decoder Selects appropriate
A K2 1 word
p p
Input-Output
(M bits)
Row
address
dd
Column
address
Block
address
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
ECE 261 James Morizio 6
R d O l Memory
Read-Only M Cells
C ll
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
WL[0]
V DD
WL[1]
WL[2]
V DD
WL[3]
V bias
Pull-down loads
2:4
DEC
ROM Arrayy
Y5 Y4 Y3 Y2 Y1 Y0
Looks like 6 4
4-input
input pseudo
pseudo-nMOS
nMOS NORs
WL[0]
GND
WL [1]
WL [2]
GND
WL [3]
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Programmming using
the Contact Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
WL [0]
WL [1]
WL [2]
WL [3]
Polysilicon
Diffusion
Metal1 on Diffusion
Programmming
P i using
i
Implants Only
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
Metal bypass
Precharge devices
WL [0]
GND
WL [1]
WL [2]
GND
WL [3]
DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
ECE 261 James Morizio 18
6 transistor CMOS SRAM Cell
6-transistor
WL
V DD
M2 M4
Q
M5 Q M6
M1 M3
BL BL
M2 M4
VDD
Q Q
M1 M3
GND
M5 M6 WL
BL BL
WWL
RWL WWL
M3 RWL
M1 X X
M2
CS BL 1
BL 2
RWL
M3
M2
WWL
M1
M1
X GND V DD 2 V T
CS
V DD
BL
V DD /2 V /2
sensing DD
CBL
Cross-section
Cross section Layout
Uses Polysilicon-Diffusion Capacitance
Expensive in Area (trend now is to use trench capacitors
Decoders
Sense Amplifiers
p
Input/Output Buffers
Control / Timing Circuitry
(N)AND Decoder
NOR Decoder
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3
•••
NAND decoder using
2-input pre
pre--decoders
A1 A0 A0 A1 A3 A2 A2 A3
WL3
VDD
WL 3
WL 2
WL 2 VDD
WL 1
WL 1
V DD
WL 0
WL 0
VDD φ A0 A0 A1 A1
A0 A0 A1 A1 φ
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination
bi ti off tree
t andd pass transistor
t i t approachesh
SIMILAR TO ROM
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance
p of PLA’s has drastically
y reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
B t…
But
ECE 261 James Morizio 32
Programmable Logic Array
P
Pseudo-NMOS
d NMOS PLA
V DD
GND GND GND GND
GND
GND
GND
V DD X0 X0 X1 X1 X2 X2 f0 f1
AND-plane OR-plane
ECE 261 James Morizio 33
Dynamic PLA
f AND
GND V DD
f OR
f OR
f AND
V DD X0 X0 X1 X1 X2 X2 f0 f 1 GND
AND-plane
AND plane OR-plane
OR plane
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
ECE 261 James Morizio 35
CAMs
• Extension
E t i off ordinary
di memory ((e.g. SRAM)
– Read and write memory as usual
– Also match to see which words contain a key
adr data/key
read
CAM match
write
cell_b
match
row decoder
address match0