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03 Addr Mode & Instructions-1.ppsx
03 Addr Mode & Instructions-1.ppsx
Immediate Addressing.
Direct Addressing.
Indirect Addressing.
Implicit Addressing.
REGISTER ADDRESSING
The designated data item is present in one of the
general purpose register of 8085. This mode is
primarily used to specify variables.
e.g. MOV C, H
Copy the content of register H into register C.
The data item to be copied is present in a CPU
register H.
Hence, it is Register Addressing Mode.
Execution of MOV C, H is explained next.
MOV RD, RS
MOV RD, RS – Copy the content of Source Register
(RS) into Destination Register (RD).
RS and RD can be any of the general purpose registers
(A, B, C, D, E, H, L).
Examples MOV A, D; MOV H, C; MOV A, A etc.
49 such Opcodes are there for MOV RD, RS.
This is a 1-byte instruction.
Takes 1-Machine Cycle (Opcode Fetch) to execute.
None of the Flags are affected.
IMMEDIATE ADDRESSING
The designated data item immediately follows the
Opcode and hence the name Immediate Addressing.
This mode is used to specify the constant data.
e.g. MVI E, 50H
Copy the 8-bit data 50H into register E.
The data item (50H) to be copied is present
immediately after the Opcode MVI E.
Hence, it is Immediate Addressing Mode.
Execution of MVI E is explained next.
MVI R, DATA8
MVI R, DATA8 – Move (i.e. Copy) the 8-bit data
(DATA8) Immediately in to the specified register R.
R can be any of the 8-bit general purpose registers
(A, B, C, D, E, H, L).
Examples MVI A, 40; MVI D, 10 etc.
7 such Opcodes are there for MVI R, DATA8.
This is a 2-byte instruction.
Takes 2-Machine Cycles (Opcode Fetch and Memory
Read) to execute.
None of the Flags are affected.
MVI M, DATA8
MVI R, DATA8 – Move (i.e. Copy) the 8-bit data
(DATA8) Immediately in to the memory, specified
by the HL Pair.
((HL)) ← DATA8 .
This is a 2-byte instruction.
Takes 3-Machine Cycles (Opcode Fetch, Memory
Read, Memory Write) to execute.
None of the Flags are affected.
Execution of MVI M is explained next.
LXI RP, DATA16
LXI RP, DATA16 – Load the 16-bit data (DATA16)
Immediately in to the specified register pair RP.
RP can be one of the register pair (HL, BC, DE, SP).
RP should be H for HL pair, B for BC Pair, D for DE Pair
This is a 3-byte instruction.
Takes 3-Machine Cycles (Opcode Fetch, Memory
Read, Memory Read) to execute.
None of the Flags are affected.
Execution of LXI D is explained next.
DIRECT ADDRESSING
The designated data item is stored in memory and
the memory address is specified directly in the
instruction.
e.g. LDA, 5000H, Load accumulator directly from
memory address 5000H.
A ← (5000H).
e.g. STA, 5000H, Store accumulator directly at
memory address 5000H.
A → (5000H).
Execution of LDA and STA is explained next.
LHLD & SHLD
LHLD, 5000H, Load HL Pair directly from memory
address 5000H.
L ← (5000H).
H ← (5001H).
SHLD, 5000H, Store HL Pair directly at memory
address 5000H.
L → (5000H).
H → (5001H).
Execution of LHLD and SHLD is explained next.
A Simple Program (P1)
Write an 8085 ALP (Assembly Language Program) to
copy the data 25H at memory location 2100H and
data 30H at memory location 2101H.
LXI D ADDR1
LXI H ADDR2 ; Load Memory addresses of DATA1 & DATA2.
LDAX D ; Get DATA1 in A.
MOV B, M ; Get DATA2 in B.
MOV M, A ; Store DATA2 at ADDR1.
MOV A, B ; Get DATA1 in A.
STAX D ; Store DATA1 at ADDR2.
HLT
IMPLICIT ADDRESSING
The designated data item is stored in CPU registers
or machine component but the name of operand is
not defined in the instruction.
e.g. XCHG, Exchange the content of HL Pair with
DE Pair.
HL DE.
Since operand names HL or DE is not specified in
instruction it is Implicit Addressing.
Execution of XCHG is explained next.
Program (P5) Revisited
Two data items are stored at locations ADDR1 and ADDR2.
Write an 8085 ALP (Assembly Language Program) to
exchange data items indirectly at these memory locations.
LXI D ADDR1
LXI H ADDR2 ; Load Memory addresses of DATA1 & DATA2.
LDAX D ; Get DATA1 in A.
MOV B, M ; Get DATA2 in B.
XCHG ; Exchange the addresses in HL & DE Pair.
HL = ADDR1 and DE = ADDR2.
STAX D ; Store DATA1 at ADDR2.
MOV M, B ; Store DATA2 at ADDR1.
HLT