Microelectronics Lab Reports

California State University, Northridge
College of Engineering & Computer Science

Electrical and Computer
Engineering Department
ECE 442L Digital Electronics

Course #16293
Laboratory Report
By Peter Truong, Amarbir Singh
Spring 2018
Instructor: Sequare Daniel-Berhe, Ph.D.
1
ECE 442L Digital Electronics
Laboratory Report
Contents
Lab 1. CMOS Inverters Voltage Transfer Characteristics (VTC)

Design, Simulation and Experimental Test as well as Analysis
Lab 2. CMOS Two-Input NAND Gate Design, Simulation and

Experimental Test as well as Analysis
Lab 3. CMOS Ring Oscillation and Clock Generation Design,

Simulation and Experimental Test as well as Analysis
Lab 4. CMOS Transmission Gate Design, Simulation and Experimental

Test as well as Analysis
Lab 5 & 6. CMOS D-Latch and CMOS NAND based S-R Latch Design,
Lab 7. 4x4 NOR ROM Array Design, Simulation and Experimental

Test as well as Analysis
Lab 8. CMOS Seven Ring Voltage Control Oscillator Design,

Lab 9. Cascode Voltage Switch Logic Design, Simulation and

Project Titles:
1. Digital Camera Sensor 4. Home Security Proximity Detector
2. Frequency Dividers in Radio 5. Toggle Switch Debouncer for
Communication Home Lights
3. Universal Home Garage Door 6. RFID Readers for Passive RFID
Opener Tags on Tracking Amazon
Packages
2
CMOS Inverters Voltage Transfer Characteristics
(VTC) Design, Simulation and Experimental Test as
well as Analysis
Peter Truong & Amarbir Singh
California-State-University, Northridge, College of Engineering and Computer Science, Electrical and

Computer Engineering Department
peter.truong.962@my.csun.edu, amarbir.singh.4@my.csun.edu
Abstract— The experiment involved students observing the triode region and behaves as a small resistor. When VGS is
and testing the voltage transfer characteristics of the greater than VTN and the drain-source voltage VDS is greater
CMOS inverter. Students built a circuit on a breadboard than the difference between the VGS and
VTN, the NMOS
using a 4007 CMOS inverter, and the circuit was operates in the saturation region and has a constant drain
simulated using PSPICE. The propagation delay, rise current. A graphical representation of the NMOS voltage
time, fall time, noise margin, and switching threshold were characteristic can be seen in Fig. 1.1.
measured on the circuit at different frequencies and
The PMOS has similar behaviors to the NMOS,
compared to the theoretical values.
except the voltage and current are reversed. Although the
terms that refer to the NMOS voltages can also be used to
Key Words — CMOS, fall time, inverter, MOSFET,
describe the PMOS, it is generally easier to use there reverse
noise margin, propagation delay, rise time, switching
PMOS counterparts. Instead of gate-source voltage, a PMOS
threshold
has source-gate voltage VSG. A PMOS also has source-drain
voltage VSD, instead of the drain-source voltage of the NMOS.
In addition, the PMOS has a negative threshold voltage VTP,
I. INTRODUCTION
which is usually the same magnitude of the NMOS’s VTN. In
HE CMOS stands for complementary-symmetry order to operate, a negative voltage needs to be applied to the
metal–oxide–semiconductor. It is made up of two gate of the PMOS, and the source-gate voltage that is obtained
components: the p-type and n-type MOSFETS. As seen in must be more negative or greater in magnitude than VTP. If
Fig. 1.1, the gates of the PMOS and NMOS are connected to this condition is not fulfilled, the PMOS operates in the cutoff
form the input. Both the drains are also connected to each region. If the condition is fulfilled and VSD is less than the
other, which form the output. The source of the PMOS is difference between VSG and the magnitude of VTP, the PMOS
connected to the power source VDD, while the source of the
NMOS is connected to ground. The specific reason why it is
structured this way is because of the MOSFET’s voltage
characteristic. A MOSFET operates in three regions of
operation depending on specific conditions. By using the
voltage transfer characteristics of the NMOS and PMOS, they
can be combined to form the CMOS and be used as an
effective inverter.
For an NMOS to operate, the gate needs to be
connected to a positive voltage. When the gate-source voltage
VGS is
less than the voltage threshold VTN, it operates in the
cutoff region and behaves like an open switch. When VGS is
greater than VTN and the drain-source voltage VDS is less than Fig. 1.1. Voltage transfer characteristic of NMOS
the difference between the VGS and
VTN, the NMOS operates in
3
operates in the triode region and acts as a small resistor. contrast, input variables that call for a high output will cause
However, if the operating condition is fulfilled and is VSD the PUN to operate, and the PUN will then pull the output
greater than the difference between VSG and the magnitude of node up to VDD. Simultaneously, the PDN will be cut off and
VTP, the PMOS operates in the saturation region. A graphical no dc current path between VDD and ground will exist in the
representation of the PMOS voltage characteristic can be seen circuit.
in Fig. 1.2.
Since the PMOS and NMOS share the same input
CMOS digital circuits use the PMOS and NMOS as and output in a CMOS, the two transistors can be related in
switches, thus they will be mainly utilized in the triode and terms of the output voltage Vout and the drain current relative
cutoff regions. Typically, when a logic 1 signal or is applied to the NMOS IDN. For the NMOS, Vout is simply VDS. For the
to the gate of the NMOS, it should act like a small resistance, PMOS, it is the difference between VDD and VSD. Meanwhile,
which simulates the switch turning off. When its gate is IDP has
the same magnitude as IDN, but it flows in the opposite
grounded or given a logic 0 signal, it should act like an open direction. If we combine the graphs of the voltage transfer
switch. The reverse can be said about the PMOS, where it is characteristics of the NMOS and PMOS into a singular graph
open when given a logic 1 signal and closed when given a with an x-axis of Vout and a y-axis of IDN, it would form the
logic 0 signal. Because of the small resistance, it allows graph that is seen in Fig. 1.3. The VTC can also be graphed in
relatively all the voltage of the power supply and ground to be terms of Vin and
Vout, as seen in Fig. 1.4.
outputted, creating a full signal swing. This means Vout can
For a typical inverter, the VTC can be described with
range from 0V to VDD.
three regions: low-input region, transition region, and
The behavior in the CMOS leads to no static power high-input region. What dictates which region the inverter is
dissipation. Static power dissipation is power being consumed currently operating in is the value of the voltage input Vin. For
while there is no circuit activity or the inputs staying constant. instance, the CMOS inverter will operate in the low-input
In both states of a low and a high output, there is no dc path region when the input voltage is low. For this region, the
between the power supply and ground, thus no power is input
consumed.
As stated earlier, a CMOS inverter has the gates of
the two transistor types connected to each other to form the
input and the drains connected to each other to form the
output. The central idea is that the logic of the input will turn
one transistor on and the other off, which also means that one
will operate at a time and the other will act like an open
circuit. The CMOS logic gate, including the inverter, consists
of two networks: the pull-down network (PDN) and the
pull-up network (PUN). The PDN is made up of NMOS
transistors, while the PUN is made of PMOS transistors. The Fig. 1.3. VTC of CMOS logic inverter in terms of input and output voltage
networks are operated by the input variables, in a
complementary manner. The PDN will operate for inputs that
require a low output and will then pull the output node down
to ground or 0V. During this case, the PUN will be off, and no
direct DC path will exist between VDD and ground. In
Fig. 1.2. Voltage transfer characteristic of PMOS

Fig. 1.4. VTC of CMOS logic inverter in terms of input and output voltage
4
does not necessarily have to be exactly 0V or ground. In the transistors will ideally operate at a time for a low or high state
physical world, noise or interference signals are bound to output, the maximum high output VOH will be VDD and the
happen within a circuit. The noise can be caused by physical minimum low output VOL will be 0V. To determine VIH, it
components of the circuit itself, such as capacitances of the should be noted that the NMOS is in the triode region and the
wires. An advantage of digital circuits is that logic circuits will PMOS is in saturation. Therefore, the drain currents of the
behave the same if the input voltage is altered by an amount of transistors are equal and the relationship is given by (7).
noise within a specific margin of values. In the case of the Assuming that the PMOS and NMOS are matched, the aspect
low-input region, the noise can be within a range of voltages ratios and the transconductance parameters will cancel each
called the noise margin for low input NML. As long as the other and will not matter in the derivation of VIH. In addition,
amount of noise is within the noise margin NML, the inverter at VIH, the incremental gain of the CMOS is unity or the slope
will ideally output the maximum high output voltage VOH that of Vout/Vin is -1. If we apply this to the previous equation, the
it is capable to produce, as opposed to the minimum low result will be (8). After we obtain Vout from (8), we can plug it
output voltage VOL. The maximum amount of input voltage, into (7) and get the final equation of VIH that is shown in (9).
including the noise, that the inverter interprets as logic 0 is A similar method can be done for VOH, but a symmetrical
denoted by VIL. The noise margin for low input is the relationship from (10) can be used to obtain it easier, which
difference between VIL and VOL. results in (11). Using the equations that we derived, the noise
margins are given by (12) and (13).
Similar to the low-input noise margin, the high-input
noise margin is determined by two parameters. One of the iDP = 12 k ′p ( WL )P [(V DD – V in – |V T P |) (V DD − V out ) (3)
parameters is VOH. The other parameter is the minimum
2
amount of input voltage, including the noise, that the inverter − 12 (V DD − V out ) ]
interprets as logic 1. This is denoted by VIH. The noise
2
margin for high input is the difference between VOH and VIH. iDN = 12 k ′n ( WL )N [(V in – V T N ) V out − 12 (V out ) ] (4)
The transition region occurs when the input voltage 2
iDP = 12 k ′p ( WL )P [(V DD – V in – |V T P |) ] (5)
transitions from low to high or vice versa. More specifically,
it occurs when the input voltage is between VIL and VIH. In 2
iDN = 12 k ′n ( WL )N [(V in – V T N ) ] (6)
this region, the inverter acts as a amplifier. Generally, it is
desired to keep this region as small as possible, since the 1 ′ W 2
k ( ) [(V in
2 n L N
– V T N ) V out − 12 (V out ) ] = 12 k ′p ( WL )P [(V DD (7)
output is unstable and not able to be determined. Despite this,
there is an important parameter that occurs within the region, 2
− V in – |V T P |)(V DD − V out ) − 12 (V DD − V out )
which defines when the inverter switches from one state to the
other. This parameter is called the switching threshold VM.
− (V in − V T ) + 2V out = − (V DD – V in – V T ) (8)
When the input voltage is equal to the switching threshold, the
output voltage is equal to the input voltage. This plays an V IH = 18 (5V DD − 2V T ) (9)
important part in determining the time delay of the inverter.
The threshold is determined by the transconductance V IH −
V DD
=
V DD
− V IL (10)
2 2
parameters kn and kp, which are mainly determined by the
widths of the aspect ratios. Equation (1) is used to calculate V IL = 18 (3V DD + 2V T ) (11)
VM, where the variable r is given by (2).. When the product of
the PMOS’s aspect ratio and process transconductance N M H = V OH − V IH = 18 (3V DD + 2V T ) (12)
parameter is equal to that of the NMOS, they are considered
matched, which results in VM equating to half of VDD. N M L = V IL − V OL = 18 (3V DD + 2V T ) (13)
r(V DD – |V T P | ) + V T N
VM = r+1
(1) The propagation delay refers to the time it takes the
inverter to respond to a change at its input. A diagram of time
√ √
kp μp W p delays can be seen in Fig. 1.5. An input pulse experiences rise
r= kn
= μn W n
(2)
and fall times indicated by tr and tP respectively. For the
inverted output pulse, it experiences rise and fall times
To determine the voltage-transfer characteristic indicated by tTLH and tTHL respectively, which stand for low to
parameters, we need to determine the current values that flow high transition and vice versa. These rise and fall times are
through the transistors at the given input voltage. Equations measured at each individual wave’s amplitude levels of 90%
(3) and (4) are the PMOS and NMOS drain currents, iDP and and 10% of the maximum amplitude. There is also delay time
iDN respectively, when they operate in the triode region. between the two waveforms: the propagation delay from high
Meanwhile, (5) and (6) are the drain currents in the saturation
region. As mentioned previously, since only one of the
5
C 2
tP HL = * 2 (17)
kn′ (W /L)N V DD 3V T N
[ 47− V
V
+( V T N ) ]
DD DD
C 2
tP LH = * 2 (18)
kp′ (W /L)P V DD [ 47−
3|V T P | V
+| V T N | ]
V DD DD
tP = 12 (tP HL + tP LH ) (19)
When the two transistors of the CMOS are matched,

the low-to-high propagation delay tPLH and the high-to-low
propagation delay tPHL are equal to each other, which also
means the propagation delay tP is equal to both these values.
The transistors can either be manufactured to be matched, or
be they can be connected in series or parallel to modify the
aspect ratios of the NMOS (W/L)N and PMOS (W/L)P. The
second process is usually referred to as sizing, and it is
typically only done for the NMOS. Because the on resistance
Fig. 1.5. Propagation delays and transition times of logic inverter
of the MOSFET is inversely proportional to its W/L ratio, the
to low tPHL and the propagation delay from low to high tPLH. equivalent W/L ratio can be derived by adding each
They are measured at the occurrence of the 50% maximum transistor’s resistance. When the transistors are connected in
amplitude levels of the input waveform and output waveform. series, the resistances will be added in series, but the W/L
The inverter propagation delay tP is the average of the two. ratios will be added as if they were resistances in parallel.
Meanwhile, when the transistors are connected in parallel, the
To obtain the propagation delay, one needs to analyze resistances will be added in parallel, but the W/L ratios will be
its fundamental dynamic relationship given by (14). The added as if they were resistances in series.
equation represents that the current I flowing through a
capacitance C for an interval Δt deposits a charge ΔQ on the
capacitor, which causes the capacitor voltage to increase by
the overall capacitance from the transistors, devices, and
wires. Consider an ideal pulse input, with zero fall time and
rise time. For tPHL, right before the positive edge of the input
pulse occurs, the input voltage will be 0V, thus the output
voltage is equal to VDD and the capacitor is charged to this.
When the input becomes VDD at t=0, the PMOS will turn off
and NMOS will turn on. At this time, the output voltage will
start at VDD and the NMOS will be in saturation. The equation
for the current provided by the NMOS will be given by (15).
The NMOS will provide a large current for the capacitor to Fig. 1.6. Pin layout and schematic of CD4007 IC used in experiment
discharge. At t=tPHL, the output voltage will reach 50% of the
maximum output amplitude or VDD/2. The change in output
voltage will cause the NMOS to operate in the triode region,
and the equation for the current is given by (16). Using the
fundamental dynamic relationship from (14) and the average
current for this period of time, tPHL is given by equation (17).
The same method can be done for tPLH, and it is given by
equation (18). Once both components are found, tP can be
calculated using (19).
I Δt = ΔQ = C ΔV (14)
2
iN D = 12 k ′n ( WL )N [(V DD – V T N ) ] (15)
V DD V DD 2
iDN = 12 k ′n ( WL )N [(V DD – V T N ) 2
− 12 ( 2
)] (16)
Fig. 1.7. CMOS inverter circuit
6
.model MbreakND NMOS together. The source of MbreakpD was connected to a DC
+ Level=1 Gamma= 0 Xj=0 voltage source of 5V. The source of MbreaknD was
+ Tox=1200n Phi=.6 Rs=0 Kp=111u connected to ground. The input was a pulse generator, with
Vto=2.0 Lambda=0.01 several external parameters that could be adjusted. We first
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 wanted to test an unsized inverter with three different
Cgso=0.1p frequency input ranges. The chosen frequencies were
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u 400kHz, 700kHz, and 1MHz. To select a frequency for the
input pulse source, the parameter PER was equated to the
Fig. 1.8. Provided 10um SPICE NMOS model and parameters
calculated period of its respective frequency f using (21). The
rise and fall times TR and TF of each input was one-fifth the
.model MbreakPD PMOS
value of the chosen frequency’s period. The period width PW
+ Level=1 Gamma= 0 Xj=0
was made 40% of the value of PER. The delay time TD was
+ Tox=1200n Phi=.6 Rs=0 Kp=55u
made 0. Since we wanted the signal to start at 0V and rise to
Vto=-1.5 Lambda=0.04
5V, we made V1 equal to 0 and V2 equal to 5. Probes were
+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8
placed at the inputs and outputs of the inverter, and the timing
Cgso=0.2p
diagram for each frequency was simulated. The diagrams can
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u
be seen in the next section.
Fig. 1.9. Provided 10um SPICE PMOS model and parameters
PER = 1/f (21)
The next step of the procedure was to test the inverter
II. EXPERIMENTAL AND SIMULATION SETUP
at two different frequencies with a ramp input and the current
Before the start of the lab, we calculated the NMOS and PMOS models, then adjusting the widths of the
switching threshold of the inverter, given the NMOS and transistor models to obtain a switching threshold of VDD/2. The
PMOS 1um SPICE model that was provided. We were also frequencies to test were 110kHz and 200kHz. To create a
told to assume that was 5V. Calculating the k parameter from ramp input, we set the period width PW and the rise time TR
the SPICE MOSFET model required a new equation given by equal to the period of the respective frequency. The other
(20). Once the k parameters were found, we used (1) and (2) parameters were kept the same. For 110kHZ, we adjusted the
to obtain a switching threshold of 2.748V, which was not width of the NMOS model to 180µm and the PMOS model to
VDD/2. In order to obtain a switching threshold of VDD/2, we 62.6µm. For 200kHz, we adjusted the width of the NMOS
needed to match the transistor models by changing their model to 50µm and the PMOS model to 4µm. We were able to
widths. Using the (1) and the constants given, it was obtain a switching threshold of approximately VDD/2.
calculated that we needed the constant r to be 0.5. Therefore,
For the experimental part of the lab, we built the
we adjusted kn to be 660µA/V2 by changing the NMOS
inverter using a CD4007 IC. Next, we connected probes to the
model’s width to 118.919µm.
input and the output of the circuit to the oscilloscope. After
k = (0.5)(Kp)(W/L) (20) that, we tested the circuit with the function generator set to
pulse and adjusted to three different input frequencies. The
From this attempt to make the switching threshold
frequencies chosen were close or were within range of the first
VDD/2, it was observed that increasing the NMOS width will
three simulated frequencies. They were adjusted so we can
lower VM. The NMOS controls the pull-down-network
get enough proper wave forms. For each frequency, we
(PDN). Increasing the width increases the aspect ratio, which
wanted to at least show two periods of the input and output,
reduces the transistor’s resistance and increases the amount of
and we showed the switching threshold when the circuit was
current that will pass through it. The increase in current
unsized. We would then size the circuit or transistors by
through the NMOS will bring the output to ground faster,
connecting the NMOS of the inverter in parallel with another
which will reduce the switching threshold.
NMOS.
Although a switching threshold of VDD/2 allows
After they were sized, we obtained screenshots of the
maximum high and low noise margins, there is sometimes an
two-period waveforms and switching threshold on the
advantage to design the inverter to have VM greater than
oscilloscope again. The circuit was unsized again for the next
VDD/2. An inverter with a higher VM, will allow a greater
step of the procedure. We set the function generator to output
NML so more low voltage values of input voltage can be
a ramp output, which would be used as input for the inverter.
inverted to VDD. This can help decrease switching frequency
The frequencies we used were the last two that we simulated.
or tendency to switch, since it requires higher input voltage.
After that, we took screenshots of one period of the
We setup the simulations by opening the PSPICE waveforms on the oscilloscope, demonstrating the switching
program. The circuit was built by placing our MbreaknD and threshold. We sized the NMOS again, and took screenshots of
MbreakpD MOSFET models, then connecting their drains
7
one period of the waveforms. The results can be seen in the
next section.
III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS

Experimental and simulation data was collected for
three different frequencies for the CMOS Inverter. The circuit
used can be seen in Fig 1.8. In the first case we used a
frequency of 400kHZ. The time delay was also calculated and
measured for all three cases. The experimental results were
compared to actual values and verified for less than 5% error.
We can see the simulated results for first case in figure 1.9 and
the experimental results in Fig 1.10.
Fig. 1.10. Experimental Results for 400kHz case
The time delay for the first case was calculated using (22)
T LH +T HL
τP = 2
(22)
Fig. 1.8. Circuit for CMOS Inverter 400 kHz frequency caset
Fig. 1.11. Simulation Results for 400kHz case THL
Fig. 1.9. Experimental Results for 400 kHz

Fig. 1.12. Simulation Results for 400kHz case TLH
Propagation delay for the first simulation is measures as-

44.6ns+20.4ns
τP = 2 = 32.5ns
8
We can see the experimental measurements of TLH and
THL in

the figures 1.13 and 1.14-
Fig. 1.15. Simulation Results for 700 kHz case
Fig. 1.13. Experimental Results for 400kHz case TLH
Fig. 1.16. Experimental Results for 700 kHz case
Fig. 1.14. Experimental Results for 400kHz case THL
The propagation delay for the experimental case is found as-

88ns+72ns
τP = 2 = 80 ns Fig. 1.17. Simulation Results for 700 kHz case THL
The propagation delay for the simulation is calculated as 32.5

ns and the experimental propagation delay is 80 ns. We can
see the results for the second case, which is frequency 700
kHz, below. We have the simulation results in figure 1.15 and
experimental results in figure 1.16. The circuit is same as the
circuit for the first case except for the different frequency. The
propagation delay is calculated for simulation to be 25 ns and
for the experimental case to be around 81 ns. We can see the
simulated time delay in figures 1.17 and 1.18. The
experimental time delay can be seen in figures 1.19 and 1.20
Fig. 1.18. Simulation Results for 700 kHz case TLH
17.7ns+32.2ns
τP = 2 = 25 ns
9
Fig. 1.22. Experimental Results for 1 MHz case
Fig. 1.19. Experimental Results for 700 kHz case TLH
Fig. 1.23. Simulation Results for 1 MHz case THL
Fig. 1.20. Experimental Results for 700 kHz case THL

90 ns+ 72 ns
τP = 2 = 81 ns
Last case for part a of the lab was chosen to be 1MHz. The
simulated and measured for this case could be seen in the
figures 1.21 and 1.22. Again the circuit is same as case 1. The
Fig. 1.24. Simulation Results for 1 MHz case TLH
propagation delay for simulated case was measured to be
26.1 ns + 15.7 ns
around 21 ns and could be seen in figures 1.23 and 1.24. The τP = 2 = 20.8 ns
experimental propagation delay is seen in figures 1.25 and
1.26 and is calculated to be around 81 ns.
Fig. 1.21. Simulation Results for 1 MHz case

Fig. 1.25. Experimental Results for 1 MHz case TLH
10
Fig. 1.26. Experimental Results for 1 MHz case THL
88 ns + 74 ns Fig. 1.29. Experimental Results for 110 kHz case Unsized
τP = 2 = 81 ns
In the next part of the experiment, we obtain the VTC curve of

the inverter using ramp function. We can see the VTC curve
for both sized and unsized cases in figures 1.27 and 1.28 for
the simulation case. The experimental case is shown in figures
1.29 and 1.30. Both cases are based on frequency 110 kHz.
Fig. 1.30. Experimental Results for 110 kHz case Sized
Fig. 1.27. Simulation Results for 110 kHz case Unsized
Fig. 1.31. Simulation Results for 200 kHz case Unsized
Fig. 1.28. Simulation Results for 110 kHz case Sized, Wn=180u and Wp=62.6u
In figures 1.27 and 1.28 we can see that in unsized case, the
switching threshold is around 2.8V and in case of sized
NMOS, the switching threshold is closer to ideal value which
is around 2.5V. Same results can be seen in the experimental
data in figures 1.29 and 1.30.
Fig. 1.32. Simulation Results for 200 kHz case Sized, Wn=50u and Wp=4u
11
REFERENCES
[1] Sedra/Smith, “Microelectronics Circuits” 7th ed. Oxford
Univ. Press, Oxford, NY, 2015, pp. 1088-1165.
[2] Department of Electrical and Computer Engineering,

“Digital Electronics Laboratory Lab Manual”. California
State Univ. Press, Northridge, CA, 2008, pp. 9-12.
[3] Shelley, Basil. “The CMOS Inverter Explained.”

Courseware, Cal Poly, Online.
Fig. 1.33. Experimental Results for 200 kHz case Unsized
Fig. 1.34. Experimental Results for 200 kHz case Sized
In figures 1.31 and 1.32, same results can be seen for 200 kHz
case. For unsized case, the VM is closer to 3V, but after sizing,
the results are much closer to 2.5V. Our experimental results
are also very similar to the expected results and can be seen in
figure 1.33 for the unsized case and figure 1.34 for sized case.
IV. DISCUSSIONS AND CONCLUSIONS

It was observed how a CMOS inverter is created. We plotted
input/output waveform for CMOS inverter for 3 different
frequencies in the lab. It was observed that the results for all
three cases were very similar. We also verified out results
using PSpice and simulating all three cases. In the second part
of the experiment we learned how the sizing of the transistors
affects the VTC. If we want to get a desired threshold voltage,
we need to change the width of the NMOS. We simulated and
plotted the VTC for unzised case and sized case and verified
our desired results. The propagation delay was also calculated
for both experimental and simulation part. The propagation
delay for simulation was in range of 20 ns - 30 ns. In case of
Experimental data, the propagation delay was around 80 ns,
which is very close to the theoretical value of 70 ns.
12
CMOS Two-Input NAND Gate Design, Simulation
and Experimental Test as well as Analysis
Amarbir Singh & Peter Truong

amarbir.singh.4@my.csun.edu, peter.truong.962@my.csun.edu
The experiment involved designing and

Abstract—
testing a 2-input NAND gate using CMOS technology.
Once the circuit was assembled, the input signal was
applied at different frequencies, and the output signal was
observed. The circuit was also simulated using PSPICE,
whose results were compared to the ones of the experiment
and the theoretical result. In addition to observing the
behavior of the output, we observed the voltage-transfer
characteristic. Furthermore, we modified our circuit to
implement a NAND gate using the pseudo-NMOS.
Key Words — CMOS, De Morgan’s law, NMOS, NAND,

PMOS, pull-up network, pull-down network,
pseudo-NMOS, voltage- transfer characteristic
I. INTRODUCTION Fig. 2.1. PUN and PDN diagram of CMOS technology
HE CMOS can be used to implement boolean logic by should be connected in parallel. Looking at Fig. 2.2, the two
taking multiple input signals, and appropriately bringing NMOS are connected in parallel with shared nodes of the
the output to either VDD or ground depending on said input. output Y and ground. To establish a connection between the
Recall that the pull-down network brings the output to ground two nodes, at least one of the transistors need to be operating.
or 0 when the input activates it, while the pull-up network Therefore, at least one of the inputs, either A or B, need to be
brings the output to VDD or 1 when the input activates it. Fig. high. The PMOS has a similar behavior, but it pulls the output
2.1 illustrates the two networks in CMOS technology. The two to VDD and the gates of the PMOS need a logic low input.
networks are operated by the input variables in a
complementary fashion, since the NMOS will operate when
the signal applied to its gate is high and the PMOS will
operate when the signal applied to its gate is low. A particular
input will only turn on one network and turn the other one off.
In the previous experiment, we only used one transistor in
each network; however, we will be using multiple transistors
in the same network in this lab.
Boolean logic can be expressed as an equation that
tells what inputs will cause the output to be high or what Fig. 2.2. PUN and PDN diagram of CMOS technology
inputs will cause the output to be low. The equations can also
be broken down into terms of OR/NOR and AND/NAND
logic. For the transistors to implement OR/NOR logic, they
13
Table 2.1 NAND gate truth table
Fig. 2.3. PUN and PDN diagram of CMOS technology
In contrast, the AND/NAND logic requires the

transistors to be connected in series. Looking at Fig. 2.3, the
two NMOS are connected in series. To establish a connection
between the output Y and ground, both transistors need to be
operating. Therefore, both inputs A and B need to be high.
Again, the PMOS has a similar behavior, but it pulls the
output to VDD and the gates of the PMOS need a logic low Fig. 2.4. Circuit of CMOS NAND gate, sized for worst case
input.
Elaborating further, the worst case occurs when an
One implementation is the two-input NAND gate,
input combination results in the lowest output current. It is
whose output behavior is tabulated in Table 2.1. The data in
part of the designer’s job to make that current equal to that of
the table can also be described with boolean expressions.
the basic inverter by determining the size of each transistor.
Equation (1) describes that the NAND logic is simply inverted
Suppose we are trying to determine the necessary sizes for
AND logic. If we expanded the right side of the equation and
each transistor of a CMOS NAND gate for the worst case.
used De Morgan’s law, we obtain (2), which describes the
Also, suppose the necessary aspect ratios for a matched
necessary input conditions for output Y to be high. In this
CMOS inverter’s two transistors are denoted as (W/L)n and
case, either A or B need to be low for output Y to be high. If
(W/L)p. For the PDN, the amount of current does not vary
we inverted both sides of (1) and used De Morgan’s law, we
when activated. Therefore, we simply want aspect ratio of the
obtain (3), which described the necessary input conditions for
NAND’s PDN to be equal to the inverter’s PDN. Recall that
output Y to be low. In this case, both A and B need to be high
when MOSFET’s are in series, the aspect ratios are added as if
for output Y to be low.
they were parallel resistances. For the two NMOS’s aspect
Y = (A⋅B) (1) ratios to be equal to (W/L)n, each NMOS should have an
NMOS equal to 2(W/L)n. For the PUN, the worst case or
Y = A+B (2) lowest current produced occurs when only one of the two
PMOS is turned on. Since only one of them will be turned on
Y = A⋅B (3) in the worst case, each PMOS will have an aspect ratio of
(W/L)p.
Using the derived equations, the NAND gate can be
implemented using four transistors. The PUN will be made up The pseudo-NMOS involves using less transistors
of two PMOS in parallel with inputs A and B. The PDN will than CMOS technology. One implementation of the
be made of two NMOS in series with inputs A and B. The pseudo-NMOS is having the PUN only consist of one PMOS
NAND gate is illustrated in Fig 2.4. Once the circuit has been with its gate connected to its drain. This will cause the PUN
designed, the aspect ratios of each transistor should be chosen to require no input and VSG to be equal to VSD, thus the PMOS
so that each network has the current-driving capability equal will be constantly be in the triode region when it is operating.
to that of the basic inverter. This is defined as the worst case. This is a problem when we want the output to be ground, since
both the PUN and PDN will be operating. This will cause
Inputs Output power dissipation because there will be a connection between
A B Y VDD and ground. In addition, the PDN will be need to be
0 0 1 designed so it will win the fight in bringing the output to
0 1 1 ground by having more current flow through it than the PUN.
1 0 1 Another problem with this technology is that the maximum
drain or gate voltage will be VDD - |VTP|. Because the gate is
1 1 0
connected to the drain, the drain voltage will dictate if the
14
PMOS will operate, which only occurs when VSG > |VTP|. The
pseudo-NMOS will not provide a full-swing of 0 to VDD.
Fig. 2.7. Pin layout and schematic of sn74ls74 IC used in experiment
Fig. 2.5. Circuit of pseudo-NMOS implementation of CMOS NAND gate
In this experiment, we used a SN74ls74 D-flip-flop,

whose pin diagram is shown in Fig 2.7. For the time being, all
that is needed to be known is that the D-flip-flop slightly acts
like a single-pole single-throw switch. When the switch
closes, the input D will be sent to the outputs Q and Q . The
clock input of the flip-flop determines when the switch closes.
For this model, the input D is only sent during a negative to
positive transition (positive-edge) in the clock. Using this
information, a D-flip-flop can also be used as a frequency
divider with a factor of two. This can be done by having the
Q output connected to the D input. When an input frequency
is applied to the clock, output Q will output the same clock
signal, but with half the frequency. Whenever a positive-edge
Fig. 2.8. Frequency division diagram
occurs on the clock input, the flip-flop will sample input D at
that instant and Q will be the inverted output. The next time a .model MbreaknD NMOS
positive-edge occurs, D will be equal to Q from the previous + Level=1 Gamma= 0 Xj=0
occurrence of the positive edge. Q will produce the inverted + Tox=1200n Phi=.6 Rs=0 Kp=111u
output again, and the cycle will repeat. Vto=2.0 Lambda=0.01
Cgso=0.1p
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u
.model MbreakpD PMOS

Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u
Fig. 2.6. Pin layout and schematic of CD4007 IC used in experiment
15
II. EXPERIMENTAL AND SIMULATION SETUP In the experimental portion, we only needed to size
the NMOS transistors of the NAND gate. This was done by
Before the start of the experiment, we were asked to
connecting the NMOS transistors in the NAND gate circuit in
consider the sizes needed for the transistors of a four input
parallel with other NMOS transistors on other CD4007 IC’s.
NAND gate and a three input NOR gate. For the four input
NAND gate, its structure will be similar as the two input
NAND gate. Referring to Fig 2.4, two more PMOS transistors
will be added in parallel to the PUN and two more NMOS III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS
transistors will be added in series to the PDN. Using a similar
method mentioned previously, the PDN’s aspect ratio will be Experimental and simulation data was collected for
needed to be equal to that of an inverter, thus each NMOS will three different frequencies for the CMOS Two-Input Nand
have an aspect ratio of 4(W/L)n. The worst case will also be Gate. The circuit used can be seen in Fig 2.10. In the first case
similar to what was mention previously, where only one we used a frequency of 400kHZ. We also sized the NMOS
PMOS will operate. Each PMOS will have an aspect ratio of transistors to bring the Vm down. We can see the simulated
(W/L)P. For a three input NOR gate, it will have a reverse results for first case in figure 2.11 and the experimental results
structure of the NAND gate. In the PUN, there will be three in Fig 2.12.
PMOS in series with aspect ratios of (W/L)p each. In the PDN,
there will be three NMOS in parallel with aspect ratios of
3(W/L)n.
We setup the simulations by opening the PSPICE
program. The circuit was built by placing our MbreaknD and
MbreakpD MOSFET models similar to that of Fig. 2.2. Two
inputs A and B were provided by two pulse wave inputs of
5V, with input B having twice the period length of input A.
This also means that input B has half the frequency of input A.
Probes were placed at input A, input B, and the NAND output.
Three cases were simulated, each with B having half the
frequency of A. The three cases were input A having
frequencies of 400kHz, 700kHz, and 1MHz.
Next, the voltage transfer characteristic was observed
with the transistors unsized and appropriately sized at two
different input frequencies each: 110kHz and 200kHz. The
transistors were appropriately sized with the methods
mentioned previously and the NMOS widths were doubled to Fig. 2.10 CMOS Nand Gate Simulation Circuit
simulate the worst case.
The circuit on PSPICE was then modified to

implement the pseudo-NMOS configuration in Fig 2.5. In this
case, we used only one PMOS whose gate was connected to
drain. One input had a frequency of 1MHz and another had a
frequency of 500kHz. The pseudo-NMOS allowed us to
observe the worst case, since only one PMOS was left
operating.
Once the simulations were done, the circuits were

built in accordance to the schematics earlier, including the
psuedo-NMOS NAND gate configuration. To create two Fig. 2.11 CMOS Nand Gate Simulation Results for case 1
inputs, input A with the higher frequency was provided by a
As we can see in the figure 2.11, the nand gate output is high
function generator. The other input B was provided by a
unless both of the inputs are high at the same time, which
D-flip-flop with a clock input of input A. This functioned as a
satisfies the truth table for the nand gate. We are using the
frequency divider. The inputs and outputs were measured by
same sizes for all the transistors in our model. We can also use
using probes and a four-channel oscilloscope. The same
this circuit as an inverter by connecting all the inputs together.
frequency ranges from the simulations were used in the
experimental portion.
16
Third case was repeating the simulation and
experimental data for 1 MHz frequency. The simulation
results could be seen in figure 2.15 and the experimental
results could be seen in figure 2.16.
Fig. 2.15 CMOS Nand Gate Simulation Results for case 3

Fig. 2.12 CMOS Nand Gate Experimental Results Case1
In the second case, we chose the frequency to be 700

kHz and the circuit is same as figure 2.10. We are showing the
results for three cycles only. The circuit is similar to the case
one except for the different frequency.
Fig. 2.16 CMOS Nand Gate Experimental Results for case 3
Fig. 2.13 CMOS Nand Gate Simulation Results for case 2 As we can see in the experimental results, the output is not
pulled down all the way because of unsized NMOS. So we are
sizing the transistors to bring the output down. We are
connecting another NMOS gate to gate, drain to drain and
source to source. The results of the sized NMOS can be seen
in figure 2.17.
Fig. 2.14 CMOS Nand Gate Experimental Results for case 2
Fig. 2.17 CMOS Nand Gate Sized Experimental Results for case 3
17
We also plotted the VTC curve using two different
frequencies, 110 kHz and 200 kHz, unsized and sized.
Fig. 2.22 CMOS Nand Gate Simulation VTC Curve 200 kHz Unsized
Fig. 2.18 CMOS Nand Gate Simulation VTC Curve 110 kHz Unsized
Fig. 2.23 CMOS Nand Gate Simulation VTC Curve 200 kHz Sized
Fig. 2.19 CMOS Nand Gate Simulation VTC Curve 110 kHz Sized
Fig. 2.24 CMOS Nand Gate Experimental VTC Curve 200 kHz Unsized
Fig. 2.20 CMOS Nand Gate Experimental VTC Curve 110 kHz Unsized
Fig. 2.21 CMOS Nand Gate Experimental VTC Curve 110 kHz Sized Fig. 2.25 CMOS Nand Gate Experimental VTC Curve 200 kHz Sized
18
The Nand Gate was also constructed using Pseudo
Nmos technology. In this case, we used only one PMOS
whose gate was connected to drain. The circuit can be seen in
figure 2.26. We can see the simulation results in figure 2.27
and experimental results in figure 2.28.
Fig. 2.28 Pseudo NMOS Nand Gate Experimental Results

Nand gate is the most used gate in digital design. We
simulated and implemented Nand Gate using CMOS and
Pseudo NMOS technologies. We compared our simulation
results to experimental results using unsized and sized Nmos
transistors. It was concluded that in terms of output waveform,
the CMOS technology is better a better choice as it has full
swing, however Pseudo NMOS is better because it uses less
number of transistors. We also realized that sizing one time
does not make the CMOS VTC output ideal. In order to bring
Fig. 2.26 Pseudo Nmos Nand Gate Circuit Vm down, we need to size a number of times. The AND and
NOT applications of NAND gate were also discussed.
As the Pseudo Nmos cannot output a full swing, we can see in Provided parameters for PSpice model were used. It was also
our results that output does not have the same magnitude as observed that after sizing, the experimental results were pulled
the input. Because the PMOS is constantly on, it cannot bring down more and the output waveform was smoother.
the output all the way to ground. In addition, because the gate
is connected to its source, the voltage at the drain cannot
exceed VDD - |VTP| or else the PMOS will cease to operate. The REFERENCES
max output amplitude is around 3.5V. Even though there is
only one PMOS, the logic still works. The output is high as
long as both of the inputs are not high.
“Digital Electronics Laboratory Lab Manual”. California
State Univ. Press, Northridge, CA, 2008, pp. 13-16.
[3] “CMOS Gate Circuitry.” All About Circuits,

www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-c
ircuitry/.
Fig. 2.27 Pseudo NMOS Nand Gate Simulation Results
19
CMOS Ring Oscillation and Clock Generation
Design, Simulation and Experimental Test as well as
Analysis

The experiment involved designing and

Abstract— inverted output at the right-most inverter. Since each inverter
building ring oscillators with a different, odd number of has about the same amount of propagation delay tp,, the input
CMOS inverters. The ring oscillator generated different will go through approximately N times that amount by the end
frequencies depending on the amount of inverters added. of the inverted output. To complete one cycle or oscillation,
Once the circuit was assembled, output signals from each the input of the left-most inverter should return to its initial
inverter were observed and the average propagation delay value. Therefore, the period T of the oscillation would be
time was found.. The circuit was also simulated using double of the previous value, which is given by (1). Since
PSPICE, whose results were compared to the ones of the frequency is simply the reciprocal of the period, the oscillation
experiment and the theoretical result. frequency is given by (2). If we did not know the propagation
delay of the inverters, but we knew the amount of inverters N
Key Words — CMOS, oscillation frequency, inverter, and measured the produced frequency foscillation, we can
propagation delay, ring oscillator calculate the average propagation delay with (3).
P eriod = T oscillation = 2N tp (1)

I. INTRODUCTION
f oscillation = 1/T oscillation = 1/(2N tp ) (2)
HE CMOS can be used as inverters in a multi-ring
oscillator. A multi-ring oscillator is made up of an odd tp = 1/(2N f oscillation ) (3)
number of cascaded inverters, where one’s output is connected
to the input of another. The inverters are connected in a loop,
which means the output of the right-most inverter becomes the
new input of the left-most inverter. Fig. 3.1. shows the
general schematic of a ring oscillator.
Suppose N is an odd integer and the amount of
inverters in a ring oscillator. Observe that the input of the
left-most inverter must go through N inverters to become an
Fig. 3.1 General ring oscillator schematic
20
adding more inverters decreased the oscillation frequency.
Therefore, the max value is achieved at a 3-ring oscillator.
Given that the average propagation delay of a CMOS inverter
using the CD4007 IC is 70ns, the max frequency is 2.38 MHz.
Despite this, it it is theoretically possible to achieve an output
frequency of 2GHz if we changed the value of VDD. Equations
(4), (5), and (6) are equations used to calculate the propagation
delay of a CMOS inverter. Looking at these equations, if we
increased the value of VDD, the time delays and the overall
propagation delay would decrease. Decreasing the delays
would increase the oscillation frequency, but we will need a
Fig. 3.3. Circuit of CMOS 3-ring oscillator large value of VDD. Overall, we can theoretically get an
oscillation frequency of 2GHz if we increased the value of
.model MbreakN NMOS VDD, given that it will not burn out the chip. Otherwise, we
+ Level=1 Gamma= 0 Xj=0 must use a better IC or technology.
+ Tox=1200n Phi=.6 Rs=0 Kp=111u C 2
tP HL = * 2 (4)
Vto=2.0 Lambda=0.01 kn′ (W /L)N V DD [ 47− V
3V T N V
+( V T N ) ]
DD DD
Cgso=0.1p C 2
tP LH = * 2 (5)
kp′ (W /L)P V DD [ 47−
3|V T P | V
+| V T N | ]
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u V DD DD

tP = 12 (tP HL + tP LH ) (6)
.model MbreakP PMOS
+ Level=1 Gamma= 0 Xj=0 The experiment required us to design ring oscillators
+ Tox=1200n Phi=.6 Rs=0 Kp=55u with oscillation frequencies that were within the 5% error
Vto=-1.5 Lambda=0.04 margin of their theoretical value. The theoretical values were
+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 calculated with a propagation delay tp of 70ns. The theoretical
Cgso=0.2p values are shown in table 3.2. A part of designing these ring
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u oscillators was choosing a value of the capacitors between
each gate, which affects the propagation delay according ro
Fig. 3.5. Provided 10um SPICE PMOS model and parameters (4) and (5). This is because the voltage across a capacitor
cannot change instantaneously. The gate capacitance must
either charge or discharge to a specific value before any
II. EXPERIMENTAL AND SIMULATION SETUP current can flow from the source to the drain or vice versa,
which takes time. By selecting the appropriate gate
Before the start of the experiment, we were asked to
capacitance value, we can alter the propagation delay with a
answer some questions. One question asked to calculate the
factor that is not due to the attributes of the transistor itself.
period and frequency of a 7, a 9, and a 15 ring-oscillator given
that each inverter had an average propagation delay of 40ns. Theoretical -5% +5%
Using (1), we derived the periods were 560ns, 720ns, and
1.2µs respectively. Using (2), we derived the frequencies 3-Ring 2.38 MHz 2.26 MHz 2.50MHz
were 1.79Mhz, 1.39Mhz, and 833.33kHz respectively. 5-Ring 1.43MHz 1.36MHz 1.50MHz
Another question asked what were some advantages of a 7-Ring 1.02MHz 969kHz 1.07MHz
CMOS inverter compared to other technologies. A CMOS
inverter has an output that can achieve a full swing of 0V to 9-Ring 794kHz 754.3kHz 833.7kHz
VDD. It has very little or no static power dissipation because Table 3.1 Theoretical oscillation frequencies and 5% margin values
only one of the transistors will operate, thus no direct
connection between VDD and ground. It has high noise We setup the simulations by opening the PSPICE
margins, thus a wide range of input voltages can be used for a program. The circuit was built by placing our Mbreakn and
low input or high input. Finally, the behavior of the inverter is Mbreakp MOSFET models similar to that of Fig. 3.3. The
ratioless, meaning that it will produce the inverted output PSPICE schematic for the 3-ring oscillator can be seen in Fig.
regardless of the aspect ratios of the transistors. The third 3.4. Three probes were placed at the output of each CMOS
question asked if a 20GHz frequency output was possible inverter, and we obtained the oscillation frequency from the
using the CD4007 IC as a ring oscillator. Using the current plot. What we expected to see was three identical waveforms,
schematic and VDD of 5V we have, we cannot obtain an output each going low to high to low, endlessly. Each of the
frequency of 20Ghz. As one can see in the first question,
21
Fig. 3.6 PSPICE circuit for CMOS 7-ring oscillator
waveforms will have the same shape, but they would be

delayed and shifted to the right because of the propagation
delay of each inverter. The frequencies were obtained by Fig. 3.7 PSPICE circuit for CMOS 9-ring oscillator
measuring the period of one wave or cycle with the cursor and
using (2). After calculating the oscillation frequency and III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS
seeing if it was within the 5% margin, we built the 5-ring,
7-ring, and 9-ring oscillators on PSPICE by adding more Experimental and simulation data was collected for
inverters and probes on the right most side of the circuit. The ring oscillator in case of 3-ring, 5-ring, 7-ring and 9-ring. In
circuits can be seen in Fig. 3.5 - 3.7. The procedure for each of these cases, the measured frequency was compared to
obtaining the oscillation frequency was done for each circuit. the actual frequency and it was made sure that the results were
in 5% error margin. We can see the 3 ring oscillator in the
Once the simulations were done, the circuits were figure 3.4. The simulation results could be seen in figure 3.8.
built in accordance to the schematics earlier. This required us
to use several CD4007 IC’s. We also used external
capacitances to alter the propagation delay to obtain the
oscillation frequency we desired. The outputs and frequencies
were measured using the four-channel oscilloscope. We
observed one output on one channel for the 3-ring oscillator.
We then built the 5-ring, 7-ring, and 9-ring oscillator by using
more CD4007 IC’s. When we built the 7-ring and 9-ring
oscillator, we measured the outputs from each inverter. Since
the oscilloscope only offered four channels, we needed to split
the outputs into two groups, such as the four left-most outputs
and the four right-most outputs. The frequencies were
obtained with the measure function on the oscilloscope.
Fig. 3.8 PSPICE Results for CMOS 3-ring oscillator
As we can see that simulation results have only 1.5%

error. The experimental results for output of one inverter could
be seen in figure 3.9.
22
Fig. 3.9 Experimental Results for CMOS 3-ring oscillator
Fig. 3.12 Experimental Results for CMOS 5-ring oscillator (1st 4)
The 5-ring CMOS oscillator circuit can be seen in
figure 3.5. The simulation results can be seen in figure 3.10.
And the experimental results for one output and all the outputs
can be seen in figure 3.11, 3.12 and 3.13. There was an error
of around 1.16% between the theoretical value of frequency
and the experimental value.
Fig. 3.13 Experimental Results for CMOS 5-ring oscillator (last 4)

Fig. 3.10 PSPICE Results for CMOS 5-ring oscillator
The 7-ring circuit can be seen in the figure 3.6. We
can see the simulation results for this in figure 3.14. The
experimental results for one output and all the outputs are
shown in figures 3.15, 3.16 and 3.17. There is around 0.62%
error between the theoretical value and measured value of the
frequency of the oscillator.
Fig. 3.11 Experimental Results for CMOS 5-ring oscillator Fig. 3.14 PSPICE results for CMOS 7-ring oscillator
23
experimental values of frequency, in this case was around
0.9%.
Fig. 3.15 Experimental results for CMOS 7-ring oscillator (single Channel)
Fig. 3.18 PSPICE results for CMOS 9-ring oscillator
Fig. 3.16 Experimental results for CMOS 7-ring oscillator (1st 4)
Fig. 3.19 Experimental results for CMOS 9-ring oscillator (single Channel)
Fig. 3.17 Experimental results for CMOS 7-ring oscillator (last 4)
Fig. 3.20 Experimental results for CMOS 9-ring oscillator (1st 4)

The last case, we built and simulated a 9-ring CMOS
oscillator. We can see the circuit for this in figure 3.7. The
simulation results can be seen in figure 3.18, the experimental
results for single channel and first/last 4 channels in figures
3.19, 3.20 and 3.21. The error between theoretical and
24
Fig. 3.21 Experimental results for CMOS 9-ring oscillator (last 4)

Ring oscillators are used to create signals with
different frequencies. We used only odd number of inverters.
The frequency of the oscillator is based on the number of
inverters used and the propagation delay. We observed that the
error between theoretical values and measured value decreases
as we cascade more and more inverters. Also while plotting
two consecutive outputs, we observed that they are inverted
and shifted by the propagation delay, as expected. The
simulation results were very similar to the actual results as we
were using the same model. However we had to use different
capacitors for the simulation and different for experiment. We
did not use any input to the oscillators as oscillators work
without inputs.
REFERENCES
“Digital Electronics Laboratory Lab Manual”. California State
Univ. Press, Northridge, CA, 2008, pp. 6-9.
[3] “Ring Oscillator.” Separating and Throttling Calorimeter
(Theory) : Virtual Mass Transfer Lab : Chemical Engineering
: IIT GUWAHATI Virtual Lab, 2011, iitg.vlab.co.in/?sub=59.
25
CMOS Transmission Gate Design, Simulation and

The experiment involved creating a sample

Abstract—
and hold circuit using a transmission gate. The
transmission gate was made up of the PMOS and an
NMOS. This type of technology involved pass-transistor
logic. When the transmission gate was on, the input would
be connected to the output. The circuit’s output would
become equal to the input. When the transmission gate
was off, the output would be held at the last value of the
input before the gate turned off. It would continue to hold
this value until the gate turned on and the input changed. Fig. 4.1 Single NMOS pass-transistor logic schematic
Key Words — Clock, CMOS, cutoff, hold, NMOS, condition necessary for the the NMOS to operate inside the
pass-transistor logic, PMOS, sample, transmission gate cutoff region, which is where no current will flow through the
NMOS. Equation (1) demonstrates this condition and states
that if the voltage difference between the gate and the source
I. INTRODUCTION of the NMOS VGS is less than the threshold voltage VTN, the
HE transmission gate is an example of pass-transistor NMOS will operate in the cutoff region. In Fig. 4.1, the
logic (PTL). This form of logic uses MOS transistors in source is connected to the capacitor C and its voltage is the
a series path from the input to the output, passing or blocking output voltage vo. If the capacitor was fully discharged before
the input signal. Logic can simply be implemented with a it was charged, the NMOS will be operating since VGS is VDD
combination of switches in series or parallel, where each or greater than VTN. Once the input voltage is changed to VDD
switch is controlled by an input that determines when it closes. and the capacitor begins to charge, the voltage at the source
Each single switch can be made with a single MOS transistor will increase, which decreases the value of VGS. Once vo
or by a pair of complementary MOS transistors, which is the reaches a value of VDD - VTN, the voltage difference VGS will
transmission gate. Using pass-transistor logic in combination be equal to VTN. This fulfills the condition established by (1)
with CMOS logic allows us to implement logic function and no more current will flow through the NMOS, thus the
efficiently, because it lowers the total number of transistors capacitor will stop charging. Therefore the max value the
required than if it was done with only CMOS. output voltage can achieve is VDD - VTN, instead of the desired
value of VDD. This is why the NMOS is stated to pass a weak
Although PTL can be implemented with only one logic of 1. A similar situation can be said for the PMOS, but
MOS transistor, it has a problem with outputting the input’s instead, the smallest value it can pass if the input was 0V is
value. As seen in Fig. 4.1. a single NMOS was used to pass |VTP| and is said to pass a weak logic of 0.
an input signal vi to charge a capacitor and produce an output
voltage vo. If the control signal vC of the NMOS is VDD, the V GS ≤ V T N (1)
NMOS will operate and the input signal will flow to the
output. While the NMOS operates, if the input was equal to V SG ≤ |V T P | (2)
VDD, we want to see the output to also be VDD. Recall the
26
Despite the flaw in the single MOS transistor PTL, it
should be noted that it can be resolved by connecting the
complementary MOS transistors together, as seen in Fig 4.2.
If we were to look at the circuit in Fig. 4.1 again, we can see
the strength of the NMOS if we changed the input value.
Suppose that the capacitor is charged with a small amount of
voltage and the voltage input vi was 0V. When the control
voltage vC is VDD and the NMOS operates, the transistor will
continue to operate when the capacitor reaches the desired
output voltage of 0V. The strength of the NMOS is that it
passes a strong logic 0. The same can be said for the PMOS,
but instead, it is able to pass a desired input voltage of VDD and Fig. 4.3 Operation of the transmission gate charging a capacitor to VDD
it passes a strong logic 1. If we connected the transistors
together, they will be able compensate for their faults Although the transmission gate can pass logic 1 and
logic 0, it is not an ideal switch. There is a very small
To elaborate, assume that the capacitor in Fig. 4.3 is resistance from the transistors, thus a small voltage is lost. A
fully discharged before both transistors are turned on. When method of deriving the resistance of the transmission gate is
the control voltages are applied, the transistors will begin to by dividing the voltage across the transistor by the current
operate. If the input voltage vi had a value of VDD, the signal flowing through it. Referring to Fig 4.3, if the capacitor is
will be passed through the transistors to the output voltage vo fully discharged the NMOS will be in saturation until the
and quickly charge the capacitor. Once the capacitor reaches a capacitor is charged to VDD - VTN. The current is given by (3).
voltage of VDD - VTN, the NMOS will operate in the cutoff With the known voltage and current, the resistance of the
region and pass no current. However, the PMOS will continue NMOS is given by (4) when the NMOS operates in the
to operate and charge the capacitor to VDD, although at a saturation region. Once the capacitor is charged to VDD - VTN,
slower rate than in the beginning. The benefit of this circuit is the NMOS is cutoff and the equation of the current is given by
that given an unknown input signal, we will be able to pass it (5). Using the same method as before, the resistance is given
regardless of the value. by (6). For the PMOS, it will be operating in the saturation
If one looks at the circuits in Fig. 4.2 and Fig 4.3, one region until the capacitor is charged to |VTP|. The equation is
may notice that the transistors have complementary inputs at given be (7). The resistance is calculated with (8) while the
their gates. This means that both transistors are both turned on PMOS operates in the saturation region. Once the output
or both turned off at the same time by the same signal. For voltage reaches |VTP|, the PMOS will operate in the triode
example, in Fig 4.2, if control signal C was high, its region and the current will be given by (9). The resistance is
calculated with (10) while the PMOS operates in the triode
complement C would be low and both transistors will be
region. Since the transistors are parallel, the overall resistance
operating. If C was low, its complement C would be high and
of the transmission gate is calculated with (12).
both transistors will be off. The control signal is usually from
2
a clock and dictates when a signal is sampled, or when the iDN = 12 k ′n ( WL )N (V DD − V T N − v o ) (3)
input is passed and the output becomes the same value as it. In
V DD −v o
addition, the input signal is usually referred to as data. For a RN = 2 (4)
0.5k ′n ( WL )N (V DD −V T N −v o )
sample and hold circuit, we generally want the clock
frequency to be twenty times higher than the frequency of the
iDN = 0 (5)
input changing.
RN = ∞ (6)
2
iDP = 12 k ′p ( WL )P (V DD − |V T P |) (7)
V DD −v o
RP = 2 (8)
0.5k ′p ( WL )P (V DD −|V T P |)
2
iDP = k ′p ( WL )P [(V DD – |V T P |) (V DD − v o ) − 12 (V DD − v o ) ] (9)
1
RP = (10)
k ′p ( WL )P [V DD − |V T P | − 0.5(V DD − v o )]
Fig. 4.2 Transmission gate and its circuit symbol
RT G = (RN RP )/(RN + RP ) (11)
27
We setup the simulations by opening the PSPICE
program. The circuit was built by placing our MbreaknD and
MbreakpD MOSFET models similar to that of Fig. 4.7. The
top portion was the clock and bottom portion is the sample and
hold circuit with the transmission gate. The sine wave inputs
were generated with a sinusoidal input source. The amplitudes
were adjusted by changing the value of VAMPL and the
frequency was adjusted by changing the value of FREQ.
Similar parameters were adjusted for the clock, which used a
input pulse source. To generate a ramp and triangle wave
input for the sample and hold circuit, the sinusoidal source
Fig. 4.4. Pin layout and schematic of CD4007 IC used in experiment was replaced with an input pulse source. The ramp was made
by having the time rise parameter TR and the period width
.model MbreaknD NMOS parameter PW equal to the period of the wave PER. The
+ Level=1 Gamma= 0 Xj=0 triangle wave was generated by having TR and TF equal to
+ Tox=1200n Phi=.6 Rs=0 Kp=111u half the period PER, and PW was set to 0. Probes were placed
Vto=2.0 Lambda=0.01 on the input and output of the same and hold circuit. A similar
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 procedure was done for the experimental portion of the lab. A
Cgso=0.1p function generator was used to supply the clock and the input
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u waveforms. The oscilloscope and probes were used to
Fig. 4.5. Provided 10um SPICE NMOS model and parameters measure the output.
.model MbreakpD PMOS

Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u

The experiment required us to design a sample and
hold circuit using the transmission gate and the CD4006 IC.
The circuit should sample the output, which makes the output Fig. 4.7. Circuit for sample and hold with a 200kHz clock and a 200mV
10kHz sine input
the same value as the input when the transmission gate is on.
When the transmission gate is off, the circuit’s output should
hold and maintain its present output, which is equal to the
previous input before the transmission gate turned off. The
circuit was designed with a clock input connected to the gates
of each transistors’ gate. The NMOS received the direct clock
input to its gate and the PMOS received its complement to its
gate. The input of various waveforms at different frequencies
and amplitudes would be applied to one side of the
transmission gate. The input waveforms are a 200mV 10kHz
sine wave, a 500mV 15kHz sine wave, a 1V 30kHz sine wave,
a 1V 30kHZ ramp input, and a 1V 30kHz triangle wave input.
A capacitor in parallel to a large resistor was connected to the
other side of the transmission gate, which was the output. The
capacitor is used to hold the value of the output, and the large Fig. 4.8. Circuit for sample and hold with a 300kHz clock and a 500mV
15kHz sine input
resistor helps prevent the cap from discharge quickly. The
large resistor also prevents a large loss in voltage inside the
transgate due to internal resistances.
28
Experimental and simulation data was collected for 3
different sinusoidal input frequencies, ramp input, and triangle
input. For the first sinusoidal input, we chose frequency of
200kHz and amplitude of 200mV. We can see the circuit in
figure 4.7. The simulation results can be seen in 4.11 and
experimental results in 4.12.
Fig. 4.9. Circuit for sample and hold with a 600kHz clock and a 1V 30kHz
sine input Fig. 4.12. Simulation results with a 200kHz clock and a 200mV, 10kHz sine
input
ramp input
Fig. 4.13. Experimental results with a 200 kHz clock and a 200mV 10kHz
sine input
triangle wave input
sine input (Overlapped)
29
Case 2 circuit can be seen in figure 4.8. We are using experimental results are in figure 4.19 and 4.20. The circuit is
we are using a 300kHz clock with a 500mV 15kHz input. The shown in figure 4.9.
simulation results are shown in figure 4.15 and the
experimental results are in figure 4.16 and 4.17.
Fig. 4.18. Simulation results with a 600 kHz clock and a 1V 30kHz sine input
Fig. 4.15. Simulation results with a 300 kHz clock and a 500mV 15kHz sine
input
Fig. 4.19. Experimental results with a 600 kHz clock and a 1V 30kHz input
sine input
Fig. 4.20. Experimental results with a 600 kHz clock and a 1V 30kHz sine
input (Overlapped)
Next, we are using the ramp input. The circuit for that
Fig. 4.17. Experimental results with a 300 kHz clock and a 500mV 15kHz is shown in figure 4.10, the simulation results in figure 4.21
sine input (Overlapped)
and the experimental results in figure 4.22 and 4.23.
For third case, we have 600kHz clock and 1V 30kHz
input. The simulation results are shown in figure 4.18 and
30
Fig. 4.21. Simulation results with a 600 kHz clock and 1V 30 kHz ramp input Fig. 4.24. Simulation results with a 600 kHz clock and a 1V 30 kHz triangle
input
Fig. 4.22. Experimental results with a 600 kHz clock and a 1V 30 kHz ramp
input Fig. 4.25. Experimental results with a 600 kHz clock and a 1V 30 kHz triangle
input
Fig. 4.23. Experimental results with a 600 kHz clock and a 1V 30 kHz ramp
input (Overlapped) Fig. 4.26. Experimental results with a 600 kHz clock and a 1V 30 kHz triangle
input (Overlapped)
Next, we are using the triangle input. The circuit for
that is shown in figure 4.11, the simulation results in figure
4.24 and the experimental results in figure 4.25 and 4.26. We We simulated and created sample and hold circuits
are making sure for all the cases that capacitor holds the for different input signals. We used the PTL logic using
charge until next clock. We are using the same frequency as transmission gates. The input signal passes when clock is high
last sinusoid and ramp case. and is held there by capacitor when the clock goes low. The
capacitors used in the simulation were different than
31
capacitors used in the experimental circuit. It is required to test
different values of capacitors during the experiment so that
samples are held at a constant level. We also observed that as
we increase the input frequency, the noise in the output
waveform also increased.
We could have also used the amplifiers in this circuit
in order to reduce the noise. The clock is very important to this
circuit as clock and invert of clock needs to be 180 degrees out
of phase. So it is best if we use one signal and inversion of
that. This kind of sample and hold circuit works for all kind of
inputs as we tested it for sinusoids, triangle and ramp signals.
REFERENCES
[3] “CMOS Gate Circuitry.” All About Circuits,
www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-c
ircuitry/.
32
CMOS D-Latch and CMOS NAND Based S-R Latch
Analysis

The experiment involved sequential and

Abstract—
memory circuits, such as latches. In particular, the
D-latch and the NAND SR-latch were designed and built.
In addition to producing an output given an input, these
circuits hold on to the previous data, which is commonly
referred to as a state. This behavior and the sequential
logic of each circuit was observed through simulations on
PSPICE simulation. In addition, the circuits were built
using IC’s and the results were compared to the
simulations. During the experiment, the circuits were Fig. 5.1 Schematic of two cross-coupled inverters
analyzed to understand their behavior, their advantages,
and their disadvantages. cross-coupled inverters, as seen in Fig 5.1. Suppose the
voltage signal at node W is high, the signal will be inverted by
Key Words — Clock, CMOS logic, D-latch, hold, inverter G1 and the output will be low at node X. The voltage
inverter, NAND, memory, pull-down network, pull-up at node X is the same as node Y, which is used as input for
network, sample, static sequential circuits, SR-latch, inverter G2. Considering the input voltage will be low, the
transmission gate inverter will produce a high output voltage at node Z. Node Z
and node W are the same, and since they will be the same
logic level, there will be no conflict within this circuit. The
I. INTRODUCTION same can be said if the voltage signal at node W was low.
Inverter G1 will make node X and Y high, then inverter G2 will
A. Sequential Logic
make node Z low, which is the same as node W. These are the
EQUENTIAL circuits incorporate sequential logic, two different possible stable states of the latch, and states will
which has the output affected by the present value of the remain as the flow of the logic signal will continue
input and the previous output or state determined by previous indefinitely. If we made nodes X and Z as outputs, the latch
input values. The circuits hold the previous state and form will provide two complementary outputs in each state. Which
memory. In this experiment, the memory is created by a stable state the latch will operate depends on the external
positive feedback that provides the circuit with two stable excitation that forces it to the particular state, such as an
states. One stable state refers to a stored 1 and the other state external combinational logic circuit. When the external
refers to a stored 0. The states are held or remain indefinitely excitation is applied, the latch will then change the state
until the input dictates it to change, which is why it is referred according to it. The latch will memorize the external action
to as a static sequential circuit. by staying indefinitely in the acquired state. For one latch, it is
able to store one bit of information.
The positive-feedback loop is formed by a basic
memory element, the latch. The latch consists of two
33
B. D-Latch
The implementation of the D-latch in the experiment
involved two external inputs, the data input D and the clock
input Φ. It also produced two outputs, Q and Q . Since the
latch incorporated memory, it used the previous output value
Qn as an internal input to produce the next output Qn+1. The
truth table of the D-latch is shown in Table 5.1. In the table,
one may notice that when the clock is low, the next output
Qn+1 is
the same value as the previous output Qn. In addition,
the input D has no effect on the output. Therefore, the D-latch
is stated to be holding or in memory when the clock is low.
When the clock is high, Qn+1 takes on the value of the data
input D regardless of the previous output Qn. This is referred
to as sampling the data. Equation (1) is a boolean equation
that was derived from the truth table and describes this
Fig. 5.2. Circuit for clocked D-latch
behavior.
In this experiment, we wanted to observe the clock’s
Φ D Qn Qn+1 effect on the output. In theory, increasing the clock’s
0 0 0 0 frequency would increase the amount of times the data D is
0 0 1 1 sampled. There will be less opportunity for the input to
0 1 0 0 change when left-most transmission gate off. Therefore, the
output Q will be more accurate and look more similar to D
0 1 1 1
than if the clock was at lower frequencies.
1 0 0 0
1 0 1 0 C. SR-Latch
1 1 0 1 The experiment required us to observe the NAND
1 1 1 1 gate implementation of the SR-latch. The truth table of a
Table 5.1 D-latch truth table general SR latch is shown in Table 6.1. The latch has two
external inputs S and R, which dictates the operation or state
Qn+1 = ΦQn + ΦD (1) that the latch is in. It also produces two outputs, Q and Q .
Since the latch incorporates memory, it uses the previous
The D-latch we designed used two inverters and two output value Qn as an internal input to produce the next output
transmission gates, as seen in Fig. 5.2. The transmission gates Qn+1. When both S and R are 0, the latch is in the hold state,
were chosen to block or allow data to pass through, regardless where the next output Qn+1 is the same as the previous output
of the input value. The inverters were used to form the latch Qn. When S is 0 and R is 1, Qn+1 will be 0, regardless of Qn.
that held the bit of memory. If one were to analyze the circuit, When S is 1 and R is 0, Qn+1 will be 1, regardless of Qn. The
one can see that the two transmission gates are receiving final state is referred to as a prohibited state. For the NAND
complementary clock inputs to each of their gates. The implementation, when S and R are 1, both Qn+1 and Qn+1 will
left-most one receives an input of clock to its NMOS gate, be 1. By definition, this should not happen because they are
while the other one receives an input of clock to its NMOS complements of each other. In addition, when S and R are
gate. Ideally, only one of the two transmission gates will be immediately changed to 0 after this state, the state and output
operating at any moment. One may also notice that the two will be unknown. This case must be avoided.
inverters are cross-coupled when the the right-most
transmission gate is operating, which forms the latch. When S R Qn Qn+1 Operation
the clock is high, the left-most transmission gate operates and 0 0 0 0 hold
the other one does not. The operating gate allows the data 0 0 1 1
input D to pass through and connect to the two inverters. The 0 1 0 1 reset
inverters produce two outputs Q and Q . Since there is a 0 1 1 1
direct connection between the data input and the outputs, the 1 0 0 0 set
outputs will change accordingly with the data. When the 1 0 1 0
clock is low, the left-most transmission gate will turn off, but 1 1 0 prohibited
the other one will begin to operate. The gate will form a 1 1 1
positive-feedback loop for the two inverters. Table 6.1 SR-latch truth table
34
The NAND SR-latch implementation looks similar to D. Further Explanation
the two cross-coupled inverters, except the inverters are
There are uses for both the D-latch and SR-latch, as
replaced with NAND gates. A diagram of the latch is shown
well as advantages and disadvantages for each one. A major
in Fig. 6.1. The diagram follows the truth table, but the inputs
advantage the D-latch has over the SR-latch is that it has no
of S and R must be inverted. Equations (2) and (3) are derived
prohibited state. In addition, a major difference of our
from the diagram. The CMOS NAND SR-latch schematic can
implementation of the NAND SR-latch over out
be obtained by replacing each NAND gate with its equivalent
implementation of the D-latch is that it is asynchronous, while
CMOS logic circuit and connecting the appropriate nodes.
the D-latch is synchronous. The NAND SR-latch’s stored
The inputs S and R should be inputs to CMOS inverters,
data can be changed anytime without waiting for a clock.
whose outputs will be connected to transistors of the CMOS
Meanwhile, the D-latch’s input must wait for the clock to be
NAND gates. Once these steps are done, the schematic should
high in order to change the latch’s stored data. This can be
look like the one in Fig. 6.2.
seen as an advantage or disadvantage. Since the SR-latch does
Qn+1 = S Qn (2) not have a clock, it can cause Q and Q to be unstable or be in
a metastable state. It can lead to an unpredicted result because
Qn+1 = R Qn (3) the outputs are also used as inputs. In contrast, if the the
D-latch’s clock has an appropriate frequency, it will be not
During the design of an SR-latch, the transistors of have to worry about the unstable outputs.
the CMOS NAND gate should supply enough current to pull One other example of sequential logic is the JK
the nodes Q or Q_bar down to a voltage at least slightly below flip-flop, which is synchronous. The JK flip-flop is similar to
the threshold of the other NAND gate. In contrast, the circuit the SR latch, but it has no issue with the prohibited state.
can also be designed so the transistors supply enough current When both inputs J and K are 1, it will toggle the output. If
to pull nodes Q or Q_bar up to a voltage at least slightly above the output Q was a 1, it will become a 0 and vice versa.
the threshold of the other NAND gate. The important note is Another example is the master slave flip-flop. Although it is
that a sufficient amount of current within the circuit is needed technically one flip-flop, it can be represented as consisting of
to allow the inputs of the NAND gates to achieve the two internal flip-flops. One is referred to as the master, and the
switching threshold. This will trigger the circuit to change the other one is referred to as the slave. The output of the overall
output values that it stores when S and R dictate it to do so. flip-flop is the slave output, and the overall input is the
master’s input. The two internal flip-flops are given
complementary clocks, where only one will operate at a time.
For example, when the clock is high, the master will take the
its input and produce an output. Meanwhile, the slave will
hold its last output it had when the clock was low. When the
clock is low, the input of the master will not affect the
master’s output. The master will hold its previous output. The
master output will then be used as the slave’s input, which
affects the slave’s output. The entire flip-flop is edge sensitive.
Fig. 6.1. Cross-coupled NAND gates to form SR-latch
Fig. 6.2. Circuit for SR-latch NAND implementation
35
Fig. 6.4. Pin layout and schematic of sn74ls74 IC used in experiment Fig. 5.3. Circuit for D-latch, clock 400kHz and data input 200kHz
.model Mbreakn NMOS The clock input came from a function generator, whose
+ Level=1 Gamma= 0 Xj=0 frequency we increased for each case. Since we wanted the D
+ Tox=1200n Phi=.6 Rs=0 Kp=111u input to be relatively in phase with the clock input, we used
Vto=2.0 Lambda=0.01 the same signal, but we needed to run it through the frequency
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 divider. For example, our first case wanted the D input to be
Cgso=0.1p 200kHz and the clock to be 400kHz. We would set the
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u function generator to produce a 400kHz signal to be used as
Fig. 6.5. Provided 10um SPICE NMOS model and parameters the clock. Then, we ran the same signal through the
divide-by-two frequency divider to obtain a D input of
.model Mbreakp PMOS 200kHz. Because each case required increasing clock
+ Level=1 Gamma= 0 Xj=0 frequencies, the frequency divider needed to be reconstructed
+ Tox=1200n Phi=.6 Rs=0 Kp=55u each time to obtain the appropriate frequency for the data.
B. Experiment 6: NAND SR-Latch
Cgso=0.2p We setup the simulations by opening the PSPICE
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u program. The SR-latch circuit was built by placing our
Fig. 6.6. Provided 10um SPICE PMOS model and parameters Mbreakn and Mbreakp models according to Fig. 6.7. The S
and R inputs were provided by two independent pulse sources.
Four cases were simulated. Three cases were simulated with
the given MOS models, where the S input was at 400kHz,
II. EXPERIMENTAL AND SIMULATION SETUP 700kHz, and 1MHz. For each case, the R input was half the
A. Experiment 5: D-Latch frequency of the S input. The fourth case required us to size
the transistors and test it on any of the previous S input
We setup the simulations by opening the PSPICE frequencies.
program. The D-latch circuit was built by placing our
Mbreakn and Mbreakp MOSFET models according to Fig 5.3. During the experimental portion, the circuit was built
The clock input and data input were provided by independent using the CD4007 and SN74ls74 IC. The NMOS and PMOS
pulse sources. Five different cases were simulated, each with transistors were provided by the CD4007 IC. The SN74ls74
the clock at different frequencies. The data input D was kept IC was used as a frequency divider. The S input was provided
at a frequency of 200kHz throughout the simulations. by a function generator. The same input was ran through the
Meanwhile, the clock was ran at double that frequency for one frequency divider, whose output was half the S input’s
case, four time the next case, then eight times, then 16 times, frequency and used as the R input. We tested two cases with S
and finally 32 times. input at 400kHz and 600kHz when the circuit was unsized.
After that, we sized the circuit by connecting additional
The same cases, except for the last one, were tested in transistors in parallel with the ones in our circuit. Three
the experimental portion. The circuit was built using the additional cases were done with the newly sized circuit and the
CD4007 and SN74ls74 IC. The NMOS and PMOS transistors S input set at frequencies near the range of the ones we
in the CD4007 IC were used to build the inverters and simulated. The frequencies needed to be further changed to
transmission gates necessary for the D-latch. The SN74ls74 provide a better picture on the oscilloscope.
was used as a frequency divider to provide the data input D.
36
Next we use the frequency of the clock 4 times
frequency of the input, so the clock has 4 times smaller period.
In this case, the output shows up after half clock cycle also,
which is 8 times smaller than the input cycle. So this circuit is
more accurate than the last one. We can see the simulation
results in figure 5.6 and experimental results in figure 5.7.
Fig. 6.7. Circuit for NAND SR-latch, unsized, S 400kHz and R 200kHz

D-Latch-
Experimental and simulation data was collected for 5
different cases of clock for D-latch. We can see in figure 5.4,
when the clock is double the frequency than input, the correct
output shows up after half a clock cycle, or when the clock is Fig. 5.6. Simulation results for D-latch, clock 800kHz and data input 200kHz
high. We can see the same thing for experimental data in
figure 5.5. The circuit for D-latch is shown in figure 5.3.
Fig. 5.4 Simulation results for D-latch, clock 400kHz and data input 200kHz
Fig. 5.7.Experimental results for D-latch clock 800kHz and data input 200kHz
We can see the results for 8 times clock frequency

than input frequency in figures 5.8 and 5.9. And we can see
results for 16 times frequency in figures 5.10 and 5.11.
Fig. 5.5 Experimental results for D-latch clock 400kHz and data input 200kHz
Fig. 5.8. Simulation results for D-latch, clock 1.6MHz and data input 200kHz
37
Fig. 5.12. Simulation results for D-latch, clock 6.4MHz and data input 200kHz
SR-Latch-
We collected simulation and experimental data for
the SR-latch for 3 different frequencies. We can see our circuit
Fig. 5.9 Experimental results for D-latch clock 1.6MHz & data input 200kHz in figure 6.7. For the first case, sized, we can see simulation
results in figure 6.8 and experimental results in figure 6.9.
Fig. 5.10. Simulation results for D-latch, clock 3.2 MHz and data input
Fig. 6.8. Simulation results for NAND SR-latch, Sized, S 400kHz and R
200kHz
200kHz
Fig. 6.9. Experimental results for NAND SR-latch, Sized, S 267kHz and R
Fig. 5.11 Experimental results for D-latch, clock 3.2MHz and data input 134kHz
200kHz
We can see that when S input is high and R input is
As we increase the frequency of the clock, the input low, the output is high. When S input is low and R input is
shows up faster at the output. So we also simulated D-latch high, the output is low. When both inputs are low, the output
with clock having 32 times more frequency than input. We can doesn’t change and when both inputs are high the output is
see the simulation results in figure 5.12.
38
unpredictable. For the second case sized, the simulation results
are shown in figure 6.10 and experimental in 6.11.
Fig. 6.10. Simulation results for NAND SR-latch, Sized, S 700kHz and R
350kHz Fig. 6.13.Experimental results for NAND SR-latch, unsized, S 600kHz and R
300kHz
Fig. 6.14. Simulation results for NAND SR-latch, sized, S 1MHz and R
500kHz
Fig. 6.11.Experimental results for NAND SR-latch, Sized, S 650kHz and R

325kHz
For third case unsized, we can see the simulation

results in figure 6.12 and experimental results in 6.13. And we
can see sized results for the same frequency in figure 6.14 and
6.15.
Fig. 6.15.Experimental results for NAND SR-latch, sized, S 1.2MHz and R

600kHz

D-latch works as passing the input data to output
Fig. 6.12. Simulation results for NAND SR-latch, unsized, S 1MHz and R when the clock is high. So if the frequency of the clock is
500kHz
much higher than input, the output is closer to the input
39
waveform. While the clock is low, the input has no effect on
the output and the last input stays there. The SR-latch has 4
different possible outputs based on the inputs. When S and R
are both 0, the latch outputs the last state. When S is hgh and
R is low, the output is high. When S is low and R is high, the
output is low. And when S is high and R is high, the output is
unpredictable. While sizing the transistors in case of SR latch,
the output did not change significantly as it is already pulled
down enough. Even though there is a delay between clock and
clock bar, it is very small compared to the actual input, so it
won’t affect the output. We do not need a clock for SR latch
unlike D-latch.
REFERENCES
[3] “The D Latch.” All About Circuits,
www.allaboutcircuits.com/textbook/digital/chpt-10/d-latch/.
[4] “The S-R Latch.” All About Circuits,
www.allaboutcircuits.com/textbook/digital/chpt-10/s-r-latch/.
40
4x4 NOR ROM Array Design, Simulation and

The experiment involved designing a 4x4

Abstract— R1 R2 R3 R4 C1 C2 C3 C4
NOR ROM array with predetermined content. The circuit
used NOR and pseudo-NMOS logic. The data within the 1 0 0 0 0 1 0 1
ROM served as a lookup table that was not able to be 0 1 0 0 0 0 1 1
modified once it is established. In addition, we 0 0 1 0 1 0 0 1
investigated the effects of sizing the NMOS transistors on 0 0 0 1 0 1 1 0
the outputs.
Table 7.1 ROM truth table
Key Words — Bit line, NMOS, NOR, PDN, PMOS,
For this particular design, there will be four inputs or
pseudo-NMOS, PUN, ROM, word line
wordlines. There will also be four outputs or bitlines. To
construct the ROM with the given data in Table 7.1, there
should be an array of NMOS transistors whose gates are
I. INTRODUCTION
connected to the word lines, whose drains are connected to the
HE ROM stands for read only memory and they can be bitlines, and whose sources are connected to ground. Each
used to store a microprocessor operating-system program bitline is connected to the power supply through a loaded
or fixed data, which is data not meant to be altered. The ROM PMOS. The PMOS transistor’s gate is connected to ground,
is hardwired hardware, thus the data within it cannot be implementing pseudo-NMOS logic. The PMOS will
overwritten. continuously operate and supply current. If a cell contains a 0,
an NMOS transistor will be placed in the cell’s location. If a
In this experiment, the ROM will serve as a lookup
cell contains a 1 there will be no transistor placed in the cells’
table. The truth table is shown in Table 7.1. The columns
location. The completed circuit is shown in Fig. 7.1. When a
labeled R1 - R4 are the rows of the ROM, which represent
wordline is selected, a logic 1 signal will be sent to it. The
wordlines. A wordline is used to select a row of data or word
wordlines that are not selected will have a logic 0 sent to them,
to be read in the rom. The wordline is the address or location
and they will have no effect on the output. The NMOS
where the data is stored. A wordline is selected by sending a
transistors connected to the selected wordline will begin to
signal of 1 to it, and only one wordline at a time should be
operate and bring its respective output bitline to ground.
selected. For example, if we want to read the data in row 1,
When there is no NMOS in a cell, the bitline will remain at the
we should send a 1 to wordline R1 and 0’s to the rest.
power-supply voltage because of the pull-up PMOS. For this
Meanwhile, the columns labeled C1 - C4 are columns of the
design and pattern, none of the column’s transistors can be
ROM, which represent output bitlines. The bitlines send the
switched. If they were switched, it would alter the data.
data of the selected row to be read, and each one sends only
one bit. For example, if wordline R1 is selected, the data read A drawback of this design is that it dissipates static
is 0 from C1, 1 from C2, 0 from C3, and 1 from C4. The power, since there will be a connect between VDD and ground
intersection of a wordline and a bitline represents a cell of when the NMOS transistors operate. In addition, one needs to
memory. needs to account for the struggle between the PDN and PUN.
The PMOS will continuously try to bring the bitline to VDD.
41
Fig. 7.2. Circuit for 4 bit counter, producing wordline inputs
Fig. 7.1. Circuit for 4x4 NOR ROM array
However, if a cell’s NMOS is operating, the NMOS will try to

bring the bitline to ground. Since we desire the bitline to be
grounded whenever the NMOS operates, we need to size it so
the PDN wins. We should increase the aspect ratio of the
NMOS, which will decrease the transistor’s resistance and
increase the amount of current the goes to ground.
Fig. 7.3. Output waveform for counter
Another type of ROM is PROM, or programmable
read only memory. Similar to the ROM, the PROM is only
meant to be read and the data cannot be changed within the
system it is used in. When the PROM is manufactured, it is
empty. The PROM is programmed after manufacturing, using
a device called a PROM programmer. Typically, the PROM
is only meant to be programmed only once.
RAM and ROM are both types of memory that can
store data and binary numbers in patterns. RAM stands for
random access memory. The key difference is that the
contents of RAM can be altered, which means that data can be
read from and written to the memory addresses of RAM.
Another difference is that RAM is volatile, while ROM is Fig. 7.4. Pin layout and schematic of CD4007 IC used in experiment
non-volatile. For RAM, when its power supply is turned off
or removed, its contents will be lost. In contrast, when the
power supply is turned off or removed from the ROM, the
contents will remain.
During this experiment, the SN74ls74 IC was used to
produce a counter, whose outputs were connected to the
wordlines. The schematic for the counter is seen in Fig. 7.2
and its produced output to each wordline is seen in Fig. 7.3.
The counter would send a sequence of 1000, 0100, 0010, and
0001 repeatedly, where each beat corresponded to wordlines
R1 - R4 respectively. This allowed us to look at the data each
wordline contained, having only one wordline on at any time.
Fig. 7.5. Pin layout and schematic of sn74ls74 IC used in experiment
42
.model Mbreakn NMOS For the experimental portion, the circuit was built
+ Level=1 Gamma= 0 Xj=0 using the CD4007 IC. The inputs of the wordlines were
+ Tox=1200n Phi=.6 Rs=0 Kp=111u provided by the counter built from the SN74ls74 IC. Probes
Vto=2.0 Lambda=0.01 were connected to each of the bitlines, with channel 1
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 connected to bitline C1. With the NMOS transistors unsized,
Cgso=0.1p three frequencies close to the ones we simulated were tested.
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u We adjust the frequencies to obtain a proper picture on the
Fig. 7.6. Provided 10um SPICE NMOS model and parameters oscilloscope. Once the three frequencies were tested, we sized
the NMOS transistors by connecting other NMOS from other
.model Mbreakp PMOS CD4007 IC’s in parallel to the ones in out circuit. We tested
+ Level=1 Gamma= 0 Xj=0 the same frequencies again and observed the results on the
+ Tox=1200n Phi=.6 Rs=0 Kp=55u oscilloscope.
Cgso=0.2p III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u Experimental and simulation data was collected for
Fig. 7.7. Provided 10um SPICE PMOS model and parameters three different frequencies of the input for the ROM. We are
inputting 4 signals with only one signal high at a time. We are
using a decade counter which is counting upto 4 and then
II. EXPERIMENTAL AND SIMULATION SETUP resetting. We can see our input sequence in figure 7.3. We can
We setup the simulations by opening the PSPICE see the experimental inputs in figure 7.9.
program. The circuit was built by placing our Mbreakn and
Mbreakp MOSFET models as seen in Fig. 7.8. All the
wordlines were supplied by individual input pulse sources.
Each one had the same frequency, but different time delay TD
values. The time delays allowed us to simulate the counter,
having only one wordline given a high logic input at a time,
while the other wordlines were given a low logic input. With
the MOS transistor models given, the circuit was simulated at
three different input frequencies: 400kHz, 700kHz, and
1MHz. The three frequencies were tested again, but with the
transistors sized appropriately.
Fig. 7.9. Experimental inputs to 4x4 NOR ROM array
We can see the simulation results for the first case

unsized in figure 7.10 and experimental results in figure 7.11.
Fig. 7.8. Circuit for PSPICE 4x4 NOR ROM array, 400kHz
Fig. 7.10. Simulation results for 4x4 NOR ROM array, 400kHz (Unsized)
43
The simulation results for case 2 are shown in figure
7.14 and the experimental results in figure 7.15. For case 3,
the simulation results are shown in figure 7.16 and the
experimental results in figure 7.17.
Fig. 7.11. Experimental results for 4x4 NOR ROM array, 500kHz (Unsized)
We can see that outputs are not pulled down all the
way. In order to have the output a full swing, we are sizing all Fig. 7.14. Simulation results for 4x4 NOR ROM array, 700kHz (Sized)
the future circuits. We can see the sized output for the same
case in figure 7.12 and 7.13.
Fig. 7.12. Simulation results for 4x4 NOR ROM array, 400kHz (Sized)
Fig. 7.15. Experimental results for 4x4 NOR ROM array, 700kHz (Sized)
Fig. 7.13. Experimental results for 4x4 NOR ROM array, 350kHz (Sized) Fig. 7.16. Simulation results for 4x4 NOR ROM array, 1MHz (Sized)
44
Fig. 7.17. Experimental results for 4x4 NOR ROM array, 1MHz (Sized)

A 4x4 NOR ROM array was constructed using cmos
technology. We used a decade counter for 4 inputs, which is
one high at a time. We observed that the output does not have
a full swing, so we need to size the NMOS transistors. Even
after sizing, the outputs were not pulled down all the way, so
we decided to size three times. The desired outputs were
obtained after sizing three times. Both experimental and
simulation results were identical. We had to input 4 times the
desired frequency to the decade counter as we were getting
only one forth the original frequency. As we were dealing with
very high frequencies, there was a lot of noise in the circuits
because of capacitance in the wires. Lower frequency inputs
had a clearer output.
REFERENCES
[1] “Types of ROM.” Scottish Qualifications Authority,
https://www.sqa.org.uk/e-learning/FirstLine01CD/page_24.ht
m
[2] “Memory – RAM, ROM, Cache, Flash & Virtual”
GCSE Computing,
https://gcsecomputing.org.uk/theory/memory/
45
CMOS Seven Ring Voltage Control Oscillator
Analysis

The experiment involved designing a

Abstract— P eriod = T oscillation = 2N tp (1)
seven-ring voltage controlled oscillator. It was similar to
our previous ring-oscillator, but the value of VDD was f oscillation = 1/T oscillation = 1/(2N tp ) (2)
varied. When we vary the power supply VDD, it will
change the circuit’s oscillation frequency. Theoretically, tp = 1/(2N f oscillation ) (3)
decreasing VDD will decrease the oscillation frequency.
Equations (4) and (5) are used to derive the
components of the overall propagation delay of a single
Key Words — CMOS, inverter, NMOS, oscillation
inverter. Given that the rest of the parameters are held
frequency, PDN, PMOS, propagation delay, PUN,
constant during the circuits operation, the value VDD of will
ring-oscillator, voltage-controlled oscillator
determine the value of the propagation delay. If we were to
look at these equations, we observe that the propagation delay
has an inverse relation with VDD. If we increased the value of
I. INTRODUCTION
VDD, the time delays and the overall propagation delay would
HE voltage-controlled oscillator is similar to the decrease. The propagation delay determines the oscillation
multi-ring oscillator. It is made up of an odd number of period. Since the oscillation frequency is inversely
cascaded inverters, where one’s output is connected to the proportional to the period, oscillation frequency will increase
input of another. The inverters are also connected in a loop, with VDD. As VDD decreases, the oscillation frequency
which means the output of the right-most inverter becomes the
C 2
new input of the left-most inverter. Fig. 8.1. shows the tP HL = * 2 (4)
kn′ (W /L)N V DD [ 47− V
3V T N V
+( V T N ) ]
general schematic of a ring oscillator. Recall that the period DD DD
and oscillation frequency of a ring oscillator is given by C 2

tP LH = * (5)
equations (1), (2), and (3). In this experiment, the number of kp′ (W /L)P V DD [ 47−
3|V T P | V
+| V T N | ]
2
V DD DD
inverters will be kept constant, thus N will remain equal to
seven. The variable to test will be the average propagation tP = 12 (tP HL + tP LH ) (6)
delay of each inverter tp, which is a function of power supply
voltage VDD.
Fig. 8.1 General ring oscillator schematic
46
Fig. 8.2 Circuit for voltage-controlled seven-ring oscillator 1V decrements. We took pictures of one output and one
waveform alone. We then took pictures of four of the left-most
Fig. 8.6 Circuit for PSPICE voltage-controlled seven-ring oscillator, VDD = 2V
outputs. We plotted the results of the frequency vs VDD on a

Fig. 8.3. Pin layout and schematic of CD4007 IC used in experiment graph. The graphed results were later compared.
.model MbreakN NMOS

+ Level=1 Gamma= 0 Xj=0 III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS
+ Tox=1200n Phi=.6 Rs=0 Kp=111u
Experimental and simulation data was collected for
Vto=2.0 Lambda=0.01
13 different voltages for voltage controlled oscillator. We
compared the simulated frequency data to our experimental
Cgso=0.1p
data. Our circuit is shown in figure 8.6. Results at 2,3,4, and
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u
5V is shown below. We can see results below-
.model MbreakP PMOS

Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u

We setup the simulations by opening the PSPICE Fig. 8.7 Simulation Results voltage-controlled seven-ring oscillator, VDD = 2V
program and constructing seven CMOS inverters. We then
connected them as seen in Fig. 8.6. Probes were placed at
each inverter’s output. Once the circuit was simulated and
results were plotted, we measured the period of a waveform by
selecting two points on the waveform and measuring the time
between them. The first point was a reference point, while
second point was the next occurrence of the voltage on the
next cycle. The oscillation frequency was obtained by
calculating the reciprocal of the period. We conducted several
simulation, starting at the control voltage equal to 5V, then
decrementing it by 0.25V until it reached 1V. We also plotted
the results of the frequency vs VDD on a graph. We only took
pictures of the simulation in 1V decrements.
For the experimental portion, we built the circuit
using the CD4007 IC. We measured the output’s frequency,
starting at the control voltage equal to 5V, then decrementing
it by 0.25V until it reached 1V. We measured the frequency Fig. 8.8 Experimental Results voltage-controlled seven-ring oscillator, VDD =
using the oscilloscope. We only took pictures of the outputs at 2V (1 Channel)
47
Fig. 8.9 Experimental Results voltage-controlled seven-ring oscillator, VDD = Fig. 8.12 Experimental Results voltage-controlled seven-ring oscillator, VDD =
2V (4 Channel) 3V (4 Channel)
Fig. 8.10 Simulation Results voltage-controlled seven-ring oscillator, VDD = Fig. 8.13 Simulation Results voltage-controlled seven-ring oscillator, VDD =
3V 4V
48
We can see our simulated data in figure 8.19 and

experimental data in figure 8.21. Our graphs can be seen in
figure 8.20 and figure 8.22.
Fig. 8.16 Simulation Results voltage-controlled seven-ring oscillator, VDD =

5V
Fig. 8.19 Simulated data voltage-controlled seven-ring oscillator
Fig. 8.17 Experimental Results voltage-controlled seven-ring oscillator, VDD =

5V (1 Channel)
Fig. 8.20 Simulation graph voltage-controlled seven-ring oscillator
49
REFERENCES
[3] Administrator. “Voltage Controlled Oscillators (VCO).”
Electronics Hub, 24 Dec. 2017,
www.electronicshub.org/voltage-controlled-oscillators-vco/.
Fig. 8.21 Measured Freq. data, voltage-controlled seven-ring oscillator
Fig. 8.22 Measured Fre. graph voltage-controlled seven-ring oscillator

After we plotted our frequency vs voltage data, we
observed that they are almost linearly related. If we are
increasing the voltage, the frequency is also increasing. We
also noticed that at around 2V, there is no oscillation. We had
to increase the frequency a little above 2V in order to get an
output. While measuring the experimental frequency with all
channels attached, we noticed that frequency is different than
when only one channel is attached. This might be because of
capacitance in probes. All of the results are very similar except
for results at 2V. The graph from simulated data had a slight
more curvature than graph from experimental data.
50
Cascode Voltage Switch Logic Design, Simulation
and Experimental Test as well as Analysis

The experiment involved using cascode

Abstract— but the right NMOS will not. Therefore, Output_bar will not
voltage switch logic. After simulating and building the be connected to ground. Output will be pulled to ground and
circuit, we were instructed to observe its behavior and have a logic of 0. Since Output is connected to the gate of the
understand how it works. In addition, we were told to right-side’s PMOS, that PMOS will operate and pull
observe the effect of sizing the transistors had on the Output_bar up to a logic of 1. Since Output_bar is connected
outputs. to the gate of the left-side’s PMOS, that PMOS will turn off
and not be connected to the output or ground. From this
Key Words — cascode voltage switch logic, CMOS, analysis, we can see that there is no direct connection between
NMOS, PDN, PMOS, PUN VDD and ground. Therefore, there is no static power
dissipation.
I. INTRODUCTION An advantage of implementing this type of logic is

that there is no static power dissipation. Furthermore, the
ASCODE voltage switch logic uses true and circuit produces its own complementary output, which may be
complementary input signals to produce true and desired in certain systems. However, this type of circuit
complementary outputs. A simple example was done in this requires complementary outputs, which will require additional
experiment, whose schematic is shown in Fig 9.1. Circuits inverters. In addition to the transistors required for the
that implement this type of logic have two PMOS transistors, inverters, the circuit itself requires more transistors than
forming two pull-up networks, and several NMOS transistors equivalent circuits that implement different types of logic.
that form two pull-down networks. In our case, the circuit
incorporates two PMOS transistors and two NMOS
transistors. The pull-down networks are used to implement
the logic function. In order to explain how a general circuit
with cascode voltage switch logic works, let us assume that
the PDN’s are labeled PDN1 and PDN2, while the PUN’s are
labeled PUN1 and PUN2. PDN1 and PUN1 share the same
output, and so do PDN2 and PUN2. One of the two inputs
will turn on one of the PDN’s, such as PDN1, thus its
respective output will be pulled low. The other input will turn
off the other PDN, such as PDN2, and its output will not be
connected to ground. Because the output connected PDN1 is
pulled to ground, it will turn on the opposite PUN, which is Fig. 9.1 Pin layout
PUN2. This will cause PUN2’s output to be high, which will
turn off the PUN1, since the output is connected to PUN1’s
gate.
Our circuit follows this same behavior. If Input was
logic 1 and Input_bar was logic 0, the left NMOS will operate,
51
.model Mbreakn NMOS

Fig. 9.5. Circuit for PSPICE cascode voltage switch logic, input 400kHz
+ Tox=1200n Phi=.6 Rs=0 Kp=111u
Vto=2.0 Lambda=0.01
Cgso=0.1p III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS
+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u Experimental and simulation data was collected for
Fig. 9.3. Provided 10um SPICE NMOS model and parameters three different frequencies of the CVSL. We can see our
circuit in figure 9.5. The data for the first case was collected
.model MbreakP PMOS for unsized and sized case, and just sized for case 2 and 3.
Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u

We setup the simulations by opening the PSPICE Fig. 9.6. Simulation Results cascode voltage switch logic, input 400kHz
program. We then placed the MOS transistor models and (Unsized)
connected them as seen in Fig. 9.5. Probes were placed at the
inputs and the outputs. Input was provided by a pulse source.
Input_Bar was provided by the signal from the source, but it
was ran through an inverter. We simulated the circuit with the
models given at an input of 400kHz. Next, we sized the
transistors and simulated the circuit at three different
frequencies: 400kHz, 700kHz, and 1MHz. Sizing was
necessary to make the outputs have a full-swing of 0V to VDD.
In the experimental portion, we built the circuit using
the CD4007 IC. The inputs were provided by a function
generator and a CMOS inverter. We tested circuit with an
input of 400kHz without sizing. Next, we sized the circuit by
connecting additional NMOS transistors in parallel with the
ones in the circuit. We then tested the three different input
frequencies close to ones simulated.
Fig. 9.7. Experimental Results cascode voltage switch logic, input 400kHz
(Unsized)
52
Fig. 9.8. Simulation Results cascode voltage switch logic, input 400kHz
(Sized)
Fig. 9.11. Experimental Results cascode voltage switch logic, input 700kHz
(Sized)
Fig. 9.12. Simulation Results cascode voltage switch logic, input 1MHz
Fig. 9.9. experimental Results cascode voltage switch logic, input 400kHz (Sized)
(Sized)
Fig. 9.10. Simulation Results cascode voltage switch logic, input 700kHz
(Sized)
Fig. 9.13. Experimental Results cascode voltage switch logic, input 1MHz
(Sized)
53
We observed that in order to get a correct output, we
need to size the NMOS transistors. Without sizing, the outputs
are not pulled down all the way. The output sequence in all
three cases is same. As we increase the frequency, the outputs
are not perfect square waves because of the capacitance in the
wires. This logic is very useful for electronic switches. This
type of switch requires very little transistors but we need more
transistors for sizing and for inverted inputs. Both NMOS
transistors are connected to inputs directly but the PMOS
transistors are connected to the drains of the NMOS
transistors. Even though the input does not have a full swing,
the output does. Also we observed a small delay between input
and output.
REFERENCES
[1] Mason, Andrew. “Differential Logic.” Michigan State.
https://pdfs.semanticscholar.org/presentation/c45a/6d3ac1cb6
1abcd2f2ad18bc15b007b9b03fc.pdf
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California State University, Northridge

College of Engineering & Computer Science

ECE 442L Digital Electronics

Instructor: Sequare Daniel-Berhe, Ph.D.

Lab 1. CMOS Inverters Voltage Transfer Characteristics (VTC)

Lab 2. CMOS Two-Input NAND Gate Design, Simulation and

Lab 3. CMOS Ring Oscillation and Clock Generation Design,

Lab 4. CMOS Transmission Gate Design, Simulation and Experimental

Lab 7. 4x4 NOR ROM Array Design, Simulation and Experimental

Lab 8. CMOS Seven Ring Voltage Control Oscillator Design,

Lab 9. Cascode Voltage Switch Logic Design, Simulation and

California-State-University, Northridge, College of Engineering and Computer Science, Electrical and

Fig. 1.2. Voltage transfer characteristic of PMOS

When the two transistors of the CMOS are matched,

Fig. 1.7. CMOS inverter circuit

III. E​XPERIMENTAL AND SIMULATION DATA AND RESULTS

Fig. 1.10. Experimental Results for 400kHz case

Fig. 1.11. Simulation Results for 400kHz case T​HL

Fig. 1.9. Experimental Results for 400 kHz

Propagation delay for the first simulation is measures as-

Fig. 1.15. Simulation Results for 700 kHz case

Fig. 1.13. Experimental Results for 400kHz case T​LH

Fig. 1.16. Experimental Results for 700 kHz case

Fig. 1.14. Experimental Results for 400kHz case T​HL

The propagation delay for the experimental case is found as-

The propagation delay for the simulation is calculated as 32.5

Fig. 1.23. Simulation Results for 1 MHz case T​HL

Fig. 1.20. Experimental Results for 700 kHz case T​HL

Fig. 1.21. Simulation Results for 1 MHz case

In the next part of the experiment, we obtain the VTC curve of

Fig. 1.30. Experimental Results for 110 kHz case Sized

Fig. 1.27. Simulation Results for 110 kHz case Unsized

Fig. 1.31. Simulation Results for 200 kHz case Unsized

[2] Department of Electrical and Computer Engineering,

[3] ​Shelley, Basil. “​The CMOS Inverter Explained​.”

Fig. 1.33. Experimental Results for 200 kHz case Unsized

Fig. 1.34. Experimental Results for 200 kHz case Sized

IV. D​ISCUSSIONS AND CONCLUSIONS

California-State-University, Northridge, College of Engineering and Computer Science, Electrical and

​ The experiment involved designing and

Key Words​ — CMOS, De Morgan’s law, NMOS, NAND,

I. I​NTRODUCTION Fig. 2.1. PUN and PDN diagram of CMOS technology

Fig. 2.3. PUN and PDN diagram of CMOS technology

In contrast, the AND/NAND logic requires the

Fig. 2.7. Pin layout and schematic of sn74ls74 IC used in experiment

Fig. 2.5. Circuit of pseudo-NMOS implementation of CMOS NAND gate

In this experiment, we used a SN74ls74 D-flip-flop,

.model MbreakpD PMOS

The circuit on PSPICE was then modified to

Once the simulations were done, the circuits were

Fig. 2.15 CMOS Nand Gate Simulation Results for case 3

In the second case, we chose the frequency to be 700

Fig. 2.16 CMOS Nand Gate Experimental Results for case 3

Fig. 2.14 CMOS Nand Gate Experimental Results for case 2

Fig. 2.28 Pseudo NMOS Nand Gate Experimental Results

IV. D​ISCUSSIONS AND CONCLUSIONS

[3] “CMOS Gate Circuitry.” ​All About Circuits,​

Fig. 2.27 Pseudo NMOS Nand Gate Simulation Results

III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS

Fig. 1.11. Simulation Results for 400kHz case THL

Fig. 1.13. Experimental Results for 400kHz case TLH

Fig. 1.14. Experimental Results for 400kHz case THL

Fig. 1.23. Simulation Results for 1 MHz case THL

Fig. 1.20. Experimental Results for 700 kHz case THL

[3] Shelley, Basil. “The CMOS Inverter Explained.”

IV. DISCUSSIONS AND CONCLUSIONS

The experiment involved designing and

Key Words — CMOS, De Morgan’s law, NMOS, NAND,

I. INTRODUCTION Fig. 2.1. PUN and PDN diagram of CMOS technology

IV. DISCUSSIONS AND CONCLUSIONS

[3] “CMOS Gate Circuitry.” All About Circuits,

The experiment involved designing and

P eriod = T oscillation = 2N tp (1)

IV. DISCUSSIONS AND CONCLUSIONS

The experiment involved creating a sample

II. EXPERIMENTAL AND SIMULATION SETUP

The experiment involved sequential and

III. EXPERIMENTAL AND SIMULATION DATA AND RESULTS

IV. DISCUSSIONS AND CONCLUSIONS

The experiment involved designing a 4x4

IV. DISCUSSIONS AND CONCLUSIONS

The experiment involved designing a

Fig. 8.6 Circuit for PSPICE voltage-controlled seven-ring oscillator, VDD = 2V

outputs. We plotted the results of the frequency vs VDD on a

II. EXPERIMENTAL AND SIMULATION SETUP

Fig. 8.16 Simulation Results voltage-controlled seven-ring oscillator, VDD =

Fig. 8.17 Experimental Results voltage-controlled seven-ring oscillator, VDD =

IV. DISCUSSIONS AND CONCLUSIONS

The experiment involved using cascode

I. INTRODUCTION An advantage of implementing this type of logic is

II. EXPERIMENTAL AND SIMULATION SETUP