081
A Low- Jitter Phase-Locked Loop Architecture for Clock Generation
in Analog to Digital Converters.
S. Moorthi, D. Meganathan, M. Shankar, R. Sridhar and J. Raja paul perinbam
Abstract – This paper presents the circuit level
implementation and analysis of the Phase Locked Loop (PLL)
architecture for clock generation in Analog to Digital
Converters (ADCs). The PLLs are required to generate
low-noise or low-jitter clock signals and at the same time need
to achieve fast locking. The Analog to Digital Converters
require a clock generator whose clock output should have
jitter less than 1 ps to have higher Effective Number Of Bits
(ENOB). Catering the needs of the ADC, low-jitter PLL
architecture is proposed which consist of pre-charged
phase-frequency detector, charge pump, second order loop
filter and a current-starved inverter based Voltage Controlled
Oscillator (VCO) circuit. The integrated PLL architecture is
implemented and simulated using CADENCE Analog Design
Environment. It is synthesized using TSMC 0.18µm, six-metal
technology. The lock range (operating frequency range) of the
PLL is 95MHz to 145 MHz with a center frequency of 100
MHz and a jitter of around 700 fs are obtained as a result of its
verification at all process corners.
Keywords – Phase Locked Loop (PLL), Voltage Controlled
Oscillator (VCO), Jitter, Analog to Digital Converter (ADC)
Effective Number Of Bits (ENOB), Signal-to-Noise Distortion
Ratio (SNDR).
I. INTRODUCTION
The Clock generator is a circuit that produces the timing
or the clock signal for the operation in sequential circuits.
The circuit may produce a square wave or any complex
signal based on the need of the hour. A PLL can be used as a
clock generator in microprocessors. Here, the clock
frequency required is given as the input reference signal and
once the PLL is made to lock with this frequency, even with
a change in the reference signal due to distortions, it will
automatically detect the changes and obtain an output that
will always be equal to the needed clock frequency. So, this
type of clock generator is gaining popularity in the areas
where there can be any changes in the reference signal due to
external conditions. The work aims to implement a PLL as a
_______________________________________________________
Dr. S. Moorthi is a faculty in the Department of Electrical and
Electronics Engineering, National Institute of Technology, Trichy, India.
His area of interest includes VLSI for signal processing and Embedded
systems. (Corresponding author: srimoorthi@nitt.edu).
Dr. D. Meganathan currently works as Assistant Professor in the
Department of Electronics Engineering, MIT Campus of Anna University,
Chennai. His area of interest includes VLSI, Analog circuit design and
Signal processing.
Mr. M. Shankar and Mr. R. Sridhar completed their B.E. (ECE) at MIT,
Anna University, Chennai during 2008. Their research interest includes
ASIC design.
Dr. J. Raja paul perinbam is formerly a Professor of ECE at CEG, Anna
University, Chennai. His area of interest includes Low power VLSI design
and embedded system.
978-1-4244-9477-4/11/$26.00 ©2011 IEEE
clock generator for providing multi-phase clock signals in
Analog to Digital Converters (ADC).
There are several figures of merit that objectively
determine the PLL's performance. The three main
performance metrics considered are lock time, jittery and
power consumption. As the clock frequency of
microprocessors continues to grow, the clock timing
uncertainty due to jitter and skew becomes a much more
significant component of the overall processor cycle-time
budget. Approaches using direct, non-synchronized clocks
are expensive and difficult to implement in systems, as the
frequencies approach 1 GHz. The frequency synthesis using
a phase locked loop allows an external clock of lower
frequency, but jitter is added to the synthesized clock in the
process. For high frequency microprocessor PLLs, the jitter
is difficult to control due to the high intrinsic sensitivity of
the VCO to process, environment and digital switching noise
and to the proportionally smaller timing budget allowance
[1].
Phase-locked loops are useful for jitter reduction, skew
suppression, frequency synthesis and clock recovery in
numerous systems such as communication, wireless systems,
digital circuits and disk-drive electronics [2].
II. LITERATURE REVIEW
An on-chip clock generator for clock de-skewing and
perfect synchronization was proposed in [3]. The phase
locked loop designed was used to synchronize the output of
the color graphics display system’s three video Digital to
Analog Converters (DACs).
The PLL based clock generators were designed and
reported in [4], [5] and [6] for microprocessor, DSP and SoC
applications respectively.
An adaptive-bandwidth PLL with an improved passive
filter is described and analyzed in [7]. The operating
frequency range of the VCO is 100 MHz to 1 GHz with a
jitter value greater than 1ps.
III. THE PROPOSED PLL ARCHITECTURE
The aim of the proposed Phase Locked Loop (PLL)
architecture is to operate as a clock generator in ADC whose
clock output should have a jitter less than 1ps. A clock
generator circuit for an ADC is developed using PLL
architecture with a jitter of less than 1 ps and a center
frequency of 100 MHz. To meet the above constraint, a
phase locked loop is designed with the components
mentioned below:
(1) Precharge type phase frequency detector
(2) A charge pump
(3) Second order loop filter and
(4) Thirteen inverter stage based ring oscillator

A. Thirteen inverter stages based VCO
A Voltage Controlled Oscillator (VCO) produces an
output signal with an angular frequency that is controlled by
the input control voltage given to it. The output angular
frequency of the VCO is given below:
ωout = ωo + Kvco Vc (1)
where ωo is the VCO center frequency, Kvco is the conversion
gain of the VCO and Vc is the input control voltage of the
VCO. The output phase is equal to the integral over the
frequency variation which is expressed as:
θout (t) = ∫ Δωout(t) dt = KVCO ∫ VC(t) dt (2)
The present design focuses on a ring oscillator. Due to
the complexity involved and the large area occupied by the
LC oscillators, they are not used [8]. The ring oscillator
consists of a series of inverting amplifiers placed in a
feedback loop. It is composed of an odd number of inverters
as shown in Figure 1. It can be seen that the last output of a
chain of an odd number of inverters is the logical NOT of the
first input. This final output is asserted a finite amount of
time after the first input is asserted; the feedback of this last
output to the input causes oscillation.
V
Figure 1 Schematic of ring oscillator with inverter
stages
This circuit is a form of negative feedback, but since
each inverter has approximately a 90 degree phase shift at its
unity gain frequency, it is assured that the loop gain will be
still greater than unity when the phase shift around the loop
becomes greater than 180 degree. As a result, the circuit is
unstable and oscillations occur. At each half period the
signal will propagate around the loop with an inversion.
Assuming the output of first inverter change to be 1, this
change will propagate through all ‘n’ inverters in a time T/2,
at which the output of first inverter changes to 0; after an
additional time of T/2, the first inverter’s output will change
back to 1 and so on. Assuming each inverter has a delay of
tinv and that there are ‘n’ inverters, then
T (3)
= n * t inv
2
Thus the frequency of operation,
1 *M3
f = = ( 2 * n * t inv ) (4)
T
In a physical device with MOSFETS, the gate
capacitance must be charged before the current can flow
between the source and the drain. Thus, the output of every
inverter changes a finite amount of time after the input has
changed. From here, it can be easily seen that adding more
inverters to the chain increases the total gate delay, reducing
the frequency of oscillation.
By making the delay of the inverters to control the
voltage, the ring oscillator’s frequency can be made voltage
controlled. This is achieved by replacing the standard
inverter by a current starved inverter. The mechanism for
controlling the delay of each inverter is to limit the current
available to discharge the load capacitance of the gate. The
082
maximum discharge current of the inverter is limited by
adding an NMOS transistor in series. This transistor is
controlled by a voltage which determines the available
discharge current. Lowering the control voltage reduces the
discharge current and hence increases the high to low
transition time.
The VCO circuit used in this design is the current
starved inverter circuit. The VCO circuit consists of an odd
number of inverters which equal around thirteen inverter
stages. MOSFETs M2 and M3 operate as an inverter, while
MOSFETs M1 and M4 operate as current sources. The
current sources M1 and M4 limit the current available to the
inverters M2 and M3; in other words, the inverter is starved of
current. The drain currents of MOSFETs M5 and M7 are the
same and are set by the input control voltage. The currents in
M5 and M7 are mirrored in each inverter/current source stage.
The filter configurations used rely on the facts that the input
capacitance of the VCO is practically infinite and the input
capacitance is small compared to the capacitances present in
the loop filter. Attaining infinite resistance is usually an easy
part of the design. For the charge-pump configuration, the
input capacitance of the VCO can be added to C2. The
voltage controlled oscillator implemented using inverters is
shown in Figure 2.
M1
M5
M2
M3
M7
M4
Figure 2 Circuit diagram of voltage controlled oscillator
B. Precharge type Phase Detector
A precharge type phase detector shown in figure 3 is
used in this design.
*M1
*M4
*M2 *M5
*M7
Reset
M1
M4
M2 M5
M3 M7
Figure 3 Circuit diagram of Precharge type phase detector
Initially the reset is low, so the transistor M1 and M2 will
be ON precharging the node A to VDD. Transistor M3 will be
 083

OFF at that time. The transistor M4 and M5 will be OFF and

M7 will be ON. When VCO clock arrives (assume VCO is
faster than reference) transistor M2 will be OFF and M5 will
be ON and thus up inverter will go low. When reference
clock becomes high, down inverter will go low and reset will
go high and thereby resetting the output. Thus this precharge
type phase detector will produce pulses whose width is
proportional to the phase difference between the two clock
signals. NOR gate has been used here to reduce the width of
the reset pulse which will reduce the jitter in the output of the
PLL.
Figure 5 Model graph showing charge pump output
C. Charge pump
A charge pump is an electronic circuit that uses
capacitors as energy storage elements to create either a
higher or lower voltage source [9].

Figure 6 Circuit diagram of the implemented charge pump

D. Second order Loop filter

Figure 4 Schematic of a typical charge pump A passive second order loop filter shown in figure 7 is
used to produce the VCO control voltage.
The charge pump has two current elements and two
Vin
switches connected to them. The current elements act as a Vout

current source or a current sink. The outputs from the phase

detector are given to the two switches of the charge pump.
When the switch 1 is in the ‘ON’ state, the capacitance
connected will be charged to the value of VDD. While the
switch 2 is in the ‘ON’ state, the capacitance connected will
be discharged to the value of ground (Gnd). So when the
output 1(reference) from the phase detector is high then the
capacitance will be charged to VDD and it will take
approximately 700ns to charge to VDD. But during this
process, the value of the second output from the phase
detector which is related to the VCO is high and this turns the
second switch to the ‘ON’ position. Hence the capacitance
starts discharging to Gnd. Thus the output will be
combination of the charging and the discharging plot.
Finally, when the two output values of the phase detector are
identical then the voltage in the capacitor is maintained and
hence the PLL is said to be in the state of lock which is the
desired operation of the PLL. In the model graph shown in
Figure 5, QB is the reset pulse which takes the value of 1
whenever the VCO output turns higher. The circuit operates
in three states. If QA = QB = ‘0’, then S1 and S2 will be in the
‘OFF’ state and Vout remains constant. If QA is high and QB is
low then I1 charges the capacitance Cp and in the reverse case
when QA is low and QB is high then I2 discharges the
capacitance Cp. The circuit diagram of charge pump is shown
in Figure 6.
C1 C2
R
Figure 7 Second order passive loop filter
The time constant of the filter is equal to RC. The break
frequency (turnover frequency or cutoff frequency) is
determined using the time constant as follows:
1
fc = (5)
2 * π * R *C
The following values of the R and C components given
below are used in the filter design:
R = 33 K, C1 = 500f F, C2 = 500f F.
IV. JITTER
The difference between the ideal and actual sampling
instants in a clock signal is shown in Figure 8. The jitter in
the clock used in ADC can be indicated as a sampling time
uncertainty which will affect the Effective Number of Bits
(ENOB) of ADC as shown in Figure 9. The Signal to Noise
Distortion Ratio (SNDR) and the ENOB are determined
using the following equations:
 084

1 (6) VI. CONCLUDING REMARKS

SNDR aperture ≅ 10.log
( 2πfin σt )
2
Low jitter phase locked loop architecture is proposed as
a clock generator for analog to digital converters for the
design specifications. The range for which the PLL will be
SNDR aperture − 1.76 (7)
ENOB = locked is from 95MHz-145MHz where the center frequency
6.02 is 100MHz.
The integrated PLL architecture yields a jitter around
700 fs (is less than 1ps, as per the specification). It is verified
Signal VIN
for its operating characteristics at all process corners
ΔVIN Change in VIN during τ1
(Typical-Typical (TT), Fast-Fast (FF), and Slow-Slow (SS)).
The values obtained for various parameters are tabulated in
Table 1.
Table 1 Design summary of PLL for ADC
Parameters Values
τ1=Sampling time uncertainty
Vdd (volt) 1.8
t Id (mA) < 200
Frequency (MHz) 100
t+Δt Clock period(ns) 10
Jitter < 700fs
Figure 8 Clock signal analysis diagram Temperature Range -55ºC to 120ºC
Working Corners TT, FF, SS
18
1 MHz REFERENCES
of Bits (ENOB)
Of

16
[1] Sidropoulous S., Dean Liuz, Jaeh Kimz, Guyeon Weiz and Horowitz M.,
Number

‘Adaptive bandwidth DLLs and PLLs using regulated supply CMOS

10MHz
20MHz buffers’, IEEE symposium on VLSI circuit, digest for technical Papers,
14
Effective Number

Mountain View, CA, pp. 124-127, 2000.

50MHz
Effective

100MHz
12
[2] Fahim A.M., ‘Clock generators for SoC Processors’, Kluwer Academic
Publishers, Norwell, MA, USA, 2005.
10

[3] Chen D.L., ‘Designing On-chip Clock Generators’, IEEE Circuits and
8 Devices magazine, Vol. 8, no. 4, pp. 32-36, 1992.
1 2 4 6 8 10 12 14 16 18 20
Sampling time uncertainty (ps)

Figure 9 ENOB as a function of sampling time uncertainty [4] von Kaenel V.R., ‘A High-Speed, Low-Power Clock Generator for a
Microprocessor Application’, IEEE Journal of Solid-state circuits, Vol. 33,
V. SIMULATION RESULTS No. 11, pp. 1634-1639, 1998.

The components opted for the design of PLL [5] Nilsson P. and Torkelson M., ‘A Monolithic Digital Clock-Generator
architecture for ADC is implemented and simulated using for On-Chip Clocking of Custom DSPs’, IEEE Journal of Solid-state
CADENCE analog design environment. Its operating circuits, Vol. 31, No. 5, pp. 700-706, 1996.
characteristics are verified using 0.18 µm CMOS technology
and it works for its designed features at all process corners. [6] Chen Jia and Boan Liu, ‘A 250MHz clock for SOC systems’,
Once the PLL gets locked, the eye diagram is plotted by Proceedings of 5th International Conference on ASIC, Beijing, China, Vol.
overlapping the output waveform and jitter is measured as 2, pp. 721-724, 2003.
shown in Figures 10.
[7] Song Ying, Wang Yuan, Jia Song, Zhao Baoying and Ji Lijiu, ‘Design of
Low Jitter Adaptive-Bandwidth Charge Pump PLL with assive Filter’, 7th
International Conference on ASIC, Guilin, China, pp. 319-322, 2007.

[8] Chang-Hyeon Lee, Cornish J., McClellan K. and Choma J. Jr., ‘Design
of Low Jitter PLL for Clock Generator with supply noise insensitive VCO’,
IEEE International Symposium on Circuits and Systems, Monterey, CA, Vol.
1, No. 31, pp. 233-236, 1998.

[9] Boerstler D.W., ‘A Low-Jitter PLL Clock Generator for Microprocessors

with Lock Range of 340-612 MHz’, IEEE Journal of Solid-state circuits, Vol.
34, No. 4, pp. 513-519, 1999.

Figure 10 Eye diagram-I for jitter measurement