PCI-EXPRESS

(Peripheral Component Interconnect)

PCI Express provides a high-speed, high-performance, point-to-point, dual simplex, differential signaling
Link for interconnecting devices. Data is transmitted from a device on one set of signals, and received on
another set of signals.

Root Complex:

The Root Complex denotes the device that connects the CPU and memory subsystem to
the PCI Express fabric. It may support one or more PCI Express ports. The root complex
generates transaction requests on the behalf of the CPU. It is capable of initiating configuration
transaction. . Root complex transmits packets out of its ports and receives packets on its ports
which it forwards to memory. A multi-port root complex may also route packets from one port to
another port but is NOT required by the specification to do so.

Simple PCI Structure

Endpoints :
Endpoints are devices other than root complex and switches that are requesters or completers of
PCI Express transactions.
They are peripheral devices such as Ethernet, USB or graphics devices. Endpoints initiate
transactions as a requester or respond to transactions as a completer.

Requester

A Requester is a device that originates a transaction in the PCI Express fabric. Root complex and
endpoints are requester type devices.

Completer

A Completer is a device addressed or targeted by a requester. A requester reads data from a

completer or writes data to a completer. Root complex and endpoints are completer type devices.

Port

A Port is the interface between a PCI Express component and the Link. It consists of differential
transmitters and receivers.

Protocol Architecture for PCI-Express :

Transaction layer

The transaction layer receives read and write requests from the software layer and creates request
packets for transmission to the link layer.

All requests are implemented as split transactions and some of the request packets will need a
response packet. The transaction layer also receives response packets from the link layer and
matches these with the original software requests.

Each packet has a unique identifier that enables response packets to be directed to the correct
originator. The packet format supports 32bit memory addressing and extended 64bit memory
addressing.
The primary responsibility of Transaction Layer is the assembly and disassembly of Transaction
Layer Packets. These Transaction Layer Packets (TLPs) are forwarded from one link to another
as necessary, subject to the routing mechanisms and rules.

Transaction Types
The various transaction types supported by the PCI Express compatible devices are:

 Read
 Write
 Base Line (For messages)
 Vendor Specific

Addressing Formats
As transactions are carried out between PCI Express requesters and completers,
four separate address spaces are used: Memory, IO, Configuration, and Message. The basic
use of each address space is described

Table: 1 PCI Express Address Space And Transaction Types

Address Space Transaction Purpose
Types
Memory Read, Transfer data to or from a location in the system memory map

Write
IO Read, Transfer data to or from a location in the system IO map

Write
Configuration Read, Transfer data to or from a location in the configuration space of a
PCI-compatible device.
Write
Message Baseline, General in-band messaging and event reporting (without
consuming memory or IO address resources)
Vendor-
specific

Possible types of Transactions

There are two types of transactions which are supported by the PCI Express
compatible devices. They are:
Posted type transactions
These are the type of transactions which do not require completion
of a transaction.
Non-Posted type transactions
These are the type of transactions which require completion
of a transaction. To mitigate the penalty of the request-completion latency, messages and
some write transactions in PCI Express are posted, meaning the write request (including
data) is sent, and the transaction is over from the requester's perspective as soon .
Table: 2 PCI Express Posted and Non-Posted Transactions
Request How Request Is Handled
Memory Write All Memory Write requests are posted. No completion is expected
or sent.
Memory Read All memory read requests are non-posted. A Completion With Data
(CplD(Completion With Data) or CplDLK (Memory Read lock
Memory Read Lock Completion With Data) ) will be returned by the completer with
requested data and to report status of the memory read
IO Write All IO Write requests are non-posted. A completion without data
(Cpl) will be returned by the completer to report status of the IO
write operation.
IO Read All IO read requests are non-posted. A completion with data
(CplD) will be returned by the completer with requested data and
to report status of the IO read operation.
Configuration Write All Configuration Write requests are non-posted. A completion
without data (Cpl) will be returned by the completer to report status
Type 0 and Type 1 of the configuration space write operation.
Configuration Read All configuration read requests are non-posted. A completion with
data (CplD) will be returned by the completer with requested data
Type 0 and Type 1 and to report status of the read operation.
Message While the routing method varies, all message transactions are
handled in the same manner as memory writes in that they are
Message With Data considered posted requests

Read and Write Operation:

TLPs are pretty simple to interpret. Here's a general view of their structure.

The header contains 3 or 4 DWs but the most important fields are part of the first DW.

The "Fmt" field tells how long is the header, and if a data payload is present.