Department of Electrical Engineering

IIT Kanpur
Course: EE610 Home Assignment # 1 2009-10-I

Data for Q4-Q8: µn=350 cm2/v s, µp=100 cm2/v s , ɛr sio2=3.9, tox=9 nm,

ɛ0=8.85x10-14 F/cm, γ= 0.45 v 1/2, λN=0.1 v-1, λp=0.2 v-1, 2øf =0.9 v, VDD=3v.

Q.1.

Determine the bias current of M1 in Fig.Q1, Assume VTH=0.5v, W/L=5/0.18,

µn Cox=100µA/v2, λ=0.What is the maximum allowable value of RD for M1 to
remain in saturation?

Q.2

In circuit of Fig Q1, assume M1 is in saturation and RD=2.5k. Compute

(a) The maximum allowable value of W/L, and
(b) The minimum allowable value of RD (with W/L=5/0.18). Assume λ=0.

Q.3

Determine the bias current of M1 in Fig.Q3 assuming VTH = -0.5, W/L=5/0.18,

µp Cox=50µA/v2, λ=0, R1=20k, R2=15k. What is the maximum allowable value
of RD for M1 to remains in saturation?
Q.4

For the circuit shown in Fig Q4, calculate the small-signal voltage if
(W/L) 1= 50µm/0.5µm, (W/L) 2=10µm/0.5µm. ID1=ID2=0.5mA. Calculate the
voltage gain if the load is diode-connected PMOS. Ignore CLM.

Q.5

Solve Q.4 taking into account effect of CLM.

Q.6

In the circuit shown in Fig Q6 assume (W/L) 1=50µm/0.5µm,

(W/L) 2=50µm/2µm, ID1=ID2=0.5mA when both the devices are in saturation.
(a) Calculate the small signal gain.

(b) Calculate the maximum output voltage swing while both devices are in
saturation.

Q.7

The source follower circuit of Fig.Q7 can operate as level shifter. Suppose the

circuit is designed to shift the voltage level by 1v, i.e.Vin-Vout= 1v.

(a) Calculate the dimensions of M1 and M2 if ID1=ID2=0.5mA,

VGS1-VGS2=0.5v and λ=γ=0.

(b) Repeat part (a) if γ=0.45V1/2 and Vin =2.5v. What is the minimum input
Voltage for which M2 remains saturated.
Q.8

In the cascode stage of Fig.Q8 assume (W/L) 1=50µm/0.5µm,

(W/L) 2=10µm/0.5µm, ID1=ID2=0.5mA and RD= 1k.
(a) Choose Vb such that M1 is 50 mV away from triode region.
(b) Calculate the small signal voltage gain.