24 SECTION 11 VERILOG HDL ASICS...

THE COURSE

11.8.3 Disable
Key terms and concepts: The disable statement stops the execution of a labeled sequential
block and skips to the end of the block • difficult to implement in hardware

11.8.4 Fork and Join

Key terms and concepts: The fork statement and join statement allows the execution of two or
more parallel threads in a parallel block • difficult to implement in hardware

11.9 Logic-Gate Modeling

Key terms and concepts: Verilog has a set of built-in logic models and you may also define
your own models.
ASICs... THE COURSE 11.9 Logic-Gate Modeling 25

11.9.1 Built-in Logic Models

Key terms and concepts: primitives: • strong drive
strength is the default • the first port of a primitive gate is always the output port • remaining
ports are the input ports

Definition of the Verilog primitive 'and' gate

'and' 0 1 x z
0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x

11.9.2 User-Defined Primitives

Key terms and concepts: a user-defined primitive (UDP) uses a truth-table specification • the
first port of a UDP must be an port (no vector or ports) • inputs in a UDP truth
table are , , and • any input is treated as an • default output is • any
next state goes between an input and an output in UDP table • shorthand notation for levels •
represents a change from a to b • represents a rising edge • shorthand notations for
edges
26 SECTION 11 VERILOG HDL ASICS... THE COURSE

11.10 Modeling Delay

Key terms and concepts: built-in delays • ASIC cell library models include logic delays as a
function of fanout and estimated wiring loads • after layout, we can back-annotate • delay calcu-
lator calculates the net delays in Standard Delay Format, SDF • sign-off quality ASIC cell
libraries

11.10.1 Net and Gate Delay

Key terms and concepts: minimum, typical, and maximum delays • first triplet specifies the
min/typ/max rising delay ( or or to ) and the second triplet specifies the falling
ASICs... THE COURSE 11.10 Modeling Delay 27

delay (to ) • for a high-impedance output, we specify a triplet for rising, falling, and the delay
to transition to (from or ), the delay for a three-state driver to turn off or float

11.10.2 Pin-to-Pin Delay

Key terms and concepts: A specify block allows pin-to-pin delays across a module •
specifies a parallel connection (or parallel path) • and must have the same number of bits
• specifies a full connection (or full path) • every bit in is connected to • and may
be different sizes • state-dependent path delay
28 SECTION 11 VERILOG HDL ASICS... THE COURSE

11.11 Altering Parameters

Key terms and concepts: parameter override in instantiated module • parameters have local
scope • defparam statement and hierarchical name