18 Our Mathematical Grandmother -

The MathCo 8087

The four basic arithmetical operations with integers are already integrated on the 8086/88. It is
not surprising that the 8086/88 can handle neither floating-point numbers nor transcendental
functions; this is carried out by the mathematical coprocessor 8087. It can enhance the perform-
ance up to a factor of 100, when compared to software emulations. Additionally, the 8087
supports an SOSS/SS CPU in maximum mode with 68 new mnemonics.

18.1 8087 Number Formats and Numerical Instruction Set

As a mathematical coprocessor, the 8087 can process floating-point numbers directly. In the
same way as the 80286 and its successors, the 8087 represents all numbers in the temporary real
format according to the IEEE standard. Figure 6.3 (Chapter 6) shows the number formats that
are supported by the 8087. Unfortunately, the 8087 does not implement the IEEE standard for
floating-point numbers in a very strict way (not very surprising - the 8087 was available before
the standard). The 8087 numeric instruction set is slightly smaller than that for an i387 or
80287XL; for example, the FSETPM (set protected mode) instruction is (of course) missing.
Further, no functions for evaluating sine and cosine are available. But they can be constructed
with the help of the tangent. A detailed list of all 8087 instructions is given in Appendix Cl.

18.2 8087 Pins and Signals

Like the 8086/88, the 8087 has 40 pins in all for inputting and outputting signals and supply voltages.
Usually, the 8087 comes in a 40-pin DIP package. Figure 18.1 shows the pin assignment of the 8087.

ADlS-ADO (I/O)
Pins 39, 2-16

These 16 connections form the 16 data bits when the 8087 is reading or writing data, as well as
the lower 16 address bits for addressing memory. As is the case with the 8086, these 16 pins
form a time-divisionally multiplexed address and data bus.

A19-A16/S6-S3 (II01
Pins 35-38

These four pins form the four high-order bits of the address bus, as well as four status signals,
and form a time-divisionally multiplexed address and control bus. During bus cycles controlled
by the 8087, the S6, S4 and S3 signals are reserved and held on a high level. Additionally, S5
is then always low. If the 8086/88 is controlling the bus then the 8087 observes the CPU activity
using the signals at pins 56 to S3.

471
472 Chapter 16

AD15
Al+%3
Al 7lS4
A181S5
A19/S6
ms7
- -
RWGTI
: INT

8087

Figure 18.1: 8087 pin assignment. The 8087 comes itt a standard DIP pncknge cornprisiq 40 pins.
J

BHEIS7 (I/O)
Pin 3 4

This bus high enable signal indicates whether a byte is transferred on the high-order part ADIS-
AD8 of the data bus. When the 8086/88 is in control of the bus the 8087 observes the signal at
pin 57 supplied by the CPU.

BUSY (0)
Pin 23

If the signal at this pin is high then the 8087 is currently executing a numerical instruction.
Usually, BUSY is connected to the TEST pin of the 8086/88. The CPU checks the TEST pin and
therefore the BUSY signal to determine the completion of a numerical instruction.

CLK (I)
Pin 19

CLK is the clock signal for the 8087.

INT (0)
Pin 32

The signal output at this pin indicates that during the execution of a numerical instruction 1”
the 8087, a non-maskable exception has occurred, for example an overflow. The output of tkr
signal can be suppressed by interrupt masking in the 8087.
Our Mathematical Grandmother The MathCo 8087 473

QSl, QSO (I, I)

Pins 24, 25

The signals at these pins indicate the status of the prefetch queue in the 8086/W Thus, the 8087
can observe the CPU’s prefetch queue. For (QSl, QSO) the following interpretations hold:

(00) the prefetch queue is not active;

(01) the first byte of the opcode in the prefetch queue is processed:
(10) the prefetch queue is cancelled;
(11) a next byte of the opcode in the prefetch queue is processed.

READY (I)
Pin 22

The addressed memory confirms the completion of a data transfer from or to memory with a
high-level signal at READY. Therefore, like the 8086/88, the 8087 can also insert wait cycles if
the memory doesn’t respond quickly enough to an access.

RESET (I)
Pin 21

If this input is high for at least four clock cycles, the 8087 aborts its operation immediately and
carries out a processor reset.
- -
RQ/GTO (I/O)
Pin 31

The 8087 uses this pin to get control of the local bus -from the- SOS6/8S so as to execute its own
memory cycles. RQ/GTO is connected to the CPU’s RQ/GTl pin. Normally, the 8086/88 is in
control of the bus to read instructions and data. If the 8087 accesses the memory because of a
LOAD or STORE instruction, it takes over control of the local bus. Therefore, both the 8086/88
and the 8087 can act as a local busmaster.
- -
RQ/GTl (I/O)
Pin 33

This pin may be used by another local busmaster to get control of the local bus from the 8087.

% zl, so (I/O)
Pins 28-26

These three control signals indicate the current bus cycle. For the combinations (S2, Sl, SO) the
following interpretations hold for bus cycles controlled by the 8087:

(OXX) invalid;
(1001 invalid;
(101) data is read from memory;
(110) data is written into memory;
1111) passive state.
474 Chapter 18

If the SO86/88 is controlling the bus, the 8087 observes the CPU activity using the signals at pins
S2toSO.

vcc (I)
Pin 40

This pin is supplied with the supply voltage of +5 V.

GND
Pins 1, 20

These pins are grounded (usually at 0 V)

18.3 8087 Structure and Functioning

The control unit largely comprises a unit for bus control, data buffers, and a prefetch queue. The
prefetch queue is identical to that in the 8086/88 in a double sense:

- It has the same length. Immediately after a processor reset the 8087 checks by means of the
BHE/S7 signal whether it is connected to an 8086 or 8088. The 8087 adjusts the length of its
prefetch queue according to the length in the 8086 (six bytes) or 8088 (four bytes), respectively.
_ The prefetch queue contains the same instructions. By synchronous operation of the 8086/
88 and 8087, the same bytes (and therefore also the same instructions) are present in the
prefetch queues of both CPU and coprocessor.

Thus, the CU of the coprocessor attends the data bus synchronously to and concurrently with
the CPU and fetches instructions to decode. Like the other 80x87 coprocessors, the 8087 also has
a status, control and tag word, as well as a register stack with eight BO-bit FP-registers. Addi-
tionally, the two registers for instruction and data pointers are implemented.

The status word format is shown in Figure 18.2. If bit B is set the numerical unit NU is occupied
by a calculation or has issued an interrupt that hasn’t yet been serviced completely. If the IX bit
is set, a non-maskable exception has occurred and the 8087 has activated its INT output. In the
PC/XT an NM1 is issued. (Beginning with the 80287, IR has been replaced by ES = error status.)
The meaning of the remaining bits C3-CO, TOP, PE, LIE, OE, ZE, DE and ZE is the same as for
the 80287.

The 8087 generates an exception under various circumstances, but some exceptions may be
masked. Further, you are free to define various modes for rounding, precision and the repre-
sentation of infinite values. For this purpose, the 8087 has a control word, shown in Figure 15.3.
Our Mathematical Grandmother - The MathCo 8087 475

Figure 18.3: 8087 control word

The IC bit controls the processing of infinite values. Projective infinity leads to only one value,
namely m. If you set IC equal to 0, then the 8087 operates with affine infinity, and two infinite
values +a0 and --m are possible. Beginning with the 80287XL, the IC bit is only present on
compatibility grounds because the IEEE standard allows affine infinity only. With the M bit, you
can mask interrupts globally, in which case the 8087 ignores all exceptions and doesn’t execute
an on-chip exception handler. This capability has also been removed with the 80287. The func-
tion of the remaining bits PM, UM, OM, ZM, DM and IM is the same as in the i387 (Section 6.5).

You will find the 8087 tag word in Section 6.5; it is identical to that in the i387. Moreover, the
memory images of the instruction and data pointers match those for the 16-bit real format in the
i387. They are shown in Figure 6.10.

18.4 8087 Memory Cycles

An interesting difference between the 8087 and all later 80x87 model occurs in the memory
access: the 8087 can access memory on its own; there are no I/O cycles between CPU and
coprocessor.

The 8086/88 distinguishes instructions with memory access from pure arithmetical instructions
handed by the 8087. The CPU calculates the operand address according to the addressing
scheme indicated, and then the 8086/88 executes a dummy read cycle. This cycle differs from a
normal read cycle only in that the CPU ignores the data supplied by the memory. If the CPU
recognizes a coprocessor instruction without a memory operand, it continues with the next
struction after the 8087 has signalled via its BUSY pin that it has completed the current
struction.

he 8087 also behaves differently for instructions with and without a memory operand. In the
rst case, it simply executes an instruction such as FSQRT (square root of a floating-point
umber). For an instruction with a memory operand it uses the 8086/88 dummy read cycle in
re following way:

Fetching an operand from memory: the 8087 reads the address supplied by the CPU in the
dummy read cycle via the address bus and stores it in an internal temporary register. Then
the 8087 reads the data word that is put onto the data bus by the memory. If the operand
is longer than the data word transferred within this read cycle, the 8087 requests control of
the local bus from the 8086/88. Now the 8087 carries out one or more succeeding read cycles
on its own. The coprocessor uses the memory address fetched during the course of the
dummy read cycle and increments it until the whole memory operand is read. For example,
in the case of the 8088/87 combination, eight memory read cycles are necessary to read a
476 Chapter 18

floating-point number in long real format. Afterwards, the 8087 releases control of the loc.ll
bus to the 8086/88 again.

- Writing an operand into memory: in this case the coprocessor also fetches the address output
by the CPU in a dummy read cycle, but ignores the memory data appearing on the data bus,
Afterwards, the 8087 takes over control of the local bus and writes the operand into memory,
starting with the fetched address, in one or more write cycles.

Because of the dummy read cycle the 8087 doesn’t need its own addressing unit to determine
the effective address of the operand with segment, offset and displacement. This is advanta-
geous because the 8087, with its 75 000 transistors, integrates far more components on a single
chip compared to the 28 000 transistors of the 8086/88, and space is at a premium (remember
that the 8087 was born in the 1970s).

The 8087 also uses the 8086/88 addressing unit if new instructions have to be fetched into the
prefetch queue. The CPU addresses the memory to load one or two bytes into the prefetch
queue. These instruction bytes appear on the data bus. The processor status signals keep the
8087 informed about the prefetch processes, and it monitors the bus. If the instruction bytes
from memory appear on the data bus, the 8087 (and also the 8086/88, of course) loads them into
the prefetch queue.

For the data transfer between memory and coprocessor, no additional I/O bus cycles between
CPU and 8087 are necessary. Therefore, the LOAD and STORE instructions require more time
on an 80287. Don’t be surprised if, for pure mathematical applications, a 10 MHz XT with an
8087 coprocessor is nearly as fast as a 10 MHz AT with an 80287. The 80287 (without XL) runs
only at two-thirds of the CPU speed, thus at 6.67MHz. Moreover, it requires the additional
I/O bus cycles between CPU and 80287 when accessing memory. However, the 80286/80287
combination cancels this disadvantage with a more effective bus cycle lasting for only two clock
cycles per data transfer at zero wait states, compared to the four clock cycles of the SO86/8O87
combination. In the end, both systems give about the same performance.

18.5 8086/8087 System Configuration

Figure 18.4 shows typical wiring oi the 8087 coprocessor and CPU 8086/88. As they are
busmasters, both chips access the same local bus which is connected to memory, the I/O a&
dress space and the bus slots via the 8288 bus controller. The 8086/88 and the 8087 read and
decode the same instruction stream at the same speed, thus they operate s~&zrorrozts/~~ and are
supplied with the same clock signal (CLK) by the 8284 clock generator. All higher coprocessol-s,
however, such as the 80287,387, etc., run asychronously to the CPU. For synchronous operntloll
of the 8086/88 and 8087, the 8087 must always know the current state of the 8086/88.

The 8087 can process its instructions independently of the CPU. Even concurrent (parall
execution of instructions is possible, but here the problem of resynchronization arises dft’2r
completion of the coprocessor instruction. After decoding the current ESC instruction, the 8(N~l/
88 would prefer to execute the next instruction at once, but cannot do so because the CPU 11~‘~
to wait for the coprocessor. Because of this, the BUSY pin of the 8087 is connected to tllc‘
Our Mathematical Grandmother - The MathCo 8087 477

Figure 18.4: 8086/8087 system configw&m. The 8087 hnnnor~izes especinlly well with the 8086/88, and cm
therefore be connected to the 8086jSS without difficulties. The 8087 uses the same bus controller, the same clock
generator, nnd the same interrupt controller as the CPU.

TEST pin of the 8086/88. When the coprocessor executes an instruction it activates the BUSY
signal. When it has completed the instruction, it deactivates the signal. The WAIT instruction
of the 8086/88 causes the CPU to check the TEST pin continuously to observe the BUSY state
of the coprocessor. Only when the 8087 has deactivated BUSY to signal to the 8086/88 that the
current instruction is completed and the 8087 is ready to accept further numeric instructions
does the CPU continue with the next instruction. Via the QSO and QSl pins, the 8087 detects the
status of the 8086/88’s prefetch queue to observe the CPU’s operation. Thus, the 8086/88 and
8087 always operate synchronously.

If an error or an exception occurs during a numerical calculation in the coprocessor, such as

overflow or underflow, the 8087 activates its INT output to issue a hardware interrupt request
to the CPU. Usually, the INT signal of the 8087 is managed by an interrupt controller (the 8259A,
for example) and then applied to the 8086/88. But the PC/XT does it in another way: the 8087
hardware interrupt request is supplied to the NM1 input of the 8086/88. The PC/XT has only
one 8259A PIC and must therefore save IRQ channels. Note that besides the coprocessor inter-
rupt, an error on an extension adapter or a memory parity error may also issue an NM1 corres-
ponding to interrupt 2. Thus, the interrupt handler must be able to locate the source of an NMI.

Figure 18.4 demonstrates that both the 8086/88 and the 8087 can access the local bus, to read
data from memory, for example. 8086/88 instructions such as MOV reg, mem or the LOAD
instruction of the 8087 carry out a memory access. Thus there are two busmasters, each using
the local bus independently. A simultaneous access of the local bus by the CPU and coprocessor
would give rise to a conflict between them, with disastrous consequences. Therefore, only one
of these two processors may control the local bus, and the transfer- of control
- between them must
be carried out in a strictly defined way. Because of this, the RQ/GTl pins of the 8086/88
- - _
and RQ/GlO pins of the 8087 are connected. From the description above _ you_ can see that these
Pins serve to request and grant local bus control. The 8087 uses the RQ/GTO pin to get control
478 Chapter 18

- -
of the local bus for data transfers to and from memory. The RQ/GTl pin is available for other
busmasters, for example the I/O 8299 coprocessor. Therefore, CPU and coprocessor may altern-
ate in controlling the local bus. The 8087 bus structure and its bus control signals are equivalent
to those of the 8086/88.