Experiment No.

14
Aim: Design and simulate of Sequence Detector.
Tools used: Xilinx ISE Design suite 14.7
Theory:
Sequence Detector:
A sequence detector is a model used to design sequential logic circuits. It is conceived as an
abstract machine that can be in one of a finite number of states. The machine is in only one state
at a time; the state it is in at any given time is called the current state. It can change from one
state to another when initiated by a triggering event or condition, this is called a transition. A
particular sequence detector is defined by a list of its states, and the triggering condition for each
transition. It can be implemented using models like Mealy and Moore machine. As output is
dependent on excitation in mealy machine there are chances of glitches in the output. In order to
avoid this problem moore machine can be implemented
(a) Sequence 1:1101:
1.Truth table of Non Overlapping sequence using mealy machine :

Present state input Next state output

Q1 Q0 x Q1(+) Q0(+) Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 0 1
Table 14.1 Truth table of 1101 Sequence Detector of non over lapping type

Truth table of Overlapping sequence using mealy machine :

Present state input Next state output

Q1 Q0 x Q1(+) Q0(+) Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 0 1
Table 14.2 Truth table of 1101 Sequence Detector of overlapping type

1
Synthesis:

Fig 14.1 State diagram 1101 Sequence Detector of non overlapping type

SET SET
D1 Q D0 Q
0 Y
1

CLR Q1 CLR Q
0

clr

Fig 14.2Block diagram 1101 Sequence Detector of non overlapping type

Design equation:
̅̅̅̅+𝑄1
D1=Q1𝑄0 ̅̅̅̅Q0X

D0=𝑄1. 𝑄0.X+Q1𝑄0.𝑋
Y=Q1Q0X

Fig 14.3 State diagram 1101 Sequence Detector of overlapping type

2
 x

SET
D
SET
Q D Q
1 0

CLR Q CLR Q

clk
Fig 14.4 Block diagram 1101 Sequence Detector of overlapping type

Design equation:
̅̅̅̅+𝑄1
D1=Q1𝑄0 ̅̅̅̅Q0X

D0=x(𝑄1 ⊕ 𝑄0+Q1𝑄0 ⊕ 𝑥

Y=Q1Q0X

2.Truth table of Non Overlapping sequence using moore machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 0 0
0 1 1 0 0 0 0 0
0 1 1 1 1 0 0 0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 1

Table 14.3Truth table of 1101 Sequence Detector of non over lapping type using moore machine

3
 Truth table of Overlapping sequence using moore machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 0 0
0 1 1 0 0 0 0 0
0 1 1 1 1 0 0 0
1 0 0 0 0 0 0 1
1 0 0 1 0 1 0 1
Table 14.4Truth table of 1101 Sequence Detector of overlapping type using moore machine

Synthesis:

Fig 14.5State diagram 1101 Sequence Detector of non overlapping type using moore machine

SET SET SET

D Q D Q D Q
2 1 0

CLR Q CLR Q CLR Q

Y

Fig 14.6Block diagram 1101 Sequence Detector of non overlapping type using moore machine

4
Design equation:
D2=Q1Q0X

D1=Q1𝑄0+Q0𝑄1.X

D0=Q1𝑄0. 𝑋+𝑄0. 𝑄1.X+Q2X

Y=Q2

Fig 14.7State diagram 1101 Sequence Detector of overlapping type using moore machine

SET SET SET

D Q D Q D Q
2 1 0

CLR Q CLR Q CLR Q

Y

Fig 14.8Block diagram 1101 Sequence Detector of overlapping type using moore machine

Design equation:
D2=Q1Q0X

D1=Q1𝑄0+Q0𝑄1.X+Q2X

D0=Q1𝑄0. 𝑋+𝑄2. 𝑄1.𝑄0.X

Y=Q2

5
(b) Sequence 2: 1010110:
1.Truth table of Non Overlapping sequence using mealy machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0
1 0 1 0 1 0 0 0
1 0 1 1 1 1 0 0
1 1 0 0 0 0 0 1
1 1 0 1 0 0 0 0

Table 14.5 Truth table of 1010110Sequence Detector of non over lapping type

Truth table of Overlapping sequence using mealy machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 0
1 1 0 0 0 0 0 1
1 1 0 1 0 0 1 0

Table 14.6 Truth table of 1010110Sequence Detector of overlapping type

6
Synthesis:

Fig 14.9State diagram 1010110Sequence Detector of non overlapping type

SET SET SET

D Q D Q D Q
Y
2 1 0

CLR Q CLR Q CLR Q

clk

Fig 14.10Block diagram 1010110Sequence Detector of non overlapping type

Design Equation:

D2=Q2𝑄1. 𝑋+𝑄1𝑄0. 𝑋+Q2Q0

D1=𝑄2Q1. 𝑄0. 𝑋+𝑄2. 𝑄1𝑄0. 𝑋+Q2Q0x

D0= 𝑄2.X+𝑄1𝑄0. 𝑋

Y=Q2Q1.𝑄0.𝑋

7
 Fig 14.11State diagram 1010110Sequence Detector of overlapping type

Fig 14.12Block diagram 1010110Sequence Detector of overlapping type

Design Equation:

D2=Q2𝑄1. 𝑋+𝑄1𝑄0. 𝑋+Q2Q0

D1=𝑄2Q1. 𝑄0. 𝑋+𝑄2. 𝑄1𝑄0. 𝑋+Q2Q0x+Q2Q1Q0

D0= 𝑄2.X+𝑄1. 𝑋+𝑄0.X

Y=Q2Q1.𝑄0.𝑋

8
 2.Truth table of Non Overlapping sequence using moore machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0
1 0 1 0 1 0 0 0
1 0 1 1 1 1 0 0
1 1 0 0 1 1 1 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 1 0 0 1 1

Table 14.7Truth table of 1010110 Sequence Detector of non over lapping typeusing moore machine

Truth table of Overlapping sequence using moore machine :

Present state input Next state output

Q2 Q1 Q0 x Q2(+) Q1(+) Q0(+) Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0
0 1 0 0 0 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0
0 1 1 1 0 0 1 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0
1 0 1 0 1 0 0 0
1 0 1 1 1 1 0 0
1 1 0 0 1 1 1 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 1 0 1 1 1

Table 14.8 Truth table of 1010110Sequence Detector of overlapping type using moore machine

9
Synthesis:

Fig 14.13State diagram 1010110Sequence Detector of non overlapping type using moore machine

Design Equation:

D2=Q2𝑄1. 𝑋+Q2Q1.𝑄0.𝑋+Q2.𝑄1.Q0+𝑄2.Q1Q0.𝑋

D1=𝑄2Q1. 𝑄0. 𝑋+𝑄2. 𝑄1𝑄0. 𝑋+Q2.𝑄1.Q1.X+Q2Q1.𝑄0.𝑋

D0=Q2Q1. 𝑄0+Q2𝑄0.X+Q1X+𝑄2.X
Y=Q2Q1Q0

SET SET SET

D Q D Q D Q Y
2 1 0
CLR Q CLR Q CLR Q

clk

Fig 14.14Block diagram 1010110 Sequence Detector of non overlapping type using moore machine

10
 Fig 14.15State diagram 1010110 Sequence Detector of overlapping type using moore machine

Design Equation:

D2=Q2𝑄1. 𝑋+Q2Q1.𝑄0.𝑋+Q2.𝑄1.Q0+𝑄2.Q1Q0.𝑋

D1=𝑄2Q1. 𝑄0. 𝑋+𝑄2. 𝑄1𝑄0. 𝑋+Q2Q0x+Q2Q1.𝑄0.𝑋

D0=Q2Q1. 𝑄0+Q2𝑄0.X+Q1X+𝑄2.X
Y=Q2Q1Q0

SET SET SET

D Q D Q D Q

2 1 0
CLR Q CLR Q CLR Q

clk

Fig 14.16Block diagram1010110 Sequence Detector of overlapping type using moore machine

11
Verilog Code:
(a)Verilog code for Sequence 1101:
4 bit Non Overlapping sequence using mealy machine:
1.Dataflow module coding :
module datamealy41( input clk, input clr, input x,
output [0:1] Q, output y
);
wire w0,w1;
assign w0= (~Q[0]&Q[1]&x)|(Q[0]&~Q[1]);
assign w1= (~Q[0]&~Q[1]&x)|(Q[0]&~Q[1]&x);
assign y= (Q[0]&Q[1]&x);

dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
endmodule
module dff(input clk,input clr, input d,output reg Q);
initial begin Q=1'b0; end
always@(posedgeclk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule
2.Behavioural module coding:
module mealy4bitnonover( input clk, input x, output reg y,
output reg [1:0] outstate
);
reg [1:0] state;
initial begin {state,y}=3'b000; end
always @(posedgeclk)
begin
casex ({state,x})
3'b000: begin {state,y}=3'b000; end
3'b001: begin {state,y}=3'b010; end
3'b010: begin {state,y}=3'b000; end
3'b011: begin {state,y}=3'b100; end
3'b100: begin {state,y}=3'b110; end
3'b101: begin {state,y}=3'b100; end
3'b110: begin {state,y}=3'b000; end
3'b111: begin {state,y}=3'b001; end
endcase
assign outstate=state;

12
end
endmodule

4 bitOverlapping sequence using mealy machine:

1.Dataflow module coding :
module datamealy42( inputclk, input clr, input x,
output [0:1] Q, output y
);
wire w0,w1;
assign w0= (~Q[0]&Q[1]&x)|(Q[0]&~Q[1]);
assign w1= ((Q[0]^~Q[1])&x)|((Q[1]^~x)&Q[0]);
assign y=(Q[0]&Q[1]&x);

dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedgeclk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule

2.Behavioural module coding:

module melay2(input clk, input x, output reg y,
output reg [1:0] outstate
);
reg [1:0] state;
initial begin {state,y}=3'b000; end
always @(posedgeclk)
begin
casex ({state,x})
3'b000: begin {state,y}=3'b000; end
3'b001: begin {state,y}=3'b010; end
3'b010: begin {state,y}=3'b000; end
3'b011: begin {state,y}=3'b100; end
3'b100: begin {state,y}=3'b110; end
3'b101: begin {state,y}=3'b100; end
3'b110: begin {state,y}=3'b000; end
3'b111: begin {state,y}=3'b011; end
endcase
assign outstate=state;
end

13
endmodule

4 bitNon Overlapping sequence using moore machine:

1.Dataflow module coding :

module datamoore41( input clk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;
assign w0= (Q[1]&Q[2]&x);
assign w1= (~Q[1]&Q[2]&x)|(Q[1]&~Q[2]);
assign w2= (Q[1]&~Q[2]&~x)|(~Q[1]&~Q[2]&x)|(Q[0]&x);
assign y=Q[0];
dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedgeclk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule
2.Behavioural module coding:
module moore1( inputclk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end
always @(posedgeclk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0000; end
4'b0011: begin {state,y}=4'b0100; end
4'b0100: begin {state,y}=4'b0110; end
4'b0101: begin {state,y}=4'b0100; end
4'b0110: begin {state,y}=4'b0000; end
4'b0111: begin {state,y}=4'b1000; end
4'b1000: begin {state,y}=4'b0001; end
4'b1001: begin {state,y}=4'b0011; end

14
endcase
outstate=state;
end
endmodule

4 bitOverlapping sequence using moore machine:

1.Dataflow module coding :
module datamoore41(
input clk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;
assign w0= (Q[1]&Q[2]&x);
assign w1= (Q[1]&~Q[2])|(~Q[1]&Q[2]&x)|(Q[0]&x);
assign w2= (Q[1]&~Q[2]&~x)|(~Q[0]&~Q[1]&~Q[2]&x);
assign y=Q[0];
dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedgeclk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule

2.Behavioural module coding:

module moore2(input clk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end
always @(posedgeclk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0000; end
4'b0011: begin {state,y}=4'b0100; end
4'b0100: begin {state,y}=4'b0110; end
4'b0101: begin {state,y}=4'b0100; end
4'b0110: begin {state,y}=4'b0000; end
4'b0111: begin {state,y}=4'b1000; end

15
4'b1000: begin {state,y}=4'b0001; end
4'b1001: begin {state,y}=4'b0101; end
endcase
outstate=state;
end
endmodule
(b)Verilog code for Sequence 1010110:
7 bit Non Overlapping sequence using mealy machine:
1.Dataflow module coding :
module datamealy71( input clk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;
assign w0= (Q[0]&~Q[1]&x)|(Q[0]&Q[2])|(Q[1]&Q[2]&~x);
assign w1= (~Q[0]&Q[1]&~Q[2]&x)|(Q[0]&Q[2]&x)|(~Q[0]&~Q[1]&Q[2]&~x);
assign w2= (~Q[1]&~Q[2]&x)|(~Q[0]&x);
assign y=(Q[0]&Q[1]&~Q[2]&~x);
dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedgeclk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule
2.Behavioural module coding:
module mealy71(
input clk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end
always @(posedge clk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0100; end
4'b0011: begin {state,y}=4'b0010; end
4'b0100: begin {state,y}=4'b0000; end
4'b0101: begin {state,y}=4'b0110; end

16
4'b0110: begin {state,y}=4'b1000; end
4'b0111: begin {state,y}=4'b0010; end
4'b1000: begin {state,y}=4'b0000; end
4'b1001: begin {state,y}=4'b1010; end
4'b1010: begin {state,y}=4'b1000; end
4'b1011: begin {state,y}=4'b1100; end
4'b1100: begin {state,y}=4'b0001; end
4'b1101: begin {state,y}=4'b0000; end
endcase
outstate=state;
end
endmodule

7bitOverlapping sequence using mealy machine:

1.Dataflow module coding :
module datamealy72(input clk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;
assign w0= (Q[0]&~Q[1]&x)|(Q[0]&Q[2])|(Q[1]&Q[2]&~x);
assign w1=
(~Q[0]&~Q[1]&Q[2]&~x)|(~Q[0]&Q[1]&~Q[2]&x)|(Q[0]&Q[2]&~x)|(Q[0]&Q[1]&Q[2]);
assign w2= (~Q[2]&x)|(~Q[0]&x)|(Q[2]&x);

assign y=(Q[0]&Q[1]&~Q[2]&~x);

dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedge clk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule

2.Behavioural module coding:

module mealy72(
input clk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end

17
always @(posedgeclk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0100; end
4'b0011: begin {state,y}=4'b0010; end
4'b0100: begin {state,y}=4'b0000; end
4'b0101: begin {state,y}=4'b0110; end
4'b0110: begin {state,y}=4'b1000; end
4'b0111: begin {state,y}=4'b0010; end
4'b1000: begin {state,y}=4'b0000; end
4'b1001: begin {state,y}=4'b1010; end
4'b1010: begin {state,y}=4'b1000; end
4'b1011: begin {state,y}=4'b1100; end
4'b1100: begin {state,y}=4'b0101; end
4'b1101: begin {state,y}=4'b0010; end
endcase
outstate=state;
end
endmodule

7 bitNon Overlapping sequence using moore machine:

1.Dataflow module coding :
module datamoore71( inputclk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;
assign w0=
(Q[0]&Q[1]&~Q[2]&~x)|(Q[0]&~Q[1]&x)|(Q[0]&~Q[1]&Q[2])|(~Q[0]&Q[1]&Q[2]&~x);
assign w1=
(Q[0]&Q[1]&~Q[2]&~x)|(~Q[0]&Q[1]&~Q[2]&x)|(~Q[0]&~Q[1]&Q[2]&~x)|(Q[0]&~Q[1]&Q
[2]&x);
assign w2= (Q[0]&Q[1]&~Q[2])|(~Q[0]&x)|(Q[1]&x)|(Q[0]&~Q[2]&x);
assign y=(Q[0]&Q[1]&Q[2]);

dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
18
initial begin Q=1'b0; end
always@(posedge clk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule

2.Behavioural module coding:

module morre71( inputclk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end
always @(posedge clk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0100; end
4'b0011: begin {state,y}=4'b0010; end
4'b0100: begin {state,y}=4'b0000; end
4'b0101: begin {state,y}=4'b0110; end
4'b0110: begin {state,y}=4'b1000; end
4'b0111: begin {state,y}=4'b0010; end
4'b1000: begin {state,y}=4'b0000; end
4'b1001: begin {state,y}=4'b1010; end
4'b1010: begin {state,y}=4'b1000; end
4'b1011: begin {state,y}=4'b1100; end
4'b1100: begin {state,y}=4'b1110; end
4'b1101: begin {state,y}=4'b0010; end
4'b1110: begin {state,y}=4'b0001; end
4'b1111: begin {state,y}=4'b0011; end
endcase
outstate=state;
end
endmodule

7 bit Overlapping sequence using moore machine:

1.Dataflow module coding :
module datamoore72( input clk, input clr, input x,
output [0:2] Q, output y
);
wire w0,w1,w2;

19
assign w0=
(Q[0]&Q[1]&~Q[2]&~x)|(Q[0]&~Q[1]&x)|(Q[0]&~Q[1]&Q[2])|(~Q[0]&Q[1]&Q[2]&~x);
assign w1=
(Q[0]&Q[2]&x)|(Q[0]&Q[1]&~Q[2]&~x)|(~Q[0]&Q[1]&~Q[2]&x)|(~Q[0]&~Q[1]&Q[2]&~x);
assign w2= (Q[0]&Q[1]&~Q[2])|(Q[0]&~Q[2]&x)|(Q[1]&x)|(~Q[0]&x);

assign y=(Q[0]&Q[1]&Q[2]);

dff f0(clk,clr,w0,Q[0]);
dff f1(clk,clr,w1,Q[1]);
dff f2(clk,clr,w2,Q[2]);
endmodule
module dff(input clk,inputclr, input d,outputreg Q);
initial begin Q=1'b0; end
always@(posedge clk)
if (clr)
Q<=1'b0;
else
Q<=d;
endmodule

2.Behavioural module coding:

module moore72( inputclk, input x, output reg y,
output reg [2:0] outstate
);
reg [2:0] state;
initial begin {state,y}=4'b0000; end
always @(posedge clk)
begin
casex ({state,x})
4'b0000: begin {state,y}=4'b0000; end
4'b0001: begin {state,y}=4'b0010; end
4'b0010: begin {state,y}=4'b0100; end
4'b0011: begin {state,y}=4'b0010; end
4'b0100: begin {state,y}=4'b0000; end
4'b0101: begin {state,y}=4'b0110; end
4'b0110: begin {state,y}=4'b1000; end
4'b0111: begin {state,y}=4'b0010; end
4'b1000: begin {state,y}=4'b0000; end
4'b1001: begin {state,y}=4'b1010; end
4'b1010: begin {state,y}=4'b1000; end
4'b1011: begin {state,y}=4'b1100; end
4'b1100: begin {state,y}=4'b1110; end
4'b1101: begin {state,y}=4'b0010; end
4'b1110: begin {state,y}=4'b0001; end
4'b1111: begin {state,y}=4'b0111; end
endcase

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outstate=state;
end
endmodule

RTL Schematics:
(a) RTL Schematics for Sequence 1101:

Fig 14.17 RTL Schematics of 1101 using mealy machine of non overlapping type sequence

Fig 14.18 RTL Schematics of 1101 using mealy machine of overlapping type sequence

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 Fig 14.19 RTL Schematics of 1101 using moore machine of nonoverlapping type sequence

Fig 14.20 RTL Schematics of 1101 using moore machine of overlapping type sequence

(b) RTL Schematics Sequence 1010110:

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Fig 14.21 RTL Schematics of 1010110 using mealy machine of non overlapping type sequence

Fig 14.22 RTL Schematics of 1010110using mealy machine of overlapping type sequence

Fig 14.23 RTL Schematics of 1010110using moore machine of non overlapping type sequence

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 Fig 14.24 RTL Schematics of 1010110using moore machine of overlapping type sequence

Test bench:
Test bench for Sequence 1101:

1.Test bench for dataflow module coding:

initial clk=1'b0;
always #25 clk=(~clk);
initial begin clr=0;
x=1;#50; x=0;#50; x=1;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=0;#50;
x=1;#50; x=0;#50; x=0;#50; x=1;#50;
x=1;#50; x=1;#50; x=0;#50; x=0;#50;
#140;
clr=1;
#60;
clr=0;
x=1;#50; x=0;#50; x=0;#50; x=1;#50; x=1;#50;
x=0;#50; x=1;#50; x=0;#50;
end
endmodule

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2.Test bench for behavioural module coding:
initial clk=1'b0;
always #25 clk=(~clk);
initial begin
x=1;#50; x=0;#50; x=1;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
end
endmodule
Test bench for Sequence 1010110:
1.Test bench for dataflow module coding:
initial clk=1'b0;
always #25 clk=(~clk);
initial begin
clr=0;
x=0;#50; x=1;#50; x=0;#50; x=1;#50;
x=1;#50; x=0;#50; x=1;#50; x=0;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=1;#50; x=0;#50; x=1;#50; x=0;#50;
#140;
clr=1;
#60;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=1;#50; x=0;#50; x=1;#50; x=0;#50;
end
endmodule

2.behavioural module coding:

initial clk=1'b0;
always #25 clk=(~clk);
initial begin
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=1;#50; x=0;#50; x=1;#50; x=0;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
x=1;#50; x=1;#50; x=0;#50; x=1;#50;
x=0;#50; x=1;#50; x=1;#50; x=1;#50;
x=1;#50; x=0;#50; x=1;#50; x=0;#50;
end
endmodule

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Output waveform:
(a) Output waveform of sequence 1101:

Fig 14.25Output waveform of 1101 sequence using mealy machine for both overlapping and
nonoverlapping type

Fig 14.26 Output waveform of 1101 sequence using moore machine for both overlapping and
nonoverlapping type

(b) Output waveform of sequence 1010110:

Fig 14.27 Output waveform of 1010110 sequence using mealy machine for both overlapping and
nonoverlapping type

Fig 14.28 Output waveform of 1010110 sequence using moore machine for both overlapping and
nonoverlapping type

Result:sequence detector for mealay and moore sequences 1101 and 101011 is done successfully
with both overlapping and non overlapping type. The output is observed and number of
occurrences in stream of sequence is counted with help of counter. Verilog code is written and
verified for this state diagram.

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.

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