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ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays
ULN200x, ULQ200x High-Voltage, High-Current Darlington Transistor Arrays
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ULN2002A, ULN2003A, ULN2003AI
ULQ2003A, ULN2004A, ULQ2004A
SLRS027O – DECEMBER 1976 – REVISED JANUARY 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 7 Parameter Measurement Information ................ 10
2 Applications ........................................................... 1 8 Detailed Description ............................................ 12
3 Description ............................................................. 1 8.1 Overview ................................................................. 12
4 Revision History..................................................... 2 8.2 Functional Block Diagrams ..................................... 12
5 Pin Configuration and Functions ......................... 3 8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Application and Implementation ........................ 14
6.2 ESD Ratings.............................................................. 4 9.1 Application Information............................................ 14
6.3 Recommended Operating Conditions....................... 4 9.2 Typical Application ................................................. 14
6.4 Thermal Information .................................................. 4 9.3 System Examples ................................................... 17
6.5 Electrical Characteristics: ULN2002A ....................... 5 10 Power Supply Recommendations ..................... 18
6.6 Electrical Characteristics: ULN2003A and 11 Layout................................................................... 18
ULN2004A.................................................................. 5 11.1 Layout Guidelines ................................................. 18
6.7 Electrical Characteristics: ULN2003AI ...................... 6 11.2 Layout Example .................................................... 18
6.8 Electrical Characteristics: ULN2003AI ..................... 6 12 Device and Documentation Support ................. 19
6.9 Electrical Characteristics: ULQ2003A and 12.1 Documentation Support ........................................ 19
ULQ2004A ................................................................. 7
12.2 Related Links ........................................................ 19
6.10 Switching Characteristics: ULN2002A, ULN2003A,
12.3 Community Resources.......................................... 19
ULN2004A.................................................................. 7
12.4 Trademarks ........................................................... 19
6.11 Switching Characteristics: ULN2003AI .................. 7
12.5 Electrostatic Discharge Caution ............................ 19
6.12 Switching Characteristics: ULN2003AI .................. 8
12.6 Glossary ................................................................ 19
6.13 Switching Characteristics: ULQ2003A, ULQ2004A 8
6.14 Typical Characteristics ............................................ 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Deleted Ordering Information table. No specification changes. ............................................................................................. 1
• Moved Typical Characteristics into Specifications section. ................................................................................................... 8
• Updated temperature rating for ULN2003AI in the ORDERING INFORMATION table ........................................................ 1
1B 1 16 1C
2B 2 15 2C
3B 3 14 3C
4B 4 13 4C
5B 5 12 5C
6B 6 11 6C
7B 7 10 7C
E 8 9 COM
Pin Functions
PIN
I/O (1) DESCRIPTION
NAME NO.
1B 1
2B 2
3B 3
4B 4 I Channel 1 through 7 Darlington base input
5B 5
6B 6
7B 7
1C 16
2C 15
3C 14
4C 13 O Channel 1 through 7 Darlington collector output
5C 12
6C 11
7C 10
COM 9 — Common cathode node for flyback diodes (required for inductive loads)
E 8 — Common emitter shared by all channels (typically tied to ground)
6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted) (1)
MIN MAX UNIT
VCC Collector-emitter voltage 50 V
(2)
Clamp diode reverse voltage 50 V
VI Input voltage (2) 30 V
Peak collector current, See Figure 4 and Figure 5 500 mA
IOK Output clamp current 500 mA
Total emitter-terminal current –2.5 A
ULN200xA –20 70
ULN200xAI –40 105
TA Operating free-air temperature range °C
ULQ200xA –40 85
ULQ200xAT –40 105
TJ Operating virtual junction temperature 150 °C
Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
2.5 2.5
TA = 25°C TA = 25°C
II = 250 µA
2 2
II = 250 µA II = 350 µA
II = 350 µA
1.5 II = 500 µA 1.5
II = 500 µA
1 1
0.5 0.5
VCE(sat)
VCE(sat)
0 0
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800
IC - Collector Current - mA IC(tot) - Total Collector Current - mA
VS = 10 V
350 N=1
400 N=4
VS = 8 V
300 N=3
250 300
N=2
200
N=6
200 N = 7
150
N=5
IC
100
100 TA = 70°C
IIC
50 N = Number of Outputs
Conducting Simultaneously
0 0
0 25 50 75 100 125 150 175 200 0 10 20 30 40 50 60 70 80 90 100
II - Input Current - µA Duty Cycle - %
Figure 3. Collector Current vs Input Current Figure 4. D Package Maximum Collector Current
vs Duty Cycle
600 2000
TJ = -40°C to 105°C
1800
C - Maximum Collector Current - mA
500
1600
N=2 N=1
N=3 1400
Input Current – µA
400
N=4
1200
400
100 TA = 85°C Typical
IIC
Figure 5. N Package Maximum Collector Current Figure 6. Maximum and Typical Input Current
vs Duty Cycle vs Input Voltage
2.1 500
TJ = -40°C to 105°C V CE = 2 V
450 TJ = -40°C to 105°C
1.9
Maximum VCE(sat) Voltage – V
400
Output Current – mA
1.7
350
250
1.3
Minimum
200
1.1
150
Typical
0.9 100
100 200 300 400 500 250 350 450 550 650
Output Current – mA Input Current – µA
Figure 7. Maximum and Typical Saturated VCE Figure 8. Minimum Output Current vs Input Current
vs Output Current
ICEX ICEX
Open VI
II(off) IC II(on)
VI Open
IC
hFE =
II
Figure 13. hFE, VCE(sat) Test Circuit Figure 14. VI(on) Test Circuit
IR VF IF
Open
Open
200 W
≤5 ns ≤10 ns
VIH
Input 90% 90% (see Note C)
1.5 V 1.5 V
10% 10%
40 µs 0V
VOH
Output
VOL
VOLTAGE WAVEFORMS
The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
CL includes probe and jig capacitance.
For testing the ULN2003A device, ULN2003AI device, and ULQ2003A devices, VIH = 3 V; for the ULN2002A device,
VIH = 13 V; for the ULN2004A and the ULQ2004A devices, VIH = 8 V.
8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The ULN2003A device comprises seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULN2003A device has a series base resistor to each Darlington pair,
thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2003A
device offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and
LEDs. Applications requiring sink currents beyond the capability of a single output may be accommodated by
paralleling the outputs.
This device can operate over a wide temperature range (–40°C to 105°C).
COM
Output C
7V 10.5 NŸ
Input B
7.2 NŸ 3 NŸ E
COM COM
RB Output C RB Output C
2.7 NŸ 10.5 NŸ
Input B Input B
7.2 NŸ 3 NŸ E 7.2 NŸ 3 NŸ E
Figure 20. ULN2003A, ULQ2003A and ULN2003AI Figure 21. ULN2004A and LQ2004A Block Diagram
Block Diagram
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
IN1 OUT1
IN2 OUT2
IN4 OUT4
VSUP
IN6 OUT6
IN7 OUT7
For a more accurate determination of number of coils possible, use the below equation to calculate ULN2003A
device on-chip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
where
• N is the number of channels active together
• VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT) (2)
To ensure reliability of ULN2003A device and the system, the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 3.
PD(MAX) =
(T J(MAX) - TA )
qJA
where
• TJ(max) is the target maximum junction temperature
• TA is the operating ambient temperature
• RθJA is the package junction to ambient thermal resistance (3)
Limit the die junction temperature of the ULN2003A device to less than 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
13 14
12
11 12
10
9 10
Output voltage - V
Output voltage - V
8
8
7
6
6
5
4 4
3
2 2
1
0 0
-0.004 0 0.004 0.008 0.012 0.016 -0.004 0 0.004 0.008 0.012 0.016
Time (s) D001
Time (s) D001
Figure 23. Output Response With Activation of Coil Figure 24. Output Response With De-activation of Coil
(Turnon) (Turnoff)
1 16 1 16
2 15 2 15
3 14
3 14
4 13
4 13
5 12
5 12
6 11
6 11 10
7
7 10 8 9
P-MOS
Output Lam
8 9 Test
TTL
Output
1 16 1 16
2 15 2 15
3 14 3 14
RP
4 13 4 13
5 12 5 12
6 11 6 11
7 10 7 10
8 9 8 9
CMOS
Output
TTL
Output
Figure 27. Buffer for Higher Current Loads Figure 28. Use of Pullup Resistors to Increase
Drive Current
11 Layout
1B 1 16 1C
2B 2 15 2C
3B 3 14 3C
4B 4 13 4C
5B 5 12 5C
6B 6 11 6C
7B 7 10 7C
E 8 9 VCOM
GND
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 15-Apr-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ULN2002AN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -20 to 70 ULN2002AN
(RoHS)
ULN2002ANE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -20 to 70 ULN2002AN
(RoHS)
ULN2003AD ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADE4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADRG3 ACTIVE SOIC D 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003AID ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIDE4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIDG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIDR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIDRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU | CU SN N / A for Pkg Type -40 to 105 ULN2003AIN
(RoHS)
ULN2003AINE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 105 ULN2003AIN
(RoHS)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ULN2003AINSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 ULN2003AI
& no Sb/Br)
ULN2003AIPW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 UN2003AI
& no Sb/Br)
ULN2003AIPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 UN2003AI
& no Sb/Br)
ULN2003AIPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 UN2003AI
& no Sb/Br)
ULN2003AIPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 105 UN2003AI
& no Sb/Br)
ULN2003AIPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 105 UN2003AI
& no Sb/Br)
ULN2003AN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU | CU SN N / A for Pkg Type -20 to 70 ULN2003AN
(RoHS)
ULN2003ANE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -20 to 70 ULN2003AN
(RoHS)
ULN2003ANSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2003A
& no Sb/Br)
ULN2003APW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 UN2003A
& no Sb/Br)
ULN2003APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 UN2003A
& no Sb/Br)
ULN2003APWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -20 to 70 UN2003A
& no Sb/Br)
ULN2003APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 UN2003A
& no Sb/Br)
ULN2004AD ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULN2004ADE4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULN2004ADG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ULN2004ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULN2004ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULN2004ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULN2004AN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -20 to 70 ULN2004AN
(RoHS)
ULN2004ANE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -20 to 70 ULN2004AN
(RoHS)
ULN2004ANSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -20 to 70 ULN2004A
& no Sb/Br)
ULQ2003AD ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2003A
& no Sb/Br)
ULQ2003ADG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM ULQ2003A
& no Sb/Br)
ULQ2003ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2003A
& no Sb/Br)
ULQ2003ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM ULQ2003A
& no Sb/Br)
ULQ2003AN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 ULQ2003A
(RoHS)
ULQ2004AD ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2004A
& no Sb/Br)
ULQ2004ADG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM ULQ2004A
& no Sb/Br)
ULQ2004ADR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ULQ2004A
& no Sb/Br)
ULQ2004ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM ULQ2004A
& no Sb/Br)
ULQ2004AN ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 ULQ2004AN
(RoHS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2016
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2016
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ULN2004ADR SOIC D 16 2500 367.0 367.0 38.0
ULN2004ADR SOIC D 16 2500 333.2 345.9 28.6
ULN2004ADR SOIC D 16 2500 364.0 364.0 27.0
ULN2004ADRG4 SOIC D 16 2500 367.0 367.0 38.0
ULN2004ADRG4 SOIC D 16 2500 333.2 345.9 28.6
ULQ2003ADR SOIC D 16 2500 333.2 345.9 28.6
ULQ2003ADRG4 SOIC D 16 2500 367.0 367.0 38.0
Pack Materials-Page 3
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