Scribd Logo
Upload

Welcome to Scribd!

  • Dsd&Dica Lab External Q.paper

    Uploaded by

    LALRAZ
    16 views1 page
    This document outlines 11 experiments for a lab internal examination in digital electronics and communication engineering. The experiments involve writing VHDL programs to implement basic logic gates, a full adder, a 3 to 8 decoder, an 8x1 multiplexer, and other digital circuits. Students are asked to both simulate and verify the results on a Spartan 3S FPGA kit.

    Original Description:

    lets wait

    Original Title

    Dsd&Dica Lab External q.paper

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document outlines 11 experiments for a lab internal examination in digital electronics and communication engineering. The experiments involve writing VHDL programs to implement basic logic gates, a full adder, a 3 to 8 decoder, an 8x1 multiplexer, and other digital circuits. Students are asked to both simulate and verify the results on a Spartan 3S FPGA kit.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    16 views1 page

    Dsd&Dica Lab External Q.paper

    Uploaded by

    LALRAZ
    This document outlines 11 experiments for a lab internal examination in digital electronics and communication engineering. The experiments involve writing VHDL programs to implement basic logic gates, a full adder, a 3 to 8 decoder, an 8x1 multiplexer, and other digital circuits. Students are asked to both simulate and verify the results on a Spartan 3S FPGA kit.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 1

    Department of Electronics and Communication Engineering

    III B.TECH I Sem LAB INTERNAL EXAMINATION-OCT 2018(R-16)

    DICA Laboratory Date:

    1. Write a VHDL program and Implement Logic Gates(AND, OR, NOT) by using Spartan 3S FPGA Kit
    2. Write a VHDL program and Implement full adder by using Spartan 3S FPGA Kit
    3. Write a VHDL program and Implement 3 to 8 Decoder-741x38 by using Spartan 3S FPGA Kit
    4. Write a VHDL program and verify simulation results for 8x 1 Multiplexer-74x151
    5. Write a VHDL program and verify simulation results for 4- B it comparator-74x85
    6. Write a VHDL program and verify simulation results for DFlip-Rop-74x74
    7. Write a VHDL program and verify simulation results for Decade counter -74x90
    8. Write a VHDL program and verify simulation results for 4 Bit counter-74x93
    9. Write a VHDL program and verify simulation results for Shift registers-74x95
    10. Write a VHDL program and verify simulation results for RAM (16 x 4)-74x189 for Read and Write
    operations
    11. Write a VHDL program and verify simulation results for ALU Design

    Examiner-1 Examiner-2

    You might also like